Pcb Layout Of The Eval-M1-2Ed2106S - Infineon EVAL-M1-2ED2106S User Manual

EVAL-M1-2ED2106S User Manual
2ED2106S06F drive board for BLDC motor

PCB layout of the EVAL-M1-2ED2106S

8 PCB layout of the EVAL-M1-2ED2106S
The layout details of the EVAL-M1-2ED2106S can be seen in Figure 14, Figure 15, Figure 16 and Figure 17,
respectively.
Some layout tips are indicated on this board:
• The power conductor paths such as DC+, GND, phase-out, etc. should be as thick as possible for a lower
temperature rise and lower parasitic inductances.
• The shunt resistor is SMD-preferred with the lowest parasitic inductance for a smaller negative V
switching.
• The shunt resistor should be located where the LO-COM drive loop is as small as possible.
• The link conductor path of the high-side IGBT-E and low-side IGBT-C should be as thick and short as
possible for a smaller parasitic inductance.
• The power ground and controller ground should be individually copper-filled (in the production process)
and then shorted at the return of the shunt resistor. In this way the LO-COM drive loop parasitic inductance
and the HIN/LIN-COM input signal loop parasitic inductance are both as small as possible (see Figure 15
and Figure 17).
• The V and V bypass capacitors should be close to the IC.
CC BS
• Current sensing should be connected directly at the shunt-resistor terminals and sent to the controller
interface as a differential pair.
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Revision 1.0
2019-09-18