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EVAL-M1-2ED2106S User Manual
2ED2106S06F drive board for BLDC motor
Circuit diagram of the EVAL-M1-2ED2106S
The typical OCP waveform is captured in Figure 11. The gate drive signals are terminated immediately after the
overcurrent event occurs.
CH1 – Shunt resistor voltage drop
CH2 – Low side IGBT V
CH3 –
High side IGBT V
CH4 – GK signal
Figure 11
Test result - OCP
The IGBT6 short-circuit capability is only 3 uS. Therefore in case of a short circuit, the IGBTs must be shut down
within the withstand time limitation. The total short-circuit protection (SCP) delay time is the sum of the
cascaded time interals as below:
•
Current sampling input filter time, which is set up by R55 and C29 with a time constant of 1 uS.
•
Comparator response time from the input step to the output GK flip-flop. Typical is 300 nS in this design.
•
MCU delay time from receiving the GK signal to disable the PWMs. Typical is 1.3 uS of the controller
IMC101T (t
, defined in data sheet).
GK
•
Gate driver's turn-off propogation delay time (t
•
The IGBT turn-off time, including the turn-off delay time t
gate resistor R
and the gate charge Q
goff
User Manual
GE
GE
OFF
of the IGBT. It is less than 200 nS on this board.
G
). Maximum is 300 nS of the 2ED2106S06F.
and fall time t
d(off)
16 of 29
, which is related to the turn-off
f
Revision 1.0
2019-09-18
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