Figure 4-16. Gpctr Timing Summary - National Instruments DAQ PCI-4451 User Manual

V
SOURCE IH
V
IL
V
GATE IH
V
IL
V
OH
OUT
V
OL
© National Instruments Corporation
t
gsu
t
out
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time

Figure 4-16. GPCTR Timing Summary

The GATE and OUT signal transitions shown in Figure 4-16 are referenced
to the rising edge of the SOURCE signal. This timing diagram assumes that
you programmed the counters to count rising edges. The same timing
diagram, but with the SOURCE signal inverted and referenced to the falling
edge of the SOURCE signal, would apply when you programmed the
counter to count falling edges.
The GATE input timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated signals on your
PCI-4451/4452. Figure 4-16 shows the GATE signal referenced to the
rising edge of a SOURCE signal. The GATE signal must be valid (either
high or low) for at least 10 ns before the rising or falling edge of a SOURCE
signal for the GATE to take effect at that SOURCE edge, as shown by t
and t in Figure 4-16. It is not necessary to hold the GATE signal after the
gh
active edge of the SOURCE signal is detected.
If you use an internal timebase clock, you cannot synchronize the GATE
signal with the clock. In this case, GATEs applied close to a SOURCE edge
take effect either on that SOURCE edge or on the next one. This
arrangement results in an uncertainty of one SOURCE clock period with
respect to unsynchronized gating sources.
t t
sp
sc
t
gh
t
gw
t 50 ns minimum
sc
23 ns minimum
t
sp
t 10 ns minimum
gsu
t 0 ns minimum
gh
t 10 ns minimum
gw
t 80 ns maximum
out
4-27 PCI-4451/4452/4453/4454 User Manual
Chapter 4 Signal Connections
t
sp
gsu