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Chapter 3
Hardware Overview
High-Speed Timing
Acquisition, Scaling, ROI
Scatter-Gather DMA Controllers
Bus Master PCI Interface
Board Configuration NVRAM
IMAQ PCI/PXI-1422 User Manual
The high-speed timing circuitry on the PCI/PXI-1422, built from
high-speed counters, allows you to specify or generate precise, real-time
control signals. You can map the output of this circuitry to a trigger line
to provide accurate pulses and pulse trains.
The acquisition, scaling, and region-of-interest (ROI) circuitry monitors
the incoming video signals and routes the active pixels to the multiple-tap
data formatter and SDRAM memory. The PCI/PXI-1422 can perform ROI
and scaling on all video lines and frames. Pixel and line scaling transfers
certain multiples (two, four, or eight) of pixels and lines to onboard
memory. In an ROI acquisition, you select an area within the acquisition
window to transfer to the PCI bus.
The PCI/PXI-1422 uses three independent onboard direct memory access
(DMA) controllers. The DMA controllers transfer data between the
onboard SDRAM memory buffers and the PCI bus. Each of these
controllers supports scatter-gather DMA, which allows the DMA controller
to reconfigure on-the-fly. Thus, the PCI/PXI-1422 can perform continuous
image transfers directly to either contiguous or fragmented memory
buffers.
The PCI/PXI-1422 implements the PCI interface with a National
Instruments custom application-specific integrated circuit (ASIC), the
PCI MITE. The PCI interface can transfer data at a maximum rate of
132 Mbytes/s in bus master mode. The PCI/PXI-1422 can generate
8-, 16-, and 32-bit memory read and write cycles, both single and multiple.
In slave mode, the PCI/PXI-1422 is a medium-speed decoder that accepts
both memory and configuration cycles. The interface logic ensures that the
PCI/PXI-1422 can meet PCI loading, driving, and timing requirements.
The PCI/PXI-1422 contains onboard nonvolatile RAM (NVRAM) that
configures all registers on power-up.
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