Clock Signals; Flash Memory; Sdram Memory - Digi ConnectCore XP 270 Hardware Reference Manual

Clock signals

The processor needs two clock signals:
The 13-MHz processor oscillator provides the primary clock source for the
PXA270 processor. The on-chip PLL frequency multipliers and several
peripheral modules use the processor oscillator as a reference. If the
application has not enabled the 32.768-kHz timekeeping oscillator, the
processor oscillator also drives the real-time clock (RTC) and power
manager.
The 32.768-kHz timekeeping oscillator is a low-power, low-frequency
oscillator that clocks the real-time clock (RTC) and power manager.
Both clock sources are used and implemented on the ConnectCore XP 270 module.

Flash memory

The ConnectCore XP 270 module support two Intel StrataFlash Flash Memory chips.
Each chip is 16-bit wide, making a whole 32-bit Flash Memory area. All accesses to
the flash memory are made with 32-bit words.
The Flash Memory chips are controlled by CS0#, so the module can support a
maximum of 64MB of memory. Flash Memory chips have an initial access speed of
120ns and a block sector size of 64-Kword (= 128-Kbyte).
The Flash Memories reset signal is connected to the RESET_IN# input signal. With this
choice, Flash Memories aren't reset for software reset events such as sleep mode,
watchdog reset, and GPIO reset.

SDRAM memory

Intel PXA270 processor supports a SDRAM interface at a maximum frequency of 104
MHz. On the ConnectCore XP 270 module, two SDRAM memory chips have been
connected to the processor SDRAM partition 0 (controlled by SDCS0# signal).
There are two possible considerations regarding the size of SDRAM partition on a
PXA270-based product:
Use a normal 256-Mbyte memory map; in this case, the SDRAM partition is
64-Mbyte wide.
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