3. FUNCTIONAL DESCRIPTION
3.1
Block Diagram
The CS98000 block is shown in Figure 8.
3.2
CS98000 Device Details
3.2.1
RISC-32
•
Powerful 32-bit RISC processor
•
Virtual memory support
•
Optimizing C compiler and source level debug-
ger
•
Big or little endian data formats support
•
MAC multiply/accumulate in 2 cycles with C
support.
•
4 Kbyte instruction cache, 2 Kbyte data cache.
•
Single cycle instructions, runs at 81 Mhz.
10
RISC-1
Instruction
Data
Cache
Cache
MMU
MAC
MPEG Decoder
VLC Parser
IDCT
Motion
RAM
Comp
System Sync
STC
Interrupts
External Interface
Serial Interface
Programmable I/O
Infrared Input
DVD
ATAPI / LBUS Interface
Figure 8. CS98000 Block Diagram
3.2.2
DSP-32
•
Powerful 24/32 bit DSP processor
•
24 bit fixed point logic, with 54 bit accumula-
tor.
•
Single-cycle throughput, 2 cycle latency multi-
ply accumulate, 32 bit simple integer logic.
8 Kbyte instruction cache, 8 Kbyte program
visible local memory
•
Single cycle instructions, runs at 81 Mhz.
3.2.3
System Controls
•
Include several hardware lockable semaphore
registers
•
General-purpose register for inter-processor
communication
•
32-bit timers for I/O and other uses, with pro-
grammable interval rates
RISC-2
Instruction
Data
Cache
Cache
MMU
MAC
System Controls
Registers
Instruction
Cache
PLL
Subpicture Decoder
Dataflow Engine
Decoder
DMA / BitBlit
Video Processor
SRAM Buffer
On-Screen Display
Picture-in-Picture
Memory Controller
Video / Graphics Display
SDRAM Control
FLASH Control
Filter
Audio Interface
PCM Out
PCM In
SPDIF Out
DSP
X,Y Data
Memory
CPU / MAC
Scaler
Video Input
Scaler
CS98000
DS525PP1
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