Avtech AVR-8F-B-P-ADB1A Instructions Manual page 22

TRIG
(external input)
SYNC OUT
MAIN OUTPUT
As before, if the delay is negative, the order of the SYNC and OUT pulses is reversed.
The last figure illustrates the relationship between the signal when an external TTL-level
trigger is used in the PW
external trigger's pulse width (approximately), and the delay circuit is bypassed:
TRIG
(external input)
MAIN OUTPUT
The delay, pulse width, and frequency (when in the internal mode), of the OUT pulse
can be varied with front panel controls or via the GPIB or RS-232 computer interfaces.
> 50 ns
PROPAGATION DELAY (FIXED)
100 ns, FIXED
DELAY > 0
Figure C
=PW mode. In this case, the output pulse width equals the
IN OUT
PW
IN
PROPAGATION DELAY (FIXED)
PW ≈ PW
OUT IN
Figure D
TTL LEVELS
(0V and 3V-5V)
3V, FIXED
PULSE WIDTH
TTL LEVELS
(0V and 3V-5V)
22
AMPLITUDE,
VARIABLE
AMPLITUDE,
VARIABLE