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Cypress S6J3200 Series Manual

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Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
Page 2 32-bit Microcontroller  Traveo Family S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 www.cypress.com...
Page 3 High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device.
Page 4 Preface Thank you for your continued use of Cypress semiconductor products. Read this manual and "Data Sheet" thoroughly before using products in this family. Purpose of This Manual and Intended Readers This manual explains the functions and operations of this family and describes how it is used. The manual is intended for engineers engaged in the actual development of products using this family.
Page 5 Spread Spectrum Clock Generator (SSCG) ............59 Remark ..........................60 CHAPTER 6: Operation Mode ......................61 Overview ..........................62 Configuration ........................62 Registers ..........................62 CHAPTER 7: Memory and Base Address Map .................. 63 Memory Map......................... 64 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 6 Configuration and Block Diagram ..................239 Operation ..........................240 3.1. LVD operation ....................... 240 3.2. Configurations ...................... 240 Registers ..........................241 Electric Characteristics ....................... 244 CHAPTER 14: Serial Programming ....................245 Overview ..........................246 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 7 5.10. Group Interrupted Interrupt Clear Registers (ADC12Bn_GRPIRQC0 to 1) ..317 5.11. Range Comparator Interrupt Flag Registers (ADC12Bn_RCIRQ0 to 1) ....319 5.12. Range Comparator Interrupt Enable Registers (ADC12Bn_RCIRQE0 to 1) ..323 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 8 CHAPTER 17: Trigger Configuration of Stepper Motor Controller ............. 399 Overview ..........................400 Configuration and Block Diagram ..................400 Operation ..........................401 Registers ..........................401 4.1. SMC Trigger Selection Register (SMCTGg_PTRGS) ........... 402 4.2. SMC Trigger Register (SMCTGg_PTRG) ............. 405 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 9 Waveform Generator Channel n Control Register1 (WGCHnCTRL1, n=0 to 4) ..........................479 4.8. Waveform Generator Channel n Control Register2 (WGCHnCTRL2, n=0 to 4) ..........................483 4.9. Waveform Generator Channel n Control Register3 (WGCHnCTRL3, n=0 to 4) ..........................485 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 10 4.26. Mixer AHB Bus Error Register (MXAHBERR) ............559 4.27. Mixer WFGn Data Address Register (MXWFGnDADR, n=0 to 4) ......562 4.28. Mixer PCM/I2S n Data Address Register0-15 (MXPMISnDADR0-15, n=0 to 4) ... 563 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 11 4.23. Specific Address Top i Register (ETHERNETn_spec_add_top_i) (i=1 to 4) ..674 4.24. Type ID Match i Register (ETHERNETn_spec_type_i) (i= 1 to 4) ......676 4.25. IPG Stretch Register (ETHERNETn_stretch_ratio) ..........677 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 12 4.54. Transmit Under Runs Register (ETHERNETn_tx_underruns) ......709 4.55. Single Collision Frames Register (ETHERNETn_single_collisions) ..... 710 4.56. Multiple Collision Frames Register (ETHERNETn_multiple_collisions) ....711 4.57. Excessive Collisions Register (ETHERNETn_excessive_collisions) ....712 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 13 4.93. PTP Event Frame Transmitted Seconds [31:0] Register (ETHERNETn_tsu_ptp_tx_sec) ................750 4.94. PTP Event Frame Transmitted Nanoseconds Register (ETHERNETn_tsu_ptp_tx_nsec) ................751 4.95. PTP Event Frame Received Seconds [31:0] Register (ETHERNETn_tsu_ptp_rx_sec)................752 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 14 4.132. Interrupt Enable Queue i Register (ETHERNETn_int_enable_qi) (i=1 to 3) ..809 4.133. Interrupt Disable Queue i Register (ETHERNETn_int_disable_qi) (i=1 to 3) ..811 4.134. Interrupt Mask Queue i Register (ETHERNETn_int_mask_qi) (i=1 to 3) ....813 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 15 4.16. MediaLBn Local Channel Buffer Configuration Register (MLBn_LCBCR0 - MLBn_LCBCR15) ....................875 4.17. MediaLBn Module Identification Register (MLBn_MID) ........877 CHAPTER 23: Stereo Audio DAC ...................... 878 Overview ..........................879 Configuration and Block Diagram ..................879 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 16 Interrupt Control Register (I2Sn_INTCNT) ............943 4.10. Status Register (I2Sn_STATUS) ................947 4.11. DMA Activate Register (I2Sn_DMAACT) .............. 951 4.12. Debug Register (I2Sn_DEBUG) ................953 4.13. Module ID Register (I2Sn_MIDREG) ..............955 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 17 C/A Coder ......................1012 3.4. FIFO ........................1013 3.5. CS REG (Control Status Register) ..............1014 3.6. AXI Slave Interface ..................... 1015 Registers .......................... 1016 4.1. Controller Status Register (HYPERBUSIn_CSR) ..........1017 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 18 7.13. How can I Block the Current with the External Division Resistor When the LCD Stops? ........................ 1080 7.14. How can I Display/Non-display the LCD with Static Drive (ST0 to ST8)? ... 1081 Sample Program ....................... 1082 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 19 MPU AXI Write Error Control Register (MPUXn_WERRC) ......... 1150 4.4. MPU AXI Write Error Address Register (MPUXn_WERRA)........ 1151 4.5. MPU AXI Read Error Control Register (MPUXn_RERRC) ......... 1152 4.6. MPU AXI Read Error Address Register (MPUXn_RERRA) ........ 1153 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 20 Registers .......................... 1203 4.1. General ....................... 1203 4.2. SubSysCtrl ......................1207 4.3. Memory Protection Unit ..................1285 4.4. High Performance Bus Matrix ................1286 4.5. Bus Monitor ......................1287 References ........................1296 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 21 TEQFP-216 Pin ....................1315 1.2. TEQFP-208pin....................1316 DMA destination list ......................1317 Master Access Table ......................1321 CHAPTER 37: Major Changes ......................1326 Supplementary Information ....................1327 Revision History ..........................1348 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 22 Overview CHAPTER 1: This chapter explains the product overview. Overview Document Definition Register Attribute Abbreviation CODE: OVERVIEW-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 23 Traveo platform hardware manual is expected to be used as dictionary of platform specification. − Document code usually includes its revision. − Revise information from the previous revision can be seen the supplementary information. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 24 It can be read at the supervisor mode. It can be written at the supervisor mode. It can be written after cancelling the sequence protection. It can be written after cancelling the sequence protection at the supervisor mode. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 25 Boot Description Record Base Timer Bridge-Tied Load Control Area Network Clock Domain Central Processing Unit CR Oscillator Cyclic Redundancy Check Clock SuperVisor Digital Analog Converter Debug Access Port Dual Error Detection S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 26 Port Pin Configuration Power Supply Control Power Saving State Pulse Width Modulation Random Access Memory Resource Input Configuration Reload Timer Read Only Memory RSDS Reduced Swing Differential Signal Real Time Clock S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 27 Tightly Coupled Memory TCRAM RAM connected to TCM Timing Protection Unit Time Stamp Unit Up-down Counter Vectored Interrupt Controller VRAM Video RAM Watchdog Description Record Watchdog Timer Waveform Generator WorkFLASH Work FLASH Memory S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 28 Function List CHAPTER 2: This chapter explains the functions. Function List Optional Function CODE: FUNCTIONLIST-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 29 CHAPTER 2:Function List Function List The table shows the functions which are implemented in S6J3200 series. Table 1-1 Function Description Remark CPU core Arm Cortex R5F Available (Double precision and Single precision) Available Available Available Endian Little endian See 2.1 and AC...
Page 30 It equivalents to 128 message buffer per channel of CCAN module Ethernet AVB Option See 2.1 Media-LB (MOST25) Option See 2.1 Option LCD controller See 2.3 4COM x 32 SEG (Max) Indicator PWM 1 ch MPU for AHB 1 unit S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 31 They should be seen in the datasheet in detailed. − Target resolution of graphics is WVGA 800 x 480, WQVGA 480 x 272. − Target capture resolution of graphics is WVGA 800 x 480. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 32 *2 TCRAM: 128KB + System-RAM: 128KB 1) Please contact your Cypress sales representative to receive the customer information CI708-0001 2) Please contact your Cypress sales representative to receive the product errata notification PEN182201 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 33 Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support FPD-LINK is used for DRGB only. − HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 34 This table only shows the relations between the optional function and the part numbers. That is, all products are not necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 35 2048KB Function See the function digit table. Product series Digit Product type Graphic SoC Identifier: Automotive MCU *1 TEQFP-256 is a package option under planning. *2 TCRAM: 128KB + System-RAM: 384KB S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 36 Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support FPD-LINK is used for DRGB only. − HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 37 Analog input port (12bit-ADC) AN20 to AN49 (50 ports) (50 ports) (46 ports) SEG0 to SEG31 SEG0 to SEG31 SEG0 to SEG29 SEG port of LCD controller (32 ports) (32 ports) (30 ports) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 38 PPG triggered input PPG6/7/8/9/10/11_TIN PPG6/7/8/9/10/11_TIN PPG6/7/8/9/10/11_TIN Notes: − See multiplexed functions on pin assignment sheet. − The optional restriction will be added without notification. − TEQFP-256 is a package option under planning S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 39 Product Description CHAPTER 3: This chapter explains the function feature. Overview Product Description Note CODE: PRODUCT-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 40 CHAPTER 3:Product Description Overview This chapter explains the product features of S6J3200 series. The description of this chapter should precede the duplicated description on platform manual. Product Description The table shows features. Table 2-1 Feature Description 55nm CMOS technology with embedded FLASH...
Page 41 Protected peripherals are described in the base address map. See the platform manual in detail. Internal Memories 1 wait cycle is necessary for RAM read at over 160MHz. System RAM No need to insert wait cycles for RAM write. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 42 Multi input level and multi output drivability I/O Ports Pull-up, pull-down function is available. Resource input and output is multiplexed. +B input is allowed many pins of 3.3V, 5V and 3.3V/5V I/O domain. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 43 A unit consists of a pair of 16bit base timers. 12 units, that is, 24 channels of base timers are available. Reload Timer See the platform manual in detail. I/O Timer See the platform manual in detail. Quad Position & Revolution Counter See the platform manual in detail. (Up/Down Counter) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 44 See the "HyperBus Interface Port Configuration" of S6J3200 hardware manual in detail. Stepper Motor Control (SMC) Each channel has 4 motor drivers with high output capability External Interrupt Capture Unit See the platform manual in detail. (EICU) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 45 "Low": Request to stop supplying VCC12 - CPU transfers from RUN mode to PSS shutdown mode. For timing chart of output signals include PSC in detail, see the "S6J3200 hardware manual" and chapter "State Transition" S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 46 Trigger Configuration of Stepper Motor CHAPTER 17 RSTX_PD2 Controller Stepper Motor Controller" CHAPTER 18 RSTX_PD2 Sound Generator CHAPTER 19 RSTX_PD2 Sound Waveform Generator CHAPTER 20 RSTX_PD2 Sound Mixer CHAPTER 21 RSTX_PD2 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 47 *2 See the Sub CHAPTER "4.6. GDC Control Register (GDCCR)" in the "CHAPTER 30:FPD-Link Converter" about reset signal "GDCCR:GRST". − *3 See the Sub CHAPTER "3.1. Resource Input Configuration Module" in the "CHAPTER 11: Port Configuration" about reset signal "RIC_RESIN520:CAP0_RESET_N" S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 48 [15:0] Write(B,H,W) Bus error INTER IC SOUND (I2S) bit [31:24] Reserved I2Sn_DMAACT Write(B) Bus error bit [15:8] Reserved I2Sn_DEBUG bit [31:8] Reserved Write(B,H) Bus error I2Sn_MIDREG Whole register Write(B,H,W) Bus error S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 49 0 or 1 * See the note below. SYSC0_APPLVDCFGR LVDH1S R,WX SYSC0_APPLVDCFGR LVDH1V R,WX 0110 SYSC0_APPLVDCFGR LVDH1E R,WX SYSC0_APPLVDCFGR LVDH2S R,WX SYSC0_APPLVDCFGR LVDH2V R,WX 0000 SYSC0_APPLVDCFGR LVDH2E R,WX SYSC0_STSLVDCFGR LVDL1R R,WX S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 50 SYSC0_RUNLVDCFGR LVDH1S SYSC0_RUNLVDCFGR LVDH1V 0110 SYSC0_RUNLVDCFGR LVDH1E SYSC0_RUNLVDCFGR LVDH2S R1/W1 1 should be written. Prohibit setting 0. SYSC0_RUNLVDCFGR LVDH2V 0000 Less than or equal to 0x3 should be written. SYSC0_RUNLVDCFGR LVDH2E S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 51 SSCGCGEN SYSC_SSCG1CGCNTR SSCGCGLP 11111111 SYSC_SSCG1CGCNTR SSCGCGSTP SYSC_SSCG1CGCNTR SSCGCGSSN 000000 SYSC_SSCG1CGCNTR SSCGCGEN SYSC_SSCG2CGCNTR SSCGCGLP 11111111 SYSC_SSCG2CGCNTR SSCGCGSTP SYSC_SSCG2CGCNTR SSCGCGSSN 000000 SYSC_SSCG2CGCNTR SSCGCGEN SYSC_SSCG3CGCNTR SSCGCGLP 11111111 SYSC_SSCG3CGCNTR SSCGCGSTP SYSC_SSCG3CGCNTR SSCGCGSSN 000000 SYSC_SSCG3CGCNTR SSCGCGEN S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 52 Configure them as same as PD2 As for PD3 related registers, Power SYSC0_PSSPDCFGR.PD5_xEN registers because PD5 is a sub power they are specified as (R1, domain SYSC0_APPPDCFGR.PD5_xEN domain of PD2. WX). SYSC0_STSPDCFGR.PD5_xEN S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 53 Block Diagram CHAPTER 4: This chapter explains the block diagram. Block Diagram Note CODE: BLOCK_DIAGRAM-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 54 Always ON Domain (PD1) Backup RAM_0 (PD4_0) Peripherals (PD2) Timer & Comm (PD6) Backup RAM_1 (PD4_1) General nested in PD1 Secure Bridge purpose communicati Debug I/F Debug Group - Coresight Note No description. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 55 Clock Configuration CHAPTER 5: This chapter explains the clock configuration. Overview Operation Remark CODE: CLOCK_SYSTEM-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 56 PLL2 It is described as "PWM_CLK" in the chapter of PCMPWM. PCM-PWM CLK_CD5B0 PLL3 See Traveo Platform hardware manual CLK_CD5 Sound waveform CLK_CD5A0 PLL3 See Traveo Platform hardware manual generator CLK_CD5B0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 57 External input Inter IC Sound (I2S0/I2S1) clock clock External input External input Inter IC Sound (I2S0/I2S1) ECLK clock clock External input External input Media Local Bus Interface (MediaLB) MLBn_CLK clock clock S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 58 CLK_CD3A0 Graphics Subsystem No Define Graphics Core SSCG2 CLK_CD3A0 Hyperbus Interface (GDC) No Define Operation Clock for Control register SSCG2 CLK_CD3A0 Hyperbus Interface (GDC) No Define Operation Clock for Main controller S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 59 "handshake" for AXI transaction cannot be done. If you want to quit a clock generation for some clock domain, you also need to configure an access protection for the domain using MPU. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 60 Target frequency of SSCG should be referred in Datasheet.  Down Spread Mode Figure 2-1: Down Spread Mode Down Spread Mode Output clock frequency Cycle to cycle jitter Target Modulation Ratio Time Period 1/Modulation frequency S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 61 − The group name and its clock source are described in PLATFORM OVERVIEW Configuration. See Traveo Platform hardware manual. − Clock frequency can be seen in datasheet of S6J3200 series. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 62 Operation Mode CHAPTER 6: This chapter explains operation mode. Overview Configuration Registers CODE: MODE-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 63 User mode can be applied to Software debugging using JTAG interface with ICE. − As for serial programming, see the chapter of SERIAL PROGRAMMING on this manual. Registers See Traveo Platform hardware manual. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 64 Memory and Base Address Map CHAPTER 7: This chapter explains the memory map and the base address map of registers. Memory Map Base Address Map Note CODE: MEMORYMAP-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 65 Graphic subsystem 5021_1000 5021_13FF MPU_AXI( Blit Engine) (AppS #8) 5021_1400 5021_17FF MPU_AXI( Drawing Engine) 5021_1800 5021_1FFF Reserved 5021_2000 5021_23FF DDRHSSPI configuration 5021_2400 5021_3FFF Reserved 5021_4000 5021_43FF Reserved 5021_4400 5021_47FF AXI Interconnect(Error Monitor) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 66 FFFE_FFFF FFFF_0000 FFFF_FFFF BootROM Notes: − The sector configuration and end address of FLASH and RAM are described in the chapter of TCRAM, TCFLASH, and WorkFLASH of Traveo platform hardware manual. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 67 B058_FFFF DEBUG GROUP CR5_RomTable B059_0000 B059_1FFF DEBUG GROUP CORE0 B059_2000 B059_7FFF Reserved Reserved B059_8000 B059_8FFF DEBUG GROUP CTI#0 B059_9000 B059_BFFF Reserved Reserved B059_C000 B059_CFFF DEBUG GROUP ETM0 B059_D000 B05B_FFFF Reserved Reserved S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 68 MCU_CONFIG_GROUP M.F.Serial ch.16 B06A_8400 B06A_87FF MCU_CONFIG_GROUP M.F.Serial ch.17 B06A_8800 B06B_FFFF Reserved reserved B06C_0000 B06C_FFFF MCU_CONFIG_GROUP CAN_FD ch.5 B06D_0000 B06D_FFFF MCU_CONFIG_GROUP CAN_FD ch.6 B06E_0000 B06F_FFFF Reserved reserved B070_0000 B07F_FFFF Reserved Reserved (1MB) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 69 Common PERI #0 M.F.Serial ch.0 B480_0400 B480_07FF Common PERI #0 M.F.Serial ch.1 B480_0800 B480_0BFF Common PERI #0 M.F.Serial ch.2 B480_0C00 B480_0FFF Common PERI #0 M.F.Serial ch.3 B480_1000 B480_13FF Common PERI #0 M.F.Serial ch.4 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 70 B483_07FF Common PERI #0 Output Compare 1 B483_0800 B483_0BFF Common PERI #0 Output Compare 2 B483_0C00 B483_0FFF Common PERI #0 Output Compare 3 B483_1000 B483_13FF Common PERI #0 Output Compare 4 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 71 B489_83FF Common PERI #1 QPRC ch.8 B489_8400 B489_87FF Common PERI #1 QPRC ch.9 B489_8800 B489_FFFF Reserved Reserved B48A_0000 B48A_03FF Common PERI #1 FRT ch.8 B48A_0400 B48A_07FF Common PERI #1 FRT ch.9 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 72 (Covers B470_0000 -- B47F_FFFF) Bit RMW alias for CommonPERI#0 B780_0000 B7BF_FFFF Bit RMW alias (Covers B480_0000 -- B487_FFFF) Bit RMW alias for CommonPERI#1 B7C0_0000 B7FF_FFFF Bit RMW alias (Covers B488_0000 -- B48F_FFFF) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 73 PERI GROUP. On the other hand, this product series optionally has CAN 0 and 1 in Common PERI GROUP, and uniquely has enhanced CAN5 and 6 in MCU_CONFIG_GROUP. − PPU number 301 is same for SMIX, Audio-DAC, PCM-PWM, and I2S0. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 74 AppS area [B800_0000 to BFFF_FFFF] − Register area in SUBSYSTEM [5020_0000 to 5FFF_FFFF] MPU attribute "Device" or "Strongly Ordered" is required for accesses to areas below, in particular situation. − FLASH Memory (when writing commands) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 75 IRQ and NMI Map CHAPTER 8: This chapter explains IRQ and NMI map. IRQ Map NMI Map CODE: IRQMAP-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 76 MFS RX ch.16 IRC0_IRQPL10 : IRQPL40 IRC0_IRQVA40 MFS TX ch.16 IRC0_IRQPL10 : IRQPL41 IRC0_IRQVA41 MFS RX ch.17 IRC0_IRQPL10 : IRQPL42 IRC0_IRQVA42 MFS TX ch.17 IRC0_IRQPL10 : IRQPL43 IRC0_IRQVA43 44 to 45 Reserved S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 77 Reserved TCRAM IRC0_IRQPL27 : IRQPL110 IRC0_IRQVA110 Reserved BACKUP RAM IRC0_IRQPL28 : IRQPL112 IRC0_IRQVA112 113 to 115 Reserved IRC0_IRQPL29 : IRQPL116 IRC0_IRQVA116 CR CARIBRATION IRC0_IRQPL29 : IRQPL117 IRC0_IRQVA117 118 to 127 Reserved S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 78 IRC0_IRQVA176 FRT ch.1 IRC0_IRQPL44 : IRQPL177 IRC0_IRQVA177 FRT ch.2 IRC0_IRQPL44 : IRQPL178 IRC0_IRQVA178 FRT ch.3 IRC0_IRQPL44 : IRQPL179 IRC0_IRQVA179 FRT ch.4 IRC0_IRQPL45 : IRQPL180 IRC0_IRQVA180 FRT ch.5 IRC0_IRQPL45 : IRQPL181 IRC0_IRQVA181 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 79 IRC0_IRQPL58 : IRQPL232 IRC0_IRQVA232 QPRC ch.9 IRC0_IRQPL58 : IRQPL233 IRC0_IRQVA233 234 to Reserved IRQ1 of Input Capture 0 IRC0_IRQPL60 : IRQPL240 IRC0_IRQVA240 IRQ1 of Input Capture 1 IRC0_IRQPL60 : IRQPL241 IRC0_IRQVA241 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 80 DMAC RLT(ch.0,1,2,3 OR-ed) IRC0_IRQPL70 : IRQPL282 IRC0_IRQVA282 283 to Reserved DMAC Completion ch.8 IRC0_IRQPL71 : IRQPL285 IRC0_IRQVA285 DMAC Completion ch.9 IRC0_IRQPL71 : IRQPL286 IRC0_IRQVA286 DMAC Completion ch.10 IRC0_IRQPL71 : IRQPL287 IRC0_IRQVA287 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 81 IRC0_IRQPL85 : IRQPL342 IRC0_IRQVA342 SMC ch.4 IRC0_IRQPL85 : IRQPL343 IRC0_IRQVA343 SMC ch.5 IRC0_IRQPL86 : IRQPL344 IRC0_IRQVA344 345 to Reserved SG ch.0 IRC0_IRQPL86 : IRQPL347 IRC0_IRQVA347 SG ch.1 IRC0_IRQPL87 : IRQPL348 IRC0_IRQVA348 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 82 IRC0_IRQPL102 : IRQPL408 IRC0_IRQVA408 2D Graphics Core Display0 Sync1 IRC0_IRQPL102 : IRQPL409 IRC0_IRQVA409 2D Graphics Core Content Stream1 IRC0_IRQPL102 : IRQPL410 IRC0_IRQVA410 2D Graphics Core Safety Stream1 IRC0_IRQPL102 : IRQPL411 IRC0_IRQVA411 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 83 IRC0_IRQPL111 : IRQPL447 IRC0_IRQVA447 448 to Reserved MX_DMA_ERR_IRQ0 IRC0_IRQPL113 : IRQPL453 IRC0_IRQVA453 MX_DMA_ERR_IRQ1 IRC0_IRQPL113 : IRQPL454 IRC0_IRQVA454 MX_DMA_ERR_IRQ2 IRC0_IRQPL113 : IRQPL455 IRC0_IRQVA455 MX_DMA_ERR_IRQ3 IRC0_IRQPL114 : IRQPL456 IRC0_IRQVA456 MX_DMA_ERR_IRQ4 IRC0_IRQPL114 : IRQPL457 IRC0_IRQVA457 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 84 Graphics subsystem Memory Protection IRC0_NMIPL5 : NMIPL20 IRC0_NMIVA20 Graphics subsystem (VRAM) ECC Single Bit IRC0_NMIPL5 : NMIPL21 IRC0_NMIVA21 Error Detection MLB_MPU_NMI IRC0_NMIPL5 : NMIPL22 IRC0_NMIVA22 ETHERNET_MPU_NMI IRC0_NMIPL5 : NMIPL23 IRC0_NMIVA23 24 to 31 Reserved S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 85 DMA Channel Activation Factors CHAPTER 9: This chapter explains the DMA channel activation factors. Factors List Note CODE: DMAFACT-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 86 DMAC #0 Reload Timer 1 DMAC #0 Reload Timer 2 DMAC #0 Reload Timer 3 62 to 65 Reserved Reserved DDRHSSPI RX DDRHSSPI TX 69 to 72 Reserved Base Timer ch.0-0 Base Timer ch.1-0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 87 Base Timer ch.16-1 Base Timer ch.17-1 Base Timer ch.18-0 Base Timer ch.19-0 Base Timer ch.18-1 Base Timer ch.19-1 Base Timer ch.20-0 Base Timer ch.21-0 Base Timer ch.20-1 Base Timer ch.21-1 Base Timer ch.22-0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 88 MFS ch.9 TX MFS ch.10 RX MFS ch.10 TX MFS ch.11 RX MFS ch.11 TX MFS ch.12 RX MFS ch.12 TX 219 to 224 Reserved FRT ch.0 Match FRT ch.0 Zero S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 89 ICU pair ch.4-1 ICU pair ch.5-0 ICU pair ch.5-1 ICU pair ch.6-0 ICU pair ch.6-1 ICU pair ch.7-0 ICU pair ch.7-1 ICU pair ch.8-0 ICU pair ch.8-1 ICU pair ch.9-0 ICU pair ch.9-1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 90 323 to 337 Reserved Sound Generator 0 Sound Generator 1 Sound Generator 2 Sound Generator 3 342 to 355 Reserved ADC ch.0-0 ADC ch.0-1 ADC ch.0-2 ADC ch.0-3 360 to 363 Reserved S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 91 This product does not support 'm = 381 to 511'. Accessing to those number of DMAi_CMICICm is responded with bus error. See the platform manual and chapter DMA controller in detail. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 92 Port Description CHAPTER 10: This chapter explains port functions. Port Description List Remark CODE: PORT_DESCRIPTION-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 93 Mode Pin External capacity connection output pin JTAG_NTRST JTAG test reset input pin JTAG_TDO JTAG test data output pin JTAG_TDI JTAG test data input pin JTAG_TCK JTAG test clock input pin S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 94 ADC Analog 30 input pin AN31 ADC Analog 31 input pin AN32 ADC Analog 32 input pin AN33 ADC Analog 33 input pin AN34 ADC Analog 34 input pin AN35 ADC Analog 35 input pin S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 95 47, 77, 91, EINT6 External interrupt input pin 102, 128, 148, 106, 134, 154, 187, 46, 77, 129, 48, 79, 135, EINT7 External interrupt input pin 149, 160, 188 155, 166, 196 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 96 Multi-function serial ch.9 clock I/O pin 161, 188 167, 196 SCK10 Multi-function serial ch.10 clock I/O pin 164, 192 172, 200 SCK11 Multi-function serial ch.11 clock I/O pin 167, 198, 206 175, 206, 214 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 97 SCL17 C ch.17 clock I/O pin (MFS17_SCL) SDA4 C ch.4 serial data I/O pin (MFS4_SDA) SDA10 C ch.10 serial data I/O pin (MFS10_SDA) SDA12 C ch.12 serial data I/O pin (MFS12_SDA) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 98 61, 68, 102, PPG9_TOUT0 Base timer 18 output pin 132, 191 138, 199 31, 34, 68, 99, 31, 34, 70, PPG9_TOUT2 Base timer 19 output pin 133, 192 103, 139, 200 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 99 177, 208, 212 41, 142, 201, 41, 148, 169, OCU1_OTD0 Output compare 1 ch.0 output pin 209, 213 44, 149, 170, OCU1_OTD1 Output compare 1 ch.1 output pin 143, 202, 206 210, 214 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 100 39, 146, 167, ICU0_IN0 Input Capture 0 ch.0 input pin 170, 199 178, 207 40, 141, 162, 40, 147, 168, ICU0_IN1 Input Capture 0 ch.1 input pin 169, 200, 204 177, 208, 212 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 101 Input Capture 11 ch.0 input pin 138, 197 144, 205 38, 139, 160, 38, 145, 166, ICU11_IN1 Input Capture 11 ch.1 input pin SGA0 Sound generator ch.0 SGA output pin 90, 97, 164 93, 101, 172 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 102 TIN19 Reload timer ch.19 event input pin 51, 170 TIN32 Reload timer ch.32 event input pin 51, 164 53, 172 TIN33 Reload timer ch.33 event input pin 55, 166 57, 174 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 103 Ethernet pin RXDV Ethernet pin RXCLK Ethernet pin TXER Ethernet pin TXEN Ethernet pin TXCLK Ethernet pin Ethernet pin MDIO Ethernet pin MLBCLK MediaLB pin MLBDAT MediaLB pin MLBSIG MediaLB pin S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 104 Hyper Bus 1 Data 5 pin G_DQ6_1 Hyper Bus 1 Data 6 pin G_DQ7_1 Hyper Bus 1 Data 7 pin G_RWDS_1 Hyper Bus 1 RWDS pin #699 G_CK_2 Hyper Bus 2 clock output pin S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 105 LCDC Segment(Duty) Common Output Pin SEG0 LCDC Segment(Duty) Output Pin SEG1 LCDC Segment(Duty) Output Pin SEG2 LCDC Segment(Duty) Output Pin SEG3 LCDC Segment(Duty) Output Pin SEG4 LCDC Segment(Duty) Output Pin SEG5 LCDC Segment(Duty) Output Pin S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 106 86, 208 DSP0_CTRL5 Display 0 Control output pin DSP0_CTRL6 Display 0 Control output pin DSP0_CTRL7 Display 0 Control output pin DSP0_CTRL8 Display 0 Control output pin DSP0_CTRL9 Display 0 Control output pin S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 107 Display 0 RSDS Data output pin DSP0_DATA_D7- Display 0 RSDS Data output pin DSP0_DATA_D7+ Display 0 RSDS Data output pin DSP0_DATA_D8- Display 0 RSDS Data output pin DSP0_DATA_D8+ Display 0 RSDS Data output pin S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 108 Video Capture 0 Data input pin CAP0_DATA5 Video Capture 0 Data input pin CAP0_DATA6 Video Capture 0 Data input pin CAP0_DATA7 Video Capture 0 Data input pin CAP0_DATA8 Video Capture 0 Data input pin S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 109 General-Purpose I/O port P0_12 General-Purpose I/O port P0_13 General-Purpose I/O port P0_14 General-Purpose I/O port P0_15 General-Purpose I/O port P0_16 General-Purpose I/O port P0_17 General-Purpose I/O port P0_18 General-Purpose I/O port S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 110 General-Purpose I/O port P3_09 General-Purpose I/O port P3_10 General-Purpose I/O port P3_11 General-Purpose I/O port P3_12 General-Purpose I/O port P3_13 General-Purpose I/O port P3_14 General-Purpose I/O port P3_15 General-Purpose I/O port S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 111 General-Purpose I/O port P5_01 General-Purpose I/O port P5_02 General-Purpose I/O port P5_03 General-Purpose I/O port P5_04 General-Purpose I/O port P5_05 General-Purpose I/O port P5_06 General-Purpose I/O port P5_07 General-Purpose I/O port S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 112 The port description list shows the port function of description which is mounted and supported on the product. The function which is not described in this table is not supported and assured. − See the function list of the product as well. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 113 Port Configuration CHAPTER 11: This chapter explains the port configuration. Overview Configuration and Block Diagram Operation Registers Configuration Procedure Precautions CODE: PORTCONFIG-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 114 •The port output function configuration •The analog I/O setting •The input level setting •The output drive capacity setting See the common information of the registers on the hardware manual of Traveo Platform V3. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 115 ・”IO35RSTC” initializes all of the GPIO ports in VCC53 area. :SIZE Latch RESSEL[3:0] ・”Resource output data(enable)” from PowerDomain6 is latched by :RADR “HOLDIO_PD6”, the other signals are latched by “HOLDIO_PD2”. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 116 L (8-15) (0x0068) PORTS EL (0-7) PORTS (8-15) 80ns 80ns RESSE noise noise L (0-7) filter filter disable enable RIC_RE RESSE SIN093 SCL10 L (8-15) (0x00BA PORTS EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 117 L (8-15) (0x00D6) PORTS EL (0-7) PORTS (8-15) 80ns 80ns RESSE noise noise L (0-7) filter filter disable enable RESSE RIC_RE SIN108 SDA12 L (8-15) (0x00D8) PORTS EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 118 RIC_RE RESSE L (8-15) SIN003 SDA16 (0x0006) PORTS EL (0-7) PORTS (8-15) RESSE TOT48 TOT49 L (0-7) RESSE RIC_RE L (8-15) SIN004 MFS16_TRI PORTS (0x0008) GGER EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 119 L (0-7) RESSE RIC_RE L (8-15) MFS17_TRI SIN011 PORTS GGER (0x0016) EL (0-7) PORTS (8-15) RESSE L (0-7) RESSE RIC_RE L (8-15) SIN021 SIN0 PORTS P2_27 P0_05 (0x002A) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 120 RESSE RIC_RE SIN024 SDA0 L (8-15) (0x0030) PORTS EL (0-7) PORTS (8-15) RESSE TOT0 TOT1 TOT2 TOT3 L (0-7) RESSE RIC_RE L (8-15) MFS0_TRIG SIN025 PORTS (0x0032) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 121 SIN030 SCL1 (0x003C) PORTS EL (0-7) PORTS (8-15) 80ns 80ns RESSE noise noise L (0-7) filter filter disable enable RIC_RE RESSE L (8-15) SIN031 SDA1 (0x003E) PORTS EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 122 RESSE L (8-15) RIC_RE MFS3_TRIG SIN046 PORTS (0x005C) EL (0-7) PORTS (8-15) RESSE TOT0 TOT1 TOT2 TOT3 L (0-7) RESSE RIC_RE L (8-15) MFS4_TRIG SIN053 PORTS (0x006A) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 123 RESSE L (8-15) RIC_RE MFS8_TRIG SIN081 PORTS (0x00A2) EL (0-7) PORTS (8-15) RESSE L (0-7) RESSE RIC_RE L (8-15) SIN084 SIN9 PORTS set 1 P5_08 P3_09 (0x00A8) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 124 SIN091 SIN10 PORTS set 1 P5_12 P3_14 (0x00B6) EL (0-7) PORTS (8-15) RESSE L (0-7) RESSE L (8-15) RIC_RE SIN092 SCK10 PORTS (0x00B8) EL (0-7) set 1 P5_11 P3_13 PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 125 SCK11 PORTS set 1 P5_15 P3_16 P4_27 (0x00C6) EL (0-7) PORTS (8-15) RESSE TOT16 TOT17 TOT18 TOT19 L (0-7) RESSE RIC_RE L (8-15) SIN102 MFS11_TRIG PORTS (0x00CC EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 126 L (8-15) SIN134 PORTS (0x010C) set 1 P3_10 EL (0-7) PORTS P3_16 (8-15) MCAN0_ RESSE PORT_P PIN_AN L (0-7) D_TX RESSE RIC_RE L (8-15) SIN136 PORTS (0x0110) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 127 TIN49 PORTS (0x011C) EL (0-7) PORTS (8-15) RESSE PORT_P RLT3_U PPG0_T TOT3 TOT1 L (0-7) FSET OUT0 RESSE RIC_RE L (8-15) SIN144 TIN0 PORTS P2_28 P5_28 (0x0120) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 128 P0_01 P2_31 (0x0126) EL (0-7) PORTS (8-15) RESSE PORT_P RLT19_U PPG6_T TOT19 TOT17 L (0-7) FSET OUT0 RESSE RIC_RE L (8-15) SIN160 TIN16 PORTS P0_03 P3_04 (0x0140) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 129 TIN19 PORTS (0x0146) EL (0-7) P0_09 P3_11 PORTS (8-15) RESSE PORT_P RLT35_U TOT35 TOT33 L (0-7) FSET RESSE RIC_RE L (8-15) SIN176 TIN32 PORTS P0_11 P3_13 (0x0160) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 130 P3_19 (0x0166) EL (0-7) PORTS (8-15) RESSE L (0-7) RESSE L (8-15) RIC_RE SIN192 EINT0 PORTS (0x0180) EL (0-7) P6_00 P0_15 P0_19 P1_09 P2_16 P3_00 P3_16 P4_00 PORTS P5_00 P5_16 (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 131 P3_19 P4_03 (0x0186) EL (0-7) PORTS P5_03 P5_19 (8-15) RESSE L (0-7) RESSE L (8-15) RIC_RE SIN196 EINT4 PORTS P0_03 P5_22 P3_04 P3_20 P4_04 (0x0188) EL (0-7) PORTS P5_04 P5_20 (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 132 P3_07 P3_23 P4_07 (0x018E) EL (0-7) PORTS P5_07 (8-15) RESSE L (0-7) RESSE RIC_RE L (8-15) SIN200 EINT8 PORTS P0_07 P1_01 P2_24 P3_08 P3_24 P4_08 (0x0190) EL (0-7) PORTS P5_08 (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 133 (0x0196) EL (0-7) PORTS P5_11 P5_27 (8-15) RESSE L (0-7) RESSE RIC_RE L (8-15) SIN204 EINT12 PORTS P0_11 P1_05 P2_28 P3_12 P3_28 P4_12 P4_28 (0x0198) EL (0-7) PORTS P5_12 P5_28 (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 134 P5_31 P0_14 P0_18 P1_08 P2_31 P3_15 P3_31 PORTS P4_31 P5_15 (8-15) RESSE PORT_P PPG0_T TOT0 TOT1 L (0-7) OUT2 RESSE RIC_RE L (8-15) SIN224 FRT0_TEXT PORTS (0x01C0) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 135 L (8-15) RIC_RE SIN227 FRT3_TEXT PORTS (0x01C6) EL (0-7) PORTS (8-15) RESSE PORT_P PPG4_T L (0-7) TOT0 TOT2 OUT2 RESSE L (8-15) RIC_RE SIN228 FRT4_TEXT PORTS (0x01C8) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 136 L (8-15) SIN231 FRT7_TEXT PORTS (0x01CE EL (0-7) PORTS (8-15) RESSE PORT_P RLT3_U RLT16_U PPG6_T L (0-7) FSET FSET OUT2 RESSE L (8-15) RIC_RE SIN232 FRT8_TEXT PORTS (0x01D0) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 137 RIC_RE FRT10_TEX SIN234 PORTS (0x01D4) EL (0-7) PORTS (8-15) RESSE PORT_P RLT3_U RLT16_U PPG9_T L (0-7) FSET FSET OUT2 RESSE L (8-15) RIC_RE SIN235 FRT11_TEXT PORTS (0x01D6) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 138 RESSE L (8-15) RIC_RE OCU0_MOD SIN241 PORTS (0x01E2) EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE RIC_RE L (8-15) OCU0_MOD SIN242 PORTS (0x01E4) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 139 RESSE L (8-15) RIC_RE OCU1_MOD SIN244 PORTS (0x01E8) EL (0-7) PORTS (8-15) RESSE L (0-7) set 1 set 0 RESSE RIC_RE L (8-15) SIN245 OCU1_MOD (0x01EA PORTS EL (0-7 PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 140 RESSE RIC_RE L (8-15) SIN247 OCU2_MOD PORTS (0x01EE EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE L (8-15) RIC_RE OCU2_MOD SIN248 PORTS (0x01F0) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 141 RESSE L (8-15) RIC_RE OCU3_MOD SIN250 PORTS (0x01F4) EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE RIC_RE L (8-15) OCU3_MOD SIN251 PORTS (0x01F6) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 142 RESSE L (8-15) RIC_RE OCU4_MOD SIN253 PORTS (0x01FA) EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE RIC_RE L (8-15) SIN254 OCU4_MOD PORTS (0x01FC EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 143 RESSE L (8-15) RIC_RE OCU5_MOD SIN256 PORTS (0x0200) EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE RIC_RE L (8-15) OCU5_MOD SIN257 PORTS (0x0202) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 144 RESSE L (8-15) RIC_RE OCU6_MOD SIN259 PORTS (0x0206) EL (0-7) PORTS (8-15) RESSE L (0-7) set 1 set 0 RESSE L (8-15) RIC_RE OCU6_MOD SIN260 PORTS (0x0208) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 145 RESSE L (8-15) RIC_RE OCU7_MOD SIN262 PORTS (0x020C) EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE L (8-15) RIC_RE OCU7_MOD SIN263 PORTS (0x020E) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 146 RESSE L (8-15) RIC_RE OCU8_MOD SIN265 PORTS (0x0212) EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE RIC_RE L (8-15) OCU8_MOD SIN266 PORTS (0x0214) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 147 RESSE L (8-15) RIC_RE OCU9_MOD SIN268 PORTS (0x0218) EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE RIC_RE L (8-15) OCU9_MOD SIN269 PORTS (0x021A) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 148 RESSE L (8-15) RIC_RE OCU10_MO SIN271 PORTS (0x021E) EL (0-7) PORTS (8-15) RESSE set 1 set 0 L (0-7) RESSE RIC_RE L (8-15) OCU10_MO SIN272 PORTS (0x0220) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 149 RESSE L (8-15) RIC_RE OCU11_MO SIN274 PORTS (0x0224) EL (0-7) PORTS (8-15) RESSE L (0-7) set 1 set 0 RESSE L (8-15) RIC_RE OCU11_MO SIN275 PORTS (0x0226) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 150 L (0-7) RESSE L (8-15) ICU pair PORTS ch.0-0 EL (0-7) PORTS RIC_RE (8-15) SIN290 RESSE (0x0244) FRT Ch0 L (0-7) RESSE L (8-15) ICU pair PORTS ch.0-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 151 L (8-15) ICU pair PORTS ch.1-0 EL (0-7) PORTS RIC_RE (8-15) SIN293 RESSE (0x024A) FRT Ch1 FRT Ch0 L (0-7) RESSE L (8-15) ICU pair PORTS ch.1-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 152 L (8-15) ICU pair PORTS ch.2-0 EL (0-7) PORTS RIC_RE (8-15) SIN296 RESSE (0x0250) FRT Ch2 FRT Ch0 L (0-7) RESSE L (8-15) ICU pair PORTS ch.2-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 153 PORTS EL (0-7) PORTS RIC_RE SIN299 (8-15) (0x0256) RESSE FRT Ch3 FRT Ch0 FRT Ch1 FRT Ch2 L (0-7) RESSE L (8-15) ICU pair PORTS ch.3-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 154 L (0-7) RESSE L (8-15) ICU pair PORTS ch.4-0 EL (0-7) PORTS (8-15) RIC_RE RESSE SIN302 L (0-7) FRT Ch4 (0x025C) RESSE L (8-15) ICU pair ch.4-1 PORTS EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 155 L (8-15) ICU pair PORTS ch.5-0 EL (0-7) PORTS RIC_RE (8-15) SIN305 RESSE (0x0262) FRT Ch5 FRT Ch4 L (0-7) RESSE L (8-15) ICU pair PORTS ch.5-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 156 L (8-15) ICU pair PORTS ch.6-0 EL (0-7) PORTS RIC_RE (8-15) SIN308 RESSE (0x0268) FRT Ch6 FRT Ch4 L (0-7) RESSE L (8-15) ICU pair PORTS ch.6-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 157 PORTS ch.7-0 EL (0-7) PORTS RIC_RE (8-15) SIN311 RESSE (0x026E) FRT Ch7 FRT Ch4 FRT Ch5 FRT Ch6 L (0-7) RESSE L (8-15) ICU pair PORTS ch.7-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 158 FRT Ch8 RESSE L (8-15) ICU pair ch.8-0 PORTS EL (0-7) PORTS RIC_RE SIN314 (8-15) (0x0274) RESSE FRT Ch8 L (0-7) RESSE L (8-15) ICU pair PORTS ch.8-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 159 L (8-15) ICU pair PORTS ch.9-0 EL (0-7) PORTS (8-15) RIC_RE RESSE SIN317 L (0-7) FRT Ch9 FRT Ch8 (0x027A) RESSE L (8-15) ICU pair ch.9-1 PORTS EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 160 RESSE L (8-15) ICU pair PORTS ch.10-0 EL (0-7) PORTS RIC_RE (8-15) SIN320 RESSE (0x0280) FRT Ch8 L (0-7) Ch10 RESSE L (8-15) ICU pair PORTS ch.10-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 161 ICU pair PORTS ch.11-0 EL (0-7) PORTS RIC_RE (8-15) SIN323 RESSE (0x0286) FRT Ch8 FRT Ch9 L (0-7) Ch11 Ch10 RESSE L (8-15) ICU pair PORTS ch.11-1 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 162 L (8-15) RIC_RE SIN362 ZIN8 PORTS P2_26 P5_11 (0x02D4) EL (0-7) PORTS (8-15) RESSE PORT_P TOT17 L (0-7) RESSE RIC_RE L (8-15) SIN363 AIN9 PORTS P2_29 P5_12 (0x02D6) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 163 FSET FSET RESSE L (8-15) RIC_RE SIN384 PPG0_TIN1 PORTS (0x0300) EL (0-7) PORTS (8-15) RESSE set 0 L (0-7) RESSE RIC_RE L (8-15) SIN385 PPG0_TIN2 PORTS (0x0302) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 164 L (0-7) RESSE L (8-15) RIC_RE SIN388 PPG1_TIN2 PORTS (0x0308) EL (0-7) PORTS (8-15) RESSE L (0-7) set 0 RESSE L (8-15) RIC_RE SIN389 PPG1_TIN3 PORTS (0x030A) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 165 PPG2_TIN3 PORTS (0x0310) EL (0-7) PORTS (8-15) RESSE PORT_P RLT0_U RLT1_U FRT3_M OCU3_O TOT0 TOT1 L (0-7) FSET FSET RESSE L (8-15) RIC_RE SIN393 PPG3_TIN1 PORTS (0x0312) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 166 FSET FSET RESSE L (8-15) RIC_RE SIN396 PPG4_TIN1 PORTS (0x0318) EL (0-7) PORTS (8-15) RESSE set 0 L (0-7) RESSE RIC_RE L (8-15) SIN397 PPG4_TIN2 PORTS (0x031A) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 167 L (0-7) RESSE L (8-15) RIC_RE SIN400 PPG5_TIN2 PORTS (0x0320) EL (0-7) PORTS (8-15) RESSE set 0 L (0-7) RESSE RIC_RE L (8-15) SIN401 PPG5_TIN3 PORTS (0x0322) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 168 (0x0328) EL (0-7) PORTS (8-15) RESSE PORT_P RLT16_U RLT18_U FRT11_ OCU11_ TOT16 TOT18 L (0-7) FSET FSET MTSF OTD0 RESSE RIC_RE L (8-15) SIN405 PPG7_TIN1 PORTS (0x032A) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 169 MTSF OTD0 RESSE L (8-15) RIC_RE SIN408 PPG8_TIN1 PORTS (0x0330) EL (0-7) PORTS (8-15) RESSE L (0-7) set 0 RESSE L (8-15) RIC_RE SIN409 PPG8_TIN2 PORTS (0x0332) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 170 L (0-7) RESSE L (8-15) RIC_RE SIN412 PPG9_TIN2 PORTS (0x0338) EL (0-7) PORTS (8-15) RESSE set 0 L (0-7) RESSE L (8-15) RIC_RE SIN413 PPG9_TIN3 PORTS (0x033A) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 171 (0x0340) EL (0-7) PORTS (8-15) RESSE PORT_P RLT16_U RLT19_U FRT11_ OCU11_ TOT16 TOT19 L (0-7) FSET FSET MTSF OTD0 RESSE RIC_RE L (8-15) SIN417 PPG11_TIN1 PORTS (0x0342) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 172 PORTS (8-15) RESSE PORT_P RLT1_U RLT2_U OCU1_O OCU2_O BT0_AD BT2_AD BT4_AD L (0-7) FSET FSET TOUT2 TOUT0 TOUT0 RESSE RIC_RE L (8-15) ADC12B_HW SIN439 PORTS TRG1 (0x036E) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 173 PORTS (8-15) RESSE PORT_P RLT17_U RLT18_U OCU5_O OCU6_O BT2_AD BT4_AD BT6_AD L (0-7) FSET FSET TOUT2 TOUT0 TOUT0 RESSE RIC_RE L (8-15) ADC12B_HW SIN443 PORTS TRG5 (0x0376) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 174 (8-15) RESSE PORT_P RLT33_U RLT34_U OCU9_O OCU10_ BT4_AD BT6_AD BT8_AD L (0-7) FSET FSET OTD0 TOUT2 TOUT0 TOUT0 RESSE L (8-15) RIC_RE ADC12B_HW SIN447 TRG9 PORTS (0x037E) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 175 PORTS (8-15) RESSE PORT_P RLT1_U RLT3_U OCU1_O OCU3_O BT6_AD BT8_AD BT10_A L (0-7) FSET FSET TOUT2 TOUT0 DTOUT0 RESSE L (8-15) RIC_RE ADC12B_HW SIN451 PORTS TRG13 (0x0386) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 176 PORTS (8-15) RESSE PORT_P RLT17_U RLT19_U OCU5_O OCU7_O BT8_AD BT10_A BT0_AD L (0-7) FSET FSET TOUT2 DTOUT0 TOUT0 RESSE RIC_RE L (8-15) ADC12B_HW SIN455 PORTS TRG17 (0x038E) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 177 (8-15) RESSE PORT_P RLT33_U RLT35_U OCU9_O OCU11_ BT10_A BT0_AD BT2_AD L (0-7) FSET FSET OTD0 DTOUT2 TOUT0 TOUT0 RESSE RIC_RE L (8-15) ADC12B_HW SIN459 PORTS TRG21 (0x0396) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 178 PORTS (8-15) RESSE PORT_P RLT1_U RLT16_U OCU1_O OCU4_O BT0_AD BT1_AD BT3_AD L (0-7) FSET FSET TOUT2 TOUT0 TOUT0 RESSE RIC_RE L (8-15) ADC12B_HW SIN463 PORTS TRG25 (0x039E) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 179 PORTS (8-15) RESSE PORT_P RLT17_U RLT32_U OCU5_O OCU8_O BT2_AD BT3_AD BT5_AD L (0-7) FSET FSET TOUT2 TOUT0 TOUT0 RESSE L (8-15) RIC_RE ADC12B_HW SIN467 TRG29 PORTS (0x03A6) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 180 PORTS (8-15) RESSE PORT_P RLT33_U RLT0_U OCU9_O OCU0_O BT4_AD BT5_AD BT7_AD L (0-7) FSET FSET TOUT2 TOUT0 TOUT0 RESSE RIC_RE L (8-15) SIN471 ADC12B_HW PORTS (0x03AE TRG33 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 181 PORTS (8-15) RESSE PORT_P RLT1_U RLT17_U OCU1_O OCU5_O BT6_AD BT7_AD BT9_AD L (0-7) FSET FSET TOUT2 TOUT0 TOUT0 RESSE RIC_RE L (8-15) ADC12B_HW SIN475 PORTS TRG37 (0x03B6) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 182 PORTS (8-15) RESSE PORT_P RLT17_U RLT33_U OCU5_O OCU9_O BT8_AD BT9_AD BT11_A L (0-7) FSET FSET TOUT2 TOUT0 DTOUT0 RESSE RIC_RE L (8-15) SIN479 ADC12B_HW PORTS (0x03BE TRG41 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 183 PORTS (8-15) RESSE PORT_P RLT33_U RLT1_U OCU9_O OCU1_O BT10_A BT11_A BT1_AD L (0-7) FSET FSET DTOUT2 DTOUT0 TOUT0 RESSE RIC_RE L (8-15) ADC12B_HW SIN483 PORTS TRG45 (0x03C6) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 184 PORTS (8-15) RESSE PORT_P RLT1_U RLT18_U OCU1_O OCU6_O BT0_AD BT4_AD BT5_AD L (0-7) FSET FSET TOUT2 TOUT2 TOUT2 RESSE RIC_RE L (8-15) SIN487 ADC12B_HW (0x03CE TRG49 PORTS EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 185 (8-15) RESSE PORT_P RLT17_U RLT34_U OCU5_O OCU10_ BT2_AD BT6_AD BT7_AD L (0-7) FSET FSET OTD0 TOUT2 TOUT2 TOUT2 RESSE L (8-15) RIC_RE ADC12B_HW SIN491 PORTS TRG53 (0x03D6) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 186 PORTS (8-15) RESSE PORT_P RLT33_U RLT2_U OCU9_O OCU2_O BT4_AD BT8_AD BT9_AD L (0-7) FSET FSET TOUT2 TOUT2 TOUT2 RESSE RIC_RE L (8-15) SIN495 ADC12B_HW PORTS (0x03DE TRG57 EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 187 PORTS (8-15) RESSE PORT_P RLT1_U RLT19_U OCU1_O OCU7_O BT6_AD BT10_A BT11_A L (0-7) FSET FSET TOUT2 DTOUT2 DTOUT2 RESSE RIC_RE L (8-15) ADC12B_HW SIN499 PORTS TRG61 (0x03E6) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 188 RIC_RE L (8-15) SIN510 M_DDRHSS (0x03FC PI_MSTART PORTS EL (0-7) PORTS (8-15) RESSE set 0 set 1 L (0-7) RESSE RIC_RE L (8-15) CAP0_RESE SIN520 PORTS (0x0410) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 189 L (0-7) RESSE L (8-15) RIC_RE SIN523 CAP0_VLD PORTS (0x0416) EL (0-7) PORTS (8-15) RESSE L (0-7) RESSE L (8-15) RIC_RE SIN526 PORTS (0x041C) EL (0-7) set 1 P0_28 P0_03 PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 190 L (0-7) RESSE RIC_RE L (8-15) SIN546 ECLK1 PORTS (0x0444) EL (0-7) PORTS (8-15) RESSE L (0-7) RESSE L (8-15) RIC_RE CAP0_DATA SIN558 PORTS P0_02 P0_04 (0x045C) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 191 RESSE L (8-15) RIC_RE CAP0_DATA SIN561 PORTS P0_05 P0_07 (0x0462) EL (0-7) PORTS (8-15) RESSE L (0-7) RESSE L (8-15) RIC_RE CAP0_DATA SIN562 PORTS P0_06 P0_08 (0x0464) EL (0-7) PORTS (8-15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 192 The following RIC configuration directly connects to graphic system function port. − RIC_RESIN520 (CAP0_RESET_N) & !(GRST) => cap0_reset_n − RIC_RESIN521 (CAP0_MODE0) => cap0_mode[0] − RIC_RESIN522 (CAP0_MODE1) => cap0_mode[1] − RIC_RESIN523 (CAP0_VLD) => cap0_vld S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 193 A0_7 TA_D7+/- (0x0010) PPC_PCF GFXCOR GPIO_POD DSP0_DAT PPG5_TO GR009 P0_09 E_RSDS_ OCU5_OTD0 CS#1_2 R0:POD[9] A1_7 (0x0012) INACTIVE PPC_PCF GPIO_POD DSP0_DAT DSP0_DA PPG5_TO G_RWDS_ GR010 P0_10 TOT32 OCU5_OTD1 R0:POD[10] A0_8 TA_D8+/- (0x0014) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 194 GPIO_POD DSP0_CT PPG4_TO GR028 P0_28 OCU4_OTD1 R0:POD[28] (0x0038) PPC_PCF M_RWDS GPIO_POD PPG5_TO GR030 P0_30 G_SCLK0 _0/G_RW OCU5_OTD1 R0:POD[30] (0x003C) DS_1 PPC_PCF GPIO_POD M_SDATA1 G_SDATA PPG6_TO GR031 P0_31 CS#2_0/1 OCU6_OTD0 R0:POD[31] (0x003E) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 195 GPIO_POD INDICATO PPG0_TO GR216 P2_16 OCU0_OTD0 R2:POD[16] R0_1 (0x00A0) PPC_PCF GPIO_POD PPG0_TO GR217 P2_17 OCU0_OTD1 R2:POD[17] (0x00A2) PPC_PCF GPIO_POD GR219 P2_19 R2:POD[19] (0x00A6) PPC_PCF GPIO_POD PPG3_TO GR222 P2_22 OCU3_OTD0 R2:POD[22] (0x00AC) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 196 GR303 P3_03 SGO1 TOT3 SOT8 OCU9_OTD1 TRACE3 R3:POD[3] (0x00C6) PPC_PCF GPIO_POD OCU10_OTD PPG10_TO TRACE_C GR304 P3_04 SGA2 SCK8 R3:POD[4] (0x00C8) PPC_PCF GPIO_POD OCU10_OTD PPG10_TO TRACE_C GR305 P3_05 SGO2 TOT16 R3:POD[5] (0x00CA) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 197 R3:POD[16] (0x00E0) PPC_PCF GPIO_POD MFS8_CS PPG4_TO GR317 P3_17 SGO2 OCU4_OTD1 R3:POD[17] (0x00E2) PPC_PCF GPIO_POD PPG5_TO GR318 P3_18 SGA3 TOT35 OCU5_OTD0 R3:POD[18] (0x00E4) PPC_PCF GPIO_POD PPG5_TO GR319 P3_19 SGO3 OCU5_OTD1 R3:POD[19] (0x00E6) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 198 P3_30 PWM1M2 R3:POD[30] (0x00FC) PPC_PCF GPIO_POD OCU11_OTD PPG11_TO GR331 P3_31 PWM2P2 R3:POD[31] (0x00FE) PPC_PCF GPIO_POD PPG0_TO GR400 P4_00 PWM2M2 OCU0_OTD0 R4:POD[00] (0x0100) PPC_PCF GPIO_POD PPG0_TO GR401 P4_01 PWM1P3 OCU0_OTD1 R4:POD[1] (0x0102) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 199 GR425 P4_25 DSP1_CLK OCU0_OTD1 R4:POD[25] (0x0132) PPC_PCF GPIO_POD DSP1_CT DSP0_CT PPG1_TO GR426 P4_26 SGA1 SOT11 OCU1_OTD0 R4:POD[26] (0x0134) PPC_PCF GPIO_POD DSP1_CT DSP0_CT PPG1_TO GR427 P4_27 SGO1 SCK11 OCU1_OTD1 R4:POD[27] RL10 (0x0136) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 200 PPC_PCF GPIO_POD DSP1_DAT PPG7_TO GR507 P5_07 SCK9 OCU7_OTD1 R5:POD[7] A1_6 (0x014E) PPC_PCF GPIO_POD DSP1_DAT PPG8_TO GR508 P5_08 OCU8_OTD0 R5:POD[8] A0_6 (0x0150) PPC_PCF GPIO_POD DSP1_DAT PPG8_TO GR509 P5_09 OCU8_OTD1 R5:POD[9] A1_5 (0x0152) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 201 P5_21 OCU9_OTD1 R5:POD[21] TA0_4 TA1_10 (0x016A) PPC_PCF GPIO_POD DSP0_CTR DSP0_CT DSP0_CT OCU10_OTD PPG10_TO GR522 P5_22 TXER R5:POD[22] (0x016C) PPC_PCF GPIO_POD DSP0_DAT DSP0_DA PPG9_TO GR527 P5_27 TOT0 OCU9_OTD1 R5:POD[27] A0_0 TA_D0+/- (0x0176) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 202 TRACE2 R6:POD[5] (0x018A) PPC_PCF GPIO_POD GR606 P6_06 TRACE3 R6:POD[6] (0x018C) PPC_PCF GPIO_POD GR607 P6_07 TRACE4 R6:POD[7] (0x018E) PPC_PCF GPIO_POD GR608 P6_08 TRACE5 R6:POD[8] (0x0190) PPC_PCF GPIO_POD GR609 P6_09 TRACE6 R6:POD[9] (0x0192) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 203 GPIO_POD TRACE_CL GR619 P6_19 R6:POD[19] (0x01A6) PPC_PCF GPIO_POD TRACE_CT GR620 P6_20 R6:POD[20] (0x01A8) PPC_PCF GPIO_POD GR621 P6_21 R6:POD[21] (0x01AA) PPC_PCF GPIO_POD GR622 P6_22 R6:POD[22] (0x01AC) PPC_PCF GPIO_POD GR623 P6_23 R6:POD[23] (0x01AE) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 204 PPC_PCFGR.PIE (port input enable bit) should be configured using ports as RSDS ports. Set 0 to the appropriate PIE bit.  I2SCLK port PPC_PCFGR.PIE (port input enable bit) of P0_13 and P0_17 should be configured using ports as I2SCLK ports. Set 1 to the appropriate PIE bit. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 205 GPO[1] in HYPERBUSIn_GPOR of HyperBus Interface ch.0 is not used. − GPO[1:0] in HYPERBUSIn_GPOR of HyperBus Interface ch.1, ch.2 are not used. − If HyperBus Interface ch.2 is used, the configuration of GPO bit is unnecessary. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 206 CMOS-s P5_27 CMOS-s P5_28 CMOS-s P5_29 CMOS-s P5_30 CMOS-s P5_31 CMOS-s P6_00 CMOS-s P0_00 CMOS-s P0_01 CMOS-s P0_02 CMOS-s P0_03 CMOS-s P0_04 CMOS-s P0_05 CMOS-s P0_06 CMOS-s P0_07 CMOS-s P0_08 CMOS-s S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 207 Automotive P3_00 CMOS-s Automotive P3_01 CMOS-s Automotive P3_02 CMOS-s Automotive P3_03 CMOS-s Automotive P3_04 CMOS-s Automotive P3_05 CMOS-s Automotive P3_06 CMOS-s Automotive P3_18 CMOS-s Automotive P3_19 CMOS-s Automotive P3_20 CMOS-s Automotive S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 208 Automotive P3_16 CMOS-s Automotive P3_17 CMOS-s Automotive P2_17 CMOS-s Automotive P2_16 CMOS-s Automotive P4_29 CMOS-s Automotive P4_30 CMOS-s Automotive P4_31 CMOS-s Automotive P5_00 CMOS-s Automotive CMOS-s Automotive P5_01 CMOS-s Automotive P5_02 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 209 "Automotive" is Automotive input level. − "TTL" is TTL input level. − "MediaLB" is MediaLB input level. − To get detailed information about the input level, see the DC characteristics of the Datasheet. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 210 20mA P0_17 10mA 20mA P5_22 10mA 20mA P1_09 10mA P1_05 10mA P1_07 10mA P1_06 10mA P1_04 10mA P1_08 10mA P0_30 10mA P0_31 10mA P1_01 10mA P1_00 10mA P1_03 10mA P1_02 10mA S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 211 P3_30 30mA P3_31 30mA P4_00 30mA P4_01 30mA P4_02 30mA P4_03 30mA P4_04 30mA P4_05 30mA P4_06 30mA P4_07 30mA P4_08 30mA P4_09 30mA P4_10 30mA *2-2 only with I2C output S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 212 *2-2 only with I2C output P5_10 P5_11 *2-2 only with I2C output P5_12 P5_13 P5_14 P5_15 P5_16 P5_17 *2-2 only with I2C output P5_18 P5_19 *2-2 only with I2C output P5_20 P4_25 P4_26 P4_27 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 213 *2-2 If the PPC_PCFGR:POF[2:0] is configured as SDA or SCL function, the pin is set to "Pseudo Open Drain". IOL is configured by the corresponding PPC_PCGR:ODR[1:0] register. To get detailed information about the drive capability, see the DC characteristics of the Datasheet. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 214 RIC_RESINx.PORTSEL and RESSEL − At turning from MCU PSS mode to RUN, the latched status will not be released automatically. Configuration SYSC0_SPECFGR.HOLDIO_PDx = 0 should be necessary for releasing the status. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 215 − P2_26(SCK0) − P2_25(SOT0) − P2_27(SIN0) − P4_06(MFS0_CS0) − P4_11(MFS0_CS1) − P4_12(MFS0_CS2) − P4_10(MFS0_CS3) Group1 − P0_27(SCK1) − P0_26(SOT1) − P0_28(SIN1) Multi-Function Serial Ch.1 Group2 − P2_30(SCK1) − P2_29(SOT1) − P2_31(SIN1) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 216 Multi-Function Serial Ch.9 Group2 − P5_07(SCK9) − P5_06(SOT9) − P5_08(SIN9) − P5_11(MFS9_CS0) − P5_12(MFS9_CS1) Group1 − P3_13(SCK10) − P3_12(SOT10) − P3_14(SIN10) Multi-Function Serial Ch.10 Group2 − P5_11(SCK10) − P5_10(SOT10) − P5_12(SIN10) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 217 CAN Ch.1 Group2 − P4_12(TX1) − P4_11(RX1) Group1 − P3_09(TX5) − P3_08(RX5) CAN Ch.5 Group2 − P3_15(TX5) − P3_14(RX5) Group1 − P3_11(TX6) − P3_10(RX6) CAN Ch.6 Group2 − P3_17(TX6) − P3_16(RX6) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 218 GPIO Key Code Register (GPIO_KEYCDR) Port Setting Register PPC Key Code Register (PPC_PCFGRijj) (PPC_KEYCDR) PPC Key Code Register (PPC_KEYCDR) Resource Input Setting Register RIC Key Code Register (RIC_RESINn) (RIC_KEYCDR) RIC Key Code Register (RIC_KEYCDR) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 219 Glitch at output port may sometime be observed when the following case. 1. from input to output 2. from output to input 3. from input to input 4. from output to output S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 220 Enable an input at PPC_PCFGRn.PIE =1. Configure a resource output signal at PPC_PCFGRn.POF[2:0]. Release input cut-off function at GPIO_PORTEN.GPORTEN = 1. Notes: − The dedicated input/output direction configuration should be necessary for SCK (MSF). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 221 Enable an input at PPC_PCFGRn.PIE =1. Configure a resource output signal as GPIO at PPC_PCFGRn.POF[2:0]. Configure the data direction to input at GPIO_DDRn = 0. Release input cut-off function at GPIO_PORTEN.GPORTEN = 1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 222 Configure a resource output signal at PPC_PCFGRn.POF[2:0]. Notes: − The dedicated output control configuration as well as POF should be necessary for bellows. − SOUT(MFS), − SGA,SGO(SG) − WOT(RTC) − MFS_CS (MFS) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 223 Enable an input at PPC_PCFGRn.PIE = 1. Configure a resource output signal as GPIO at PPC_PCFGRn.POF[2:0]. Configure the data direction to input at GPIO_DDRn = 0. Release input cut-off function at GPIO_PORTEN.GPORTEN = 1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 224 Figure 5-5: Procedure of Port Output Start Disable analog input in case with analog function. Configure a resource output signal as GPIO at PPC_PCFGRn.POF[2:0]. Configure the data direction to input at GPIO_DDRn = 1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 225 Regarding the analog switch setting, see 'CHAPTER of 12/10/8-BIT Analog to Digital Converter ’ and 'CHAPTER of LCDC Controller'. − D/A Converter and FPD-Link has dedicated Output Ports. They don’t have POF. The configuration is described in each chapter. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 226 0 or 1 (EINT) disable Reload Timer input noise filter 0 or 1 (TIN) disable I2C interface noise filter (SCL, SDA) enable/disable (iij, xx, n = resource channel number) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 227 GPIO for using ENINTx or TINx GPIO (for GPIO) Resource External Interrupt (for EINT/TIN) External pins GPIO for using SCLx, SDAx of I2C GPIO (for GPIO) Resource (for SCL, SDA) (MFS) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 228 State Transition CHAPTER 12: This chapter explains the state transition. Overview Diagram of State Transition Fetching the Operation Mode Changes to PSS and RUN CODE: STATE_TRANSITION-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 229 CHAPTER 12:State Transition Overview This section gives a brief overview of State transition Refer to the low-power chapter for the detailed information for performing a change state. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 230 CHAPTER 12:State Transition Diagram of State Transition This section shows diagram of state transitions. The device state transitions for this series are shown below. Figure 2-1 Diagram of Device State Transitions S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 231 STOP mode shutdown shutdown Shutdown (PD6_ON) (PD6_OFF) Setup for changes PSSEN0 disable enable enable enable enable enable PSSEN1 enable enable enable enable enable enable Execution of a WFI command. Changes start command S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 232 14.2ms~33.3ms after LVDL2 reset release. AVCC3_LVDS_PLL User (11) Ensure use of LVDS after this supply is stable by software. 10 VCC3_LVDS_TX Ensure use of LVDS after this supply is stable by software. User (11) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 233 Reset Security evaluation User Fast/Slow-CR stabilization wait Regulator of flash BootROM User processing description program operating Reset Factor (Fast-CR*1920cycle) stabilization wait program operating program operating Internal reset release wait release (Fast-CR*8cycle) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 234 Reset User (Fast-CR*3cycle + Regulator of flash Security evaluation BootROM User processing description program operating Source stabilization wait program operating program operating Reset Factor release wait Clock*3cycle) Internal reset release S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 235 Reset Regulator of flash User (Fast-CR*3cycle + Security evaluation BootROM User processing description stabilization program operating Source Reset Factor program operating program operating wait(skip) Clock*3cycle) release wait Internal reset release S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 236 If VCC12 needs to be switched off by other means, VCC5 needs ramping down to occur LVDH1 reset before switching off VCC12 t o inactivate the operation of VCC12 supplied domain below the operation assurance range. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 237 User RUN→PSS Power Domain mode of a Int- processing description program operating Updating PSS Profile OFF sequence Regulator stabilization (Slow-CR Timer mode) (PWU wait time) (PWU mode) (Slow-CR Timer mode wait S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 238 Regulator of flash Security evaluation User processing description [Slow-CR Always Regulator stabilization stabilization wait (Power supply shutoff) Updating RUN Profile stabilization wait program operating oscillation enable] wait Internal reset release (Fast-CR*1920cycle) (Fast-CR*8cycle) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 239 Low-voltage Detection CHAPTER 13: This chapter explains the function of low-voltage detection. Overview Configuration and Block Diagram Operation Registers Electric Characteristics CODE: LVD-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 240 RVD (Reset) Regulator PONR (Reset) LVDH0 LVDL1 Reset/Interrupt Enable/Disable Detection Voltage Reset/Interrupt LVDH1 Reset/Interrupt Enable/Disable Detection Voltage Reset/Interrupt VCC12 LVDL2 Enable/Disable Reset/Interrupt Detection Voltage Reset/Interrupt VCC3 LVDH2 Enable/Disable Reset/Interrupt Detection Voltage Reset/Interrupt S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 241 Bit name Description LVDL1S, LVDH1S, LVDL2S, LVDH2S 0: Reset, 1: Interrupt LVDL1V, LVDH1V, LVDL2V, LVDH2V Threshold voltage can be configured to the bit range. LVDL1E, LVDH1E, LVDL2E, LVDH2E 0: Disable, 1: Enable S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 242 Guaranteed MCU operation range 0.77 (Initial value) 0.87 0.97 1.07 Notes: − This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 243 MCU operation voltage. − When changing detection voltage level toward lower level, please change it step by step or set LVDH2E to “0”(Stop operation) to avoid activation by interference of LVDH1 switching activity. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 244 *1: These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. [bit0] LVDH2E: LVDH2 operation enable bit Description STOP operation (Initial value) Enable operation S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 245 CHAPTER 13:Low-voltage Detection Electric Characteristics See the datasheet. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 246 Serial Programming CHAPTER 14: This chapter explains serial programming. Overview Memory Map FLASH Sector Configuration Port Configuration Operation Note. CODE: SERIAL_PRG-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 247 Used for a serial output function after reset operation. P2_26/SCK0 Used for synchronous mode. Notes: − See the chapter of PORT DESCRIPTION for Port name. − See the PIN ASSIGNMENT on Datasheet. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 248 Download count number (BC15-BC8) Download count number (BC23-BC16) Download count number (BC31-BC24) Sum value of download command*1 *1: The SUM value is calculated in 8-bits, and the overflow of simple addition is ignored. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 249 Byte Value Explanation Reset command  Full Chip Erase Command Word Position Word Value Explanation C0356EA5H Key0 2E830596H Key1 01A00000H Key2 F3A033EDH Key3 370E6A51H Key4 B0412000H Key5 00000002H Key6 AA805510H Key7 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 250 *1: Only when the SUM malfunction occurs, command response is returned. Command response is not returned except the SUM malfunction occurs. After receiving executing command, it jumps to the download start address specified by the download command if the SUM is not malfunctioning. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 251 Command response *1 4 Byte : BABEFACEH Normal end *1: Command response is returned only when it is normal end. In other cases, hard reset is operated and command response is not returned. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 252 Jump to downloaded program Download command? SUM value error? SUM value error response Normal response Reception of download data SUM value error? SUM value error response Download process Command error response response S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 253 If 1.2V power supply is supervised and RSTX is controlled with its low-voltage state, PSC cannot output "high", that is, external power supply devises would not start power supplying, and MCU cannot go to a power-on sequence before a serial programming operation. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 254 12-/10-/8-bit Analog to Digital CHAPTER 15: Converter This chapter explains the functions and operations of the 12-/10-/8-bit A/D Converter. Overview Configuration and Block Diagram Operation of A/D Converter Setup Procedure Examples Registers CODE: FIP022-E02.3 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 255 (12-bit)/upper 8-bit of the conversion result  Programmable upper and lower thresholds for each range comparator  The comparison results will set flags per logical channel, depending on the configuration. Possible configurations are: S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 256 DMA burst setup, since the group result registers can be read linearly  Debug mode provides the possibility to freeze further A/D conversion processing at the end of the current conversion S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 257 12bit ADC ANIN ・・ Result ・ m≦63 Conversion completion Result register interrupt Range comparator Interrupts Range comparator thresholds requests Range comparator interface Range Comparator Result Interrupt Pulse counter Pulse Counter Interrupt S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 258 (configured as A/D converter resumption time register (ADC12Bn_RT)) elapses. At the end of resumption time, the priority arbiter compares the priorities of all logical channels with set trigger status and inactive data protection feature. The S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 259 Clear all the trigger status flags (ADC12Bn_TRGST0 to 1.TRGST and ADC12Bn_CHSTAT0 to 63.TRGST) of the affected logical channels, by writing "1" to the corresponding bits of ADC12Bn_TRGCL0 to 1 (or ADC12B_CHCTRL0 to 63.TRGCL) registers. − Reconfigure the logical channels. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 260 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 261 "Stop" setting (ADC12Bn_CHCTRL0 to 63.RSMRST = "00") - when setting DP to "1", enable the group interrupted interrupt (set the corresponding ADC12Bn_GRPIRQE0.GRPIRQE0 to 3 to "1"): The conversion result will be protected when the channel is interrupted or when all conversions have been completed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 262 If the priority (CHPRI) of the requested channel is lower than active channel, it can be interrupted and the conversion of the channel with the higher priority is started. − If the priority (CHPRI) is higher or same, it cannot be interrupted. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 263 Even though the logical channels 3 and 5 have higher priority, their trigger status is not set. (5) Logical channel 1. (6) Logical channel 2. (7) Logical channel 61. (8) Logical channel 62. It has lower number then the channel 63. (9) Logical channel 63. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 264 3 shows the configuration of the group starting with the idle trigger type, i.e. the trigger status of the logical channel 4 is set to "1" if there is no logical channel having trigger status flag set and inactive data protection function. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 265 6. (5) Group 1 is converted. (6) Idle trigger group 2 is converted. Group 0 will not be processed until next channel 0 trigger appears. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 266 3 is finished. (5) Group 1 is converted. (6) The operation is dependent on the setting of forced stop mode (ADC12Bn_CTRL.FSMD). Forced stop mode is enabled (ADC12Bn_CTRL.FSMD = "1", Figure 3-6): S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 267 Restart group setting (RSMRST[1:0] = "10") for a logical channel configures that if the group is interrupted just before conversion start of that channel, its trigger status is cleared and the processing of the group will be restarted after higher priority conversions are done: S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 268 Figure 3-9 shows an example of restarting a group processing with its first channel during the conversion of the last channel of the group processing (Forced stop mode is enabled (ADC12Bn_CTRL.FSMD = "1")). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 269 (4) After the conversion of channel 5 is finished (group 0 is converted), processing continues with the conversion of the channel 6. (5) Group 1 is converted. (6) At the end of group 1 processing, idle trigger group 2 is converted (group 0 is not restarted). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 270 (2) Processing of the group 0, conversion of logical channels 0 -> 1 -> 2 -> start of channel 3 conversion. (3) Logic channel 6 trigger is issued during the conversion of channel 3. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 271 (8) At the end of group 0 processing, idle trigger group 2 is converted. Figure 3-11 Restarting of the Group Processing with a Subgroup Group Channel 6 trigger Channel Channel 0 trigger Stop/ Resume/ Restart Trigger type Priority S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 272 (ADC12Bn_MCCTRL0 to 3.ICIRQY) determine the further channel processing (after higher priority requests are converted). Table 3-1 shows the description about multiple conversion after interrupted (ADC12Bn_CTRL.FSMD = "0"). Table 3-2 shows the description about multiple conversion after interrupted (ADC12Bn_CTRL.FSMD = "1"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 273 "1" (cannot be interrupted Don’t care. between single Don't care Multiple conversion is not interrupted. conversion) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 274 − For notes of data protection about multiple conversion, refer to section "Logical channel data protection function" in chapter "3. Operation of A/D ". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 275 (by writing "1" to the corresponding bits of ADC12Bn_TRGCL1 to 0 or ADC12Bn_CHCTRLi.TRGCL), it is set "1" again immediately when the trigger status flag of all the channels is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 276 Set AVRHSEL bit to "1". − For different ADC12Bn_OCV.OCV settings trigger the multiple conversion channel, i.e. perform AVRH voltage conversion. It is better to configure multiple conversions of AVRH and calculate average result. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 277 − Set AVRLSEL and AVRHSEL bits to "0". − Trigger and perform further logical channel conversions (analog inputs AN to which are logical channels mapped are converted by calibrated A/D Converter). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 278 Selection of one of eight available range comparator threshold values for the logical channel is "0" : 8-bit range comparator configured by corresponding ADC12Bn_CHCTRL0 to 63.RCSEL[2:0] bit fields. The upper/lower comparator compares the upper 8 bits of the A/D conversion result. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 279 Interrupt flags ADC12Bn_RCOL4 ADC12Bn_RCOL3 Selected lower threshold ADC12Bn_RCOL2 ADC12Bn_RCOL1 Interrupt ADC12Bn_RCOL0 Comparator result RES[1:0] Pulse detection Resolution of A/D conversion ADC12Bn_CTRL A/D Conversion Result RCSEL[2:0] RCINVSEL Range Comparator Control RCEN ADC12Bn_CHCTRL0～63 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 280 Interrupt flags ADC12Bn_FRCOL4 ADC12Bn_FRCOL3 Selected lower threshold ADC12Bn_FRCOL2 ADC12Bn_FRCOL1 Interrupt ADC12Bn_FRCOL0 Comparator result RES[1:0] Pulse detection Resolution of A/D conversion ADC12Bn_CTRL A/D Conversion Result RCSEL[2:0] RCINVSEL Range Comparator Control RCEN ADC12Bn_CHCTRL0～63 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 281 Positive counter is reloaded with the value set in the reload register ADC12Bn_PCCTRL0 to 63.PCTPRL when: − Negative counter reaches zero, − "1" is written to dedicated ADC12Bn_PCIRQC0 to 1.PCIRQC63 to 0 bit. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 282 Software clears PCIRQ flag and reloads positive and negative counter. h) Negative event decrements negative counter. i) Negative counter expires and reloads positive counter. j) Positive counter decrements and negative counter reloads with positive event. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 283 "0", and the A/D Converter goes to idle (power-down) state; if any trigger status bit is set again, the A/D Converter leaves idle state, and the ADC12Bn_STAT.BUSY flag is set to "1" after the resumption time elapses. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 284 Start of A/D conversion control Setting of global A/D conversion Setting of logical channel Setting of range comparator Setting of pulse detection A/D conversion Range comparator Pulse detection End of A/D conversion control S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 285 Number of the logical channel selected for conversion done interrupt for triggering a DMA request setting (ADC12Bn_CDDS0~3.CDCHNUM[5:0]) Channel conversion done DMA dedicated interrupt enable setting (ADC12Bn_CDDS0~3.CDCHEN) End setting of global A/D conversion S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 286 Number of conversions for the multiple conversion channel setting (ADC12Bn_MCCTRL0~3.CNVNUM[3:0]) Intra-channel interruptibility for the multiple conversion logical channel setting (ADC12Bn_MCCTRL0~3.ICIRQY) A/D reference voltage selection setting (ADC12Bn_MCCTRL0~3.AVRLSEL) (ADC12Bn_MCCTRL0~3.AVRHSEL) End setting of logical channel S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 287 (ADC12Bn_FRCOH0~7) (ADC12Bn_RCOH0~7) (ADC12Bn_FRCOL0~7) (ADC12Bn_RCOL0~7) Range comparator select setting (ADC12Bn_CHCTRL0~63.RCSEL[2:0]) Range comparator inverted range selection setting (ADC12Bn_CHCTRL0~63.RCINVSEL) Range comparator interrupt enable setting (ADC12Bn_RCIRQE0~1.RCIRQE) End setting of range comparator S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 288 Positive counter reload value setting (ADC12Bn_PCIRQE0~1.PCIRQE = "0") (ADC12Bn_PCCTRL0~63.PCTPRL[7:0]) Negative counter reload value setting (ADC12Bn_PCCTRL0~63.PCTNRL[4:0]) Reload positive/negative counter value (ADC12Bn_PCIRQC0~1.PCIRQC ="1") Pulse counter interrupt enable setting (ADC12Bn_PCIRQE0~1.PCIRQE) End setting of pulse detection S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 289 Set as software trigger of all channels (ADC12Bn_CHCTRL0~63. TRGTYP[1:0] = "00") During A/D conversion? (ADC12Bn_TRGST0~1. TRGST = "1") All trigger status clear (ADC12Bn_TRGCL0~1.TRGCL = "1") End of A/D conversion (single conversion, channel i) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 290 (TRGTYP[1:0] expects "00") Set as software trigger of all channels (ADC12Bn_CHCTRL0~63. TRGTYP[1:0] = "00") During A/D conversion? (ADC12Bn_TRGST0~1. TRGST = "1") All trigger status clear (ADC12Bn_TRGCL0~1.TRGCL = "1") End of group conversion S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 291 Clear range comparator interrupt flag of channel i (ADC12Bn_RCIRQC0~1.RCIRQC = "1") Continue Continue operation of range comparator? Finish Set as range comparator disable of channel i (ADC12Bn_CHCTRLi.RCEN = "0") End of range comparator (channel i) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 292 PCIRQC = "1") Reload positive and negative counters Continue Continue operation of pulse detection? Finish Set as pulse counter interrupt disable of channel i (ADC12Bn_PCIRQE0~1.PCIRQE = "0") End of pulse detection (channel i) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 293 Full Range Comparator Lower Threshold Registers (ADC12Bn_FRCOL0 to 7) Multiple conversion logical channel related registers are:  A/D Multiple Conversion Channel Control Registers (ADC12Bn_MCCTRL0 to 3)  A/D Multiple Conversion Channel Status Registers (ADC12Bn_MCSTAT0 to 3) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 294 PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME TRGTYP[1] TRGTYP[0] ANIN[5] ANIN[4] ANIN[3] ANIN[2] ANIN[1] ANIN[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:26] Reserved : Reserved bits When writing, always write "0". When reading, "0" is always read. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 295 When reading, "0" is always read. [bit20:18] RCSEL[2:0] : Range Comparator Select bit RCSEL[2:0] Description Select range comparator 0, defined by ADC12Bn_RCOH0 and ADC12Bn_RCOL0 registers. Select range comparator 7, defined by ADC12Bn_RCOH7 and ADC12Bn_RCOL7 registers. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 296 Idle trigger, the channel trigger status is set if there is no channel having trigger status flag set and inactive data protection function. TRGTYP[1:0] are not allowed to update during A/D conversion operation (ADC12Bn_TRGST0 to 1.TRGST and ADC12Bn_CHSTAT0 to 63.TRGST="1"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 297 CHAPTER 15:12-/10-/8-bit Analog to Digital Converter [bit5:0] ANIN[5:0] : Analog Input Selection bits ANIN[5:0] Description 000000 Analog input AN0 is selected. 111111 Analog input AN63 is selected. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 298 The conversion result is less than or equal to the upper threshold. The conversion result is above the upper threshold. This bit is identical to the corresponding bit in the ADC12Bn_RCOTF0 register. For more details, see ADC12Bn_RCOTF0 to 1 register description. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 299 [bit0] TRGST : Trigger Status flag Description Conversion request not detected. Conversion request detected. This bit is identical to the corresponding bit in the ADC12Bn_TRGST0 register. For more details, see ADC12Bn_TRGST0 to 1 register description. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 300 8-bit conversion resolution (bits 15 to 8 are "0"), − bit[9:0] for 10-bit conversion resolution (bits 15 to 10 are "0"), − bit[11:0] for 12-bit conversion resolution (bits 15 to 12 are "0"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 301 12-bit conversion resolution. The register is updated at the end of the A/D conversion only in the case the corresponding trigger status (ADC12Bn_TRGST0.TRGST4 and ADC12Bn_CHSTAT4.TRGST bits) is still "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 302 PCTPRL[5] PCTPRL[4] PCTPRL[3] PCTPRL[2] PCTPRL[1] PCTPRL[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:29] Reserved : Reserved bits Reading this bit returns an undefined. Writing data to these bits has no effect on the operation. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 303 ADC12Bn_PCIRQC0 to 1.PCIRQC bit or on expiration of the corresponding negative counter (PCTNCT). For further explanation of negative events and operation of pulse detection function refer to section "Pulse Detection Function" in chapter "3 Operation of A/D " S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 304 R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME CDONEIRQ7 CDONEIRQ6 CDONEIRQ5 CDONEIRQ4 CDONEIRQ3 CDONEIRQ2 CDONEIRQ1 CDONEIRQ0 ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 305 ADC12Bn_CD0 to 31 read access types (8/16/32-bit) clear the flag. If this bit is set and cleared at the same time, clearing has higher priority. This bit is identical to the CDONEIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 registers. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 306 ADC12Bn_CD32 to 63 read access types (8/16/32-bit) clear the flag. If this bit is set and cleared at the same time, clearing has higher priority. This bit is identical to the CDONEIRQ bit in the corresponding ADC12Bn_CHSTAT32 to 63 registers. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 307 CDONEIRQ BIT_NAME ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ BIT_NAME ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ BIT_NAME ACCESS_TYPE PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 308 Conversion done interrupt disabled Conversion done interrupt enabled. Conversion done interrupt is issued when the bit is "1" and the corresponding interrupt flags ADC12Bn_CDONEIRQ0.CDONEIRQ31 to 0 and ADC12Bn_CHSTAT0 to 31.CDONEIRQ are set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 309 Conversion done interrupt disabled Conversion done interrupt enabled. Conversion done interrupt is issued when the bit is "1" and the corresponding interrupt flags ADC12Bn_CDONEIRQ1.CDONEIRQ63 to 32 and ADC12Bn_CHSTAT32 to 63.CDONEIRQ are set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 310 R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W PROT_TYPE INITIAL_VALUE BIT_OFFSET CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ CDONEIRQ BIT_NAME ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 311 No effect. Conversion Done Interrupt cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_CDONEIRQ0 register and CDONEIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 register are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 312 No effect. Conversion Done Interrupt cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_CDONEIRQ1 register and CDONEIRQ bit in the corresponding ADC12Bn_CHSTAT32 to 63 register are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 313 The bit is set to "1" if following conditions are fulfilled: − The corresponding trigger status flags of the channel (ADC12Bn_CHSTAT0 to 31.TRGST and ADC12Bn_TRGST0.TRGST31 to 0) are set to "1" S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 314 This bit is cleared by writing "1" to the corresponding ADC12Bn_GRPIRQC0 bits. This bit is identical to the GRPIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 registers S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 315 This bit is cleared by writing "1" to the corresponding ADC12Bn_GRPIRQC1 bits. This bit is identical to the GRPIRQ bit in the corresponding ADC12Bn_CHSTAT32 to 63 registers S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 316 Group interrupted interrupt disabled. Group interrupted interrupt enabled. Group interrupted interrupt is issued when this bit is "1" and the corresponding interrupt flags (ADC12Bn_GRPIRQ0.GRPIRQ31 to 0 and ADC12Bn_CHSTAT0 to 31.GRPIRQ) are set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 317 Group interrupted interrupt disabled. Group interrupted interrupt enabled. Group interrupted interrupt is issued when this bit is "1" and the corresponding interrupt flags (ADC12Bn_GRPIRQ1.GRPIRQ63 to 32 and ADC12Bn_CHSTAT32 to 63.GRPIRQ) are set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 318 No effect. Group interrupted interrupt cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_GRPIRQ0 register and GRPIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 register are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 319 No effect. Group interrupted interrupt cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_GRPIRQ1 register and GRPIRQ bit in the corresponding ADC12Bn_CHSTAT32 to 63 register are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 320 [bit31:0] RCIRQ31 to 0 : Range Comparator Interrupt flags Description Range comparator interrupt not detected. Range comparator interrupt detected. This flag shows that an outside range or inside range condition has been found on the corresponding logical channel. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 321 An interrupt condition is met (see Table 5-1) This bit is cleared by writing "1" to the corresponding ADC12B_RCIRQC0.RCIRQC bit. This bit is identical to the RCIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 322 An interrupt condition is met (see Table 5-1) This bit is cleared by writing "1" to the corresponding ADC12B_RCIRQC1.RCIRQC bit. This bit is identical to the RCIRQ bit in the corresponding ADC12Bn_CHSTAT32 to 63 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 323 INT condition: above range, ADC12Bn_RCOTF0 to 1.RCOTF and ADC12Bn_CHSTAT0 to 63.RCOTF are set. outside range INT condition: below range, ADC12Bn_RCOTF0 to 1.RCOTF and ADC12Bn_CHSTAT0 to 63.RCOTF are cleared. inside INT condition: inside range range S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 324 Range comparator interrupt disabled. Range comparator interrupt enabled Range comparator interrupt is issued when this bit is "1" and the corresponding interrupt flags ADC12Bn_RCIRQ0.RCIRQ31 to 0 and ADC12Bn_CHSTAT0 to 31.RCIRQ are set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 325 Range comparator interrupt disabled. Range comparator interrupt enabled Range comparator interrupt is issued when this bit is "1" and the corresponding interrupt flags ADC12Bn_RCIRQ1.RCIRQ63 to 32 and ADC12Bn_CHSTAT32 to 63.RCIRQ are set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 326 No effect. Range comparator interrupt cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_RCIRQ0 register and RCIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 register are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 327 No effect. Range comparator interrupt cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_RCIRQ1 register and RCIRQ bit in the corresponding ADC12Bn_CHSTAT32 to 63 register are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 328 Pulse counter interrupt detected. This register returns the status of the pulse counter interrupt flag which is set when positive counter ADC12B_PCCTRL0 to 31.PCTPCT of the corresponding logical channel decrements to zero. The S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 329 This bit is cleared by writing "1" to the corresponding bit in the ADC12Bn_PCIRQC0 register. This bit is identical to the PCIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 330 This bit is cleared by writing "1" to the corresponding bit in the ADC12Bn_PCIRQC1 register. This bit is identical to the PCIRQ bit in the corresponding ADC12Bn_CHSTAT32 to 63 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 331 Pulse counter interrupt is enabled. Pulse counter interrupt is issued when this bit is "1" and the corresponding interrupt flags ADC12Bn_PCIRQ0.PCIRQ31 to 0 and ADC12Bn_CHSTAT0 to 31.PCIRQ are set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 332 Pulse counter interrupt is enabled. Pulse counter interrupt is issued when this bit is "1" and the corresponding interrupt flags ADC12Bn_PCIRQ1.PCIRQ63 to 32 and ADC12Bn_CHSTAT32 to 63.PCIRQ are set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 333 No effect. Pulse counter interrupt cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_PCIRQ0 register and PCIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 register are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 334 CHAPTER 15:12-/10-/8-bit Analog to Digital Converter Additionally, the corresponding positive and negative counter (ADC12Bn_PCCTRL0 to 31.PCTPCT and ADC12Bn_PCCTRL0 to 31.PCTNCT) are reloaded with their reload values defined in the ADC12Bn_PCCTRL0 to 31.PCTPRL and ADC12Bn_PCCTRL0 to 31.PCTNRL. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 335 ADC12Bn_CHSTAT32 to 63 register are cleared. Additionally, the corresponding positive and negative counter (ADC12Bn_PCCTRL32 to 63.PCTPCT and ADC12Bn_PCCTRL32 to 63.PCTNCT) are reloaded with their reload values defined in the ADC12Bn_PCCTRL32 to 63.PCTPRL and ADC12Bn_PCCTRL32 to 63.PCTNRL. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 336 TRGST1 TRGST0 ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX PROT_TYPE INITIAL_VALUE [bit31:0] TRGST31 to 0 : A/D Channel Trigger Status flags Description No conversion request. Conversion request is issued. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 337 When setting and clearing of the bit takes place at the same time, clearing has priority. This bit is identical to the TRGST bit in the corresponding ADC12Bn_CHSTAT0 to 31 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 338 The corresponding group processing is interrupted just before the conversion of this channel is started and the channel is not configured as "resume" channel (ADC12Bn_CHCTRL32 to 63.RSMRST = "01"). Instead, the group interrupted interrupt flag is set S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 339 When setting and clearing of the bit takes place at the same time, clearing has priority. This bit is identical to the TRGST bit in the corresponding ADC12Bn_CHSTAT32 to 63 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 340 A/D channel trigger status is cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_TRGST0 register and TRGST bit in the corresponding ADC12Bn_CHSTAT0 to 31 register are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 341 If forced stop is disabled (ADC12Bn_CTRL.FSMD = "0"), do not set trigger status flag again during the same conversion after the trigger status is cleared. Please set again after the end timing of the cleared conversion. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 342 A/D conversion period. This bit is identical to the TRGCL bit in the corresponding ADC12Bn_CHCTRL32 to 63 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 343 If forced stop is disabled (ADC12Bn_CTRL.FSMD = "0"), do not set trigger status flag again during the same conversion after the trigger status is cleared. Please set again after the end timing of the cleared conversion. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 344 Trigger overrun occurred This bit is set to "1" under following conditions: − Conversion request is issued although the corresponding trigger status bits ADC12Bn_TRGST0.TRGST and ADC12Bn_CHSTAT0 to 31.TRGST are already set to "1" S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 345 Software and hardware trigger are issued at the same cycle and corresponding trigger type ADC12Bn_CHCTRL0 to 31.TRGTYP[1:0] is set to "01" Writing "1" to the corresponding bit in the ADC12Bn_TRGORC0 register clears this bit. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 346 Software and hardware trigger are issued at the same cycle and corresponding trigger type ADC12Bn_CHCTRL32 to 63.TRGTYP[1:0] is set to "01" Writing "1" to the corresponding bit in the ADC12Bn_TRGORC1 register clears this bit. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 347 [bit31:0] TRGORC31 to 0 : Trigger Overrun Clear bits Description No effect. Trigger overrun flag is cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_TRGOR0 register is cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 348 [bit31:0] TRGORC63 to 32 : Trigger Overrun Clear bits Description No effect. Trigger overrun flag is cleared. When this bit is set to "1", the corresponding bit in the ADC12Bn_TRGOR1 register is cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 349 The flag is only applicable in "outside range" mode i.e. while the RCINVSEL bit in the corresponding ADC12Bn_CHCTRL0 to 31 register is "0". If a range comparator interrupt is signaled (corresponding bits ADC12Bn_RCIRQ0.RCIRQ31 to 0 = ADC12Bn_CHSTAT0 to 31.RCIRQ = "1"), this flag has the following meaning: S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 350 This bit is updated only in the case the corresponding interrupt flag (ADC12Bn_RCIRQ0.RCIRQ, ADC12Bn_CHSTAT0 to 31.RCIRQ) has a rising edge. This bit is identical to the RCOTF bit in the corresponding ADC12Bn_CHSTAT0 to 31 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 351 This bit is updated only in the case the corresponding interrupt flag (ADC12Bn_RCIRQ1.RCIRQ, ADC12Bn_CHSTAT32 to 63.RCIRQ) has a rising edge. This bit is identical to the RCOTF bit in the corresponding ADC12Bn_CHSTAT32 to 63 register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 352 CDCHNUM bits is disabled. Interrupt for triggering DMA request on conversion done interrupt flag (ADC12Bn_CHSTAT0 to 63.CDONEIRQ = ADC12Bn_CDONEIRQ0 to 1.CDONEIRQ = "1") of the logical channel defined by CDCHNUM bits is enabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 353 111111 Logical channel 63 selected. The conversion done interrupts of the group last logical channels are good candidates for DMA burst setup, since the group result registers can be read linearly. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 354 If [CT value >= 4]: Comparison time = (CT value x 13) x Peripheral clock period Do not set CT value to 0. For specific values of minimum and maximum comparison time, please refer to the Device Data Sheet. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 355 Do not set RT value to 0. RT value >= Maximum resumption time / Peripheral clock period. For specific values of maximum resumption time, please refer to the Device Data Sheet. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 356 ADC12Bn_CHCTRL0 to 63.SMTIME to "00". Sampling time = ST value x Peripheral clock period Do not set ST value below 6. For specific values of minimum sampling time, please refer to the Device Data Sheet. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 357 After A/D Converter calibration, the calculated offset compensation value must be written to this register. For further explanation of A/D Converter calibration refer to section "A/D Converter Calibration" in chapter "3 Operation of A/D ". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 358 After A/D Converter calibration, the calculated gain compensation value must be written to this register. For further explanation of A/D Converter calibration refer to section "A/D Converter Calibration" in chapter "3 Operation of A/D ". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 359 0x00 BIT_OFFSET BIT_NAME PDDMD FSTP FRCMD FSMD ACHMD DBGE RES[1] RES[0] ACCESS_TYPE R0,W PROT_TYPE INITIAL_VALUE [bit15:8] Reserved : Reserved bits When writing, always write "0". When reading, "0" is always read. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 360 − Request forced stop of A/D conversion is disabled. The forced stop mode is enabled. − An active A/D conversion can be interrupted. − Request forced stop of A/D conversion is enabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 361 8 bits of ADC12Bn_CD0 to 63 registers if the 8-bit resolution is configured. In case of 10-bit or 8-bit resolution, the lower 2 or 4 bits of the 12-bit conversion result are truncated (not rounded). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 362 This bit is set to "1" when first conversion request (trigger status set to "1") occurs and A/D Converter resumption time (power-up wait time configured as A/D converter resumption time register (ADC12Bn_RT)) elapses. This bit clear to "0" when the all trigger status are cleared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 363 If ACHMD is equal to "1", ACH represents the last logical channel number whose conversion has finished. ACH is updated at the end of the A/D conversion only in the case the corresponding trigger status (ADC12Bn_TRGST0 to 1.TRGST and ADC12Bn_CHSTAT0 to 63.TRGST bits) is still "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 364 RCOH[7:0], then the conversion result is outside range. Selection of one of eight available range comparator threshold values for the logical channel is configured by corresponding ADC12Bn_CHCTRL0 to 63.RCSEL[2:0] bit fields. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 365 RCOL[7:0], then the conversion result is outside range. Selection of one of eight available range comparator threshold values for the logical channel is configured by corresponding ADC12Bn_CHCTRL0 to 63.RCSEL[2:0] bit fields. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 366 ADC12Bn_CTRL.RES[1:0] define this resolution. − If 12-bit resolution (ADC12Bn_CTRL.RES[1:0] = "x0"): FRCOH[11:0] Compares the 12 bits of A/D conversion result. − If 10-bit resolution (ADC12Bn_CTRL.RES[1:0] = "01"): FRCOH[11:10] Not used for 10-bit range comparator. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 367 Compares the 8 bits of A/D conversion result. Selection of one of eight available range comparator threshold values for the logical channel is configured by corresponding ADC12Bn_CHCTRL0 to 63.RCSEL[2:0] bit fields. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 368 ADC12Bn_CTRL.RES[1:0] define this resolution. − If 12-bit resolution (ADC12Bn_CTRL.RES[1:0] = "x0"): FRCOL[11:0] Compares the 12 bits of A/D conversion result. − If 10-bit resolution (ADC12Bn_CTRL.RES[1:0] = "01"): FRCOL[11:10] Not used for 10-bit range comparator. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 369 Compares the 8 bits of A/D conversion result. Selection of one of eight available range comparator threshold values for the logical channel is configured by corresponding ADC12Bn_CHCTRL0 to 63.RCSEL[2:0] bit fields. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 370 "3 Operation of A/D ". [bit5] AVRLSEL : A/D reference voltage AVRL selection bit Description AVRL voltage is not selected for A/D conversion AVRL voltage is selected for A/D conversion S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 371 1 conversion. With this setting multiple conversion logical channel behaves like any other logical 0000 channel. 0001 2 conversions. 0010 3 conversions. 1111 16 conversions CNVNUM[3:0] are not allowed to update during A/D conversion operation (ADC12Bn_TRGST0 to 1.TRGST and ADC12Bn_CHSTAT0 to 63.TRGST="1"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 372 After the set event of the conversion done interrupt flag, the ADC12Bn_MCSTAT.MCCNT[4:0] are meaningless. MCCNT[4:0] Description 00000 No conversion is finished. 00001 1 conversion is finished. 10000 16 conversions are finished. 10001-11111 Reserved S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 373 Stepper Motor Controller CHAPTER 16: This chapter explains the functions and operations of the Stepper Motor Controller (SMC). Overview Configuration and Block Diagram Operation of the Stepper Motor Controller Registers CODE: FIP021-E1.1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 374 A variable operating Clock Prescaler (the division ratio from a Peripheral clock can be selected by software).  Output selector logic ("High", "Low", PWM pulse and "Hi-Z" signal levels can be selected). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 375 CHAPTER 16:Stepper Motor Controller Configuration and Block Diagram This section shows block diagrams of the Stepper Motor Controller. Figure 2-1 Block Diagram of the Stepper Motor Controller S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 376 The SMC Trigger Delay Register (PTRGDL) is used to delay the start of the operation by 0 to 255 clock cycles. Set Logic for PWC.CE The Set logic for PWC.CE receives the trigger and waits for a configured delay time and sets automatically PWC.CE bit. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 377 1010 CLKP/10 42.667 170.667 1011 CLKP/12 51.2 204.8 1100 CLKP/16 1024 68.267 273.067 1101 CLKP/20 1280 85.333 341.333 1110 CLKP/24 1536 102.4 409.6 1111 CLKP/32 2048 136.533 546.133 CLKP: Peripheral clock S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 378 Notes: − If the PWM Pulse Generator is started(PWC.CE="1"), operate following steps because the PWM Pulse Generator.Compare Data Value must be initialized. 1. Set the PWM Compare Register.Compare Data Value(PWC1.D[9:0], PWC2.D[9:0]) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 379 PWM2 Compare Register.Compare Data Value(PWC2.D[9:0]) − PWM Selection Register.Output Selection bits(PWS.P2[2:0], PWS.M2[2:0], PWS.P1[2:0], PWS.M1[2:0]) An example for the Stepper Motor Controller setting procedure is given on the Figure 3 2 . S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 380 CHAPTER 16:Stepper Motor Controller Figure 3-2 Example of the Setting Procedure for the Stepper Motor Controller S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 381 Hi-Z Hi-Z X: don't care Table 3-3 Selection of Motor Drive Signals and Setting of PWM2 Selection Bits PWS.P2[2:0] PWM2P PWS.M2[2:0] PWM2M PWM pulse PWM pulse Hi-Z Hi-Z X: don't care S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 382 The following scenario is shown on Figure 3-3: 1. Automatic clear of the Output Update bit (PWS.BS): load operation is executed and reflected on the output. Figure 3-3 Load Timing of PWM Compare Register and PWM Selection Register S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 383 Stepper Motor Controller, is shown on Figure 3-5. Note: − The trigger should only be received when the Stepper Motor Controller are not running (i.e. the Count Enable bit (PWC.CE) is cleared to "0"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 384 CHAPTER 16:Stepper Motor Controller Figure 3-4 Flowchart for Triggering Stepper Motor Controller S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 385 Delay Register (PTRGDL) setting is 0x00, PWC.CE is set immediately after receiving the trigger input (PWM_TRG). If the SMC Trigger Delay Register (PTRGDL) setting is 0x01, PWC.CE is set with a delay of one clock cycle after receiving the trigger input (PWM_TRG). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 386 Table 4-1 List of Registers for the Stepper Motor Controller Abbreviation Register Name Reference PWM Control Register PWC1 PWM1 Compare Register 4.2.1 PWC2 PWM2 Compare Register 4.2.2 PWM Selection Register PWSS PWM Selection Set Register PTRGDL SMC Trigger Delay Register S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 387 PWM Operating clock is equal to the Peripheral clock (CLKP) PWM Operating clock is equal to CLKP/4 PWM Operating clock is equal to CLKP/5 PWM Operating clock is equal to CLKP/6 PWM Operating clock is equal to CLKP/8 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 388 CE bit is set by the trigger. − The CE bit shall be set to "1" after the setting of the PWM Operating Clock Prescaler bits (PWC.P[3:0]) and the Operation Mode Switching bit (PWC.SC) is completed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 389 The PWC.CE bit shall be set to "1" after the setting of the PWM Operating Clock Prescaler bits (PWC.P[3:0]) and the Operation Mode Switching bit (SC) is completed. [bit1:0] Reserved: Reserved bits When writing, always write "0". When reading, "0" is always read. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 390 D[9:8] bits are "don't care". When the Operation Mode Switching bit is set to 10-bit operation mode (PWC.SC= "1"), the compare data value is taken from D[9:0] bits. D[9:0] Description 0x(0)00 … Set the PWM pulse width 0x(3)FF (99.9%) 99.6% S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 391 Compare Register (PWC1, PWC2) is possible and will not result in error response. − If the PWS.BS bit is "1" , don't change the PWM Compare Register.Compare Data Value(D[9:0], PWC2.D[9:0]) and the PWM Selection Register.Output Selection bits (PWS.P2[2:0], PWS.M2[2:0], PWS.P1[2:0], PWS.M1[2:0]). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 392 The software must always make a 16-bit write access to PWM1 and PWM2 Compare Registers (PWC1, PWC2) to ensure consistency of data. However, 8-bit write access to PWM1 or PWM2 Compare Register (PWC1, PWC2) is possible and will not result in error response. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 393 CHAPTER 16:Stepper Motor Controller − If the PWS.BS bit is "1" , don't change the PWM Compare Register.Compare Data Value(PWC1.D[9:0], D[9:0]) and the PWM Selection Register.Output Selection bits (PWS.P2[2:0], PWS.M2[2:0], PWS.P1[2:0], PWS.M1[2:0]). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 394 Enables the update of the setting for the PWM output Notes: − If the PWM Pulse Generator is started(PWC.CE="1"), operate following steps because the PWM Pulse Generator.Compare Data Value must be initialized. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 395 [bit7:6] Reserved: Reserved bit When writing, always write "0". When reading, "0" is always read. [bit5:3] P1[2:0]: Plus Output 1 Selection bits The P1[2:0] bits select the output signal for PWM1P. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 396 X: don't care Note: − If the PWS.BS bit is "1" , don't change the PWM Compare Register.Compare Data Value(PWC1.D[9:0], PWC2.D[9:0]) and the PWM Selection Register.Output Selection bits (PWS.P2[2:0], PWS.M2[2:0], PWS.P1[2:0], M1[2:0]). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 397 3. Set the PWM Control Register.Count Enable bit(PWC.CE="1") − If the PWS.BS bit is "1" , don't change the PWM Compare Register.Compare Data Value(PWC1.D[9:0], PWC2.D[9:0]) and the PWM Selection Register.Output Selection bits (PWS.P2[2:0], PWS.M2[2:0], PWS.P1[2:0], PWS.M1[2:0]). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 398 CHAPTER 16:Stepper Motor Controller [bit13:0] Reserved: Reserved bits When writing, always write "0". When reading, "0" is always read. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 399 Delay of 1 clock cycle between the trigger and the clock cycle in which the PWM generation 0x01 starts … … Delay of 255 clock cycles between the trigger and the clock cycle in which the PWM generation 0xFF starts S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 400 Trigger Configuration of Stepper CHAPTER 17: Motor Controller This chapter explains the trigger configuration of stepper motor controller. Overview Configuration and Block Diagram Operation Registers CODE: SMCTRG-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 401 SMC trigger group S1 S15, S14, S13, S12, S11, S10 PWM_TRG[0] SMC0 channel PWM_TRG[1] SMC1 channel PWM_TRG[2] SMC2 channel PWM_TRG[3] SMC3 channel PWM_TRG[4] SMC4 channel *Shaded parts are registers PWM_TRG[5] SMC5 channel S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 402 CHAPTER 17:Trigger Configuration of Stepper Motor Controller Operation The trigger configuration and its operation is described in 4. Registers Offset Register Name 0x00000000 SMCTGg_PTRGS 0x00000002 SMCTGg_PTRG S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 403 [bit12] S24 : Trigger Enable for Operation of SMC<6*g+4> This bit selects SMC<6*g+4> for the SMC trigger group S2 (triggered by SMCTGg_PTRG:TR2). Description SMC<6*g+4> is not triggered by SMCTGg_PTRG:TR2 SMC<6*g+4> is triggered by SMCTGg_PTRG:TR2 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 404 [bit4] S14 : Trigger Enable for Operation of SMC<6*g+4> This bit selects SMC<6*g+4> for the SMC trigger group S1 (triggered by SMCTGg_PTRG:TR1). Description SMC<6*g+4> is not triggered by SMCTGg_PTRG:TR1 SMC<6*g+4> is triggered by SMCTGg_PTRG:TR1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 405 [bit0] S10 : Trigger Enable for Operation of SMC<6*g+0> This bit selects SMC<6*g+0> for the SMC trigger group S1 (triggered by SMCTGg_PTRG:TR1). Description SMC<6*g+0> is not triggered by SMCTGg_PTRG:TR1 SMC<6*g+0> is triggered by SMCTGg_PTRG:TR1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 406 This bit is cleared automatically to "0" after one clock cycle. − A second trigger should not be applied to a group which has already been triggered. If this happens, the running delay counter will reset its value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 407 This bit is cleared automatically to "0" after one clock cycle. − A second trigger should not be applied to a group which has already been triggered. If this happens, the running delay counter will reset its value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 408 Sound Generator CHAPTER 18: This chapter explains the functions and operations of the Sound Generator(SG). Overview Configuration Operations Registers CODE: FS12C-E01.21 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 409 - It is enabled to generate interrupt requests at the end of outputting sound at programmed length (An overflow of Tone pulse counter). Interrupt - It is enabled to generate interrupts by writing "1" to the Start bit (SGCR.ST) when in DMA mode (SGCR.DMA="1"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 410 Register (SGCR) Register (SGAR) Register (SGFR) (SGTCR) Register (SGNR) Reload Reload Reload Reload BCLK PWM pulse Prescaler Frequency Counter Decrement counter Tone pulse counter generator PWM Cycle Data Register (SGPCR) Toggle Flip-flop S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 411 Output number of a tone pulse signal per one cycle (TCn) - to the Time Cycle Register (SGTCR) Time cycle number to assert interrupts (Nn) - to the Tone Output Number Register S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 412 In the conceptual diagram shown above, it outputs 6 steps of signal. Each register, such as Amplitude Data Register, is supposed to be written at the following timing. - Before starting signal output - Each time after asserting an interrupt S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 413 SGA pin is "H" during 1 PWM cycle. Moreover, when the Amplitude Data Register (SGAR) is greater than or equal to the PWM Cycle Data Register (SGPCR), the SGA pin output is always "H". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 414 (2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse. (The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle) When it meets neither condition, the sound output cannot guarantee the expected duty ratio. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 415 Register (SGAR). Because the bus clock proportion of 16 MHz and 40 MHz is 1:2.5, the same sound can be made by setting the values of these two registers to 1:2.5. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 416 The transfer size #1 is calculated by the setting of {SGDER.ARE1, SGDER.ARE0, SGDER.FRE, and SGDER.NRE} in the "DMA Transfer Update Enable Register (SGDER)". When this transfer size #1 is not 4 bytes, the transfer byte position is left-aligned. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 417 [23:16] [15:8] SGDMAR SGDMAR SGDMAR SGDMAR [31:24] [23:16] [15:8] [7:0] *1: The transfer size which is calculated by the setting of SGDER.ARE1, SGDER.ARE0, SGDER.FRE, and SGDER.NRE. - : Do not care. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 418 [23:16] SGDMAR SGDMAR [31:24] [23:16] SGDMAR SGDMAR SGDMAR [31:24] [23:16] [15:8] SGDMAR [31:24] SGDMAR SGDMAR [31:24] [23:16] SGDMAR SGDMAR [31:24] [23:16] SGDMAR SGDMAR SGDMAR [31:24] [23:16] [15:8] SGDMAR SGDMAR [31:24] [23:16] S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 419 ← The amplitude data (upper byte) / SGAR[15:8] SGDMAR[23:16] ← The tone output number / SGNR[7:0] SGDMAR[15:0] ← Do not care The second SGDMAR[31:24] ← The increment and decrement data / SGIDR[7:0] SGDMAR[23:0] ← Do not care S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 420 [31:24] [23:16] [15:8] [7:0] DMA transfer (4) - 2 SGAR SGAR SGFR SGNR [15:8] [7:0] [7:0] [7:0] SGIDR [7:0] SGTCR SGIDR SGPCR SGPCR [7:0] [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 421 Moreover, set other information to the Sound Control Register (SGCR) to control the Sound Generator. Initialize the Interrupt status bit (SGCR.INT) and set the Interrupt enable bit (SGCR.INTE). (2) Write "1" to the Start bit (SGCR.ST). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 422 - Amplitude Data Register (SGAR) - Frequency Data Register (SGFR) - Time Cycle Register (SGTCR) - Tone Output Number Register (SGNR) - Increase and Decrease Data Register (SGIDR) - PWM Cycle Data Register (SGPCR) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 423 - Decrement counter is 0x00 - At the rising edge of SGO (6) MCU clears the interrupt. (7) Software writes "0" to the Start bit (SGCR.ST) to stop outputting the sound. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 424 Time Cycle Register (SGTCR) Increase and Decrease Data Register (SGIDR) PWM Cycle Data Register (SGPCR) SGO, SGA output #n+1 (11) Interrupt Interrupt Clear Register (SGCCR) - Clearing interrupt Sound Control Register (SGCR) Stop (12) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 425 In case of switching the selection of increase/decrease, it is needed to write "Increase/decrease setting bit (SGCR.GID)" and the "Automatic increase/decrease enable bit (SGCR.GEN)" in the Sound Control Register (SGCR) within above-mentioned limit time. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 426 DMA Transfer Intermediate Register (SGDMAR) which works as a window register. Note: − Software needs to set the Interrupt enable bit (SGCR.INTE="1") in order to use the Interrupt request (PIRQ) as a DMA transfer request. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 427 Interrupt (13) (15) (14) Sound Control Register (SGCR) Stop (16) If the current tone cycle is outputting, the SGO and SGA output stops when the current tone cycle output is finished. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 428 (7) The outputs of SGO and SGA start, according to the register settings above. (8) The Tone pulse counter counts the number of tone pulses. When the following conditions are satisfied, the interrupt is generated. - Tone pulse counter is 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 429 The DMA transfer error means the occurrence of delay in the sound data setting. It causes unsteady sound output. In that case, please fix the priority of DMA transfer in the system to finish all data transfer within the limit time. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 430 Interrupt (14) (16) (15) Sound Control Register (SGCR) Stop (17) If the current tone cycle is outputting, the SGO and SGA output stops when the current tone cycle output is finished. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 431 (9) The Tone pulse counter counts the number of tone pulses. When the following conditions are satisfied, the interrupt is generated. - Tone pulse counter is 0x00 - Decrement counter is 0x00 - At the rising edge of SGO S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 432 The DMA transfer error means the occurrence of delay in the sound data setting. It causes unsteady sound output. In that case, please fix the priority of DMA transfer in the system to finish all data transfer within the limit time. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 433 Interrupt (14) Sound Control Register (SGCR) (16) (15) Stop (17) If the current tone cycle is outputting, the SGO and SGA output stops when the current tone cycle output is finished. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 434 (*3: DMA block size must to be "1-byte size x 1" for the access to "DMA Transfer Intermediate Register (SGDMAR)") (11) The Sound Generator keeps outputting SGO and SGA, according to the register settings above. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 435 The DMA transfer error means the occurrence of delay in the sound data setting. It causes unsteady sound output. In that case, please fix the priority of DMA transfer in the system to finish all data transfer within the limit time. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 436 #n+m+x+1 (17) (19) (18) Sound Control Register (SGCR) Stop (20) If the current tone cycle is outputting, the SGO and SGA output stops when the current tone cycle output is finished. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 437 (7) The outputs of SGO and SGA start, according to the register settings above. (8) The Tone pulse counter counts the number of tone pulses. When the following conditions are satisfied, the interrupt is generated. - Tone pulse counter is 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 438 Mth DMA transfer. Then, the Sound Generator stops driving SGO and SGA after the end of all data. (*4: The data of the Mth DMA transfer are written to the Sound Generator, and they are output to the end.) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 439 The DMA transfer error means the occurrence of delay in the sound data setting. It causes unsteady sound output. In that case, please fix the priority of DMA transfer in the system to finish all data transfer within the limit time. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 440 #n+m+x+1 (17) Sound Control Register (SGCR) (19) (18) Stop (20) If the current tone cycle is outputting, the SGO and SGA output stops when the current tone cycle output is finished. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 441 (7) The outputs of SGO and SGA start, according to the register settings above. (8) The Tone pulse counter counts the number of tone pulses. When the following conditions are satisfied, the interrupt is generated. - Tone pulse counter is 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 442 The DMA transfer error means the occurrence of delay in the sound data setting. It causes unsteady sound output. In that case, please fix the priority of DMA transfer in the system to finish all data transfer within the limit time. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 443 [SGTCR] + 1" and "Tone Output Number Register [SGNR] + 1", the Interrupt status bit (SGCR.INT) is set. When the interrupt is allowed by the setting of SGCR.INTE, an Interrupt request (PIRQ) is subsequently asserted (to be "H"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 444 0x00000000 Reserved SGDER SGCR B, H, W 0x00000004 SGAR SGFR SGNR B, H, W 0x00000008 SGTCR SGIDR SGPCR B, H, W 0x0000000C SGDMAR B, H, W 0x00000010 Reserved SGCCR H, W S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 445 This bit is to enable the update of the frequency data of the Frequency Data Register (SGFR) through the DMA Transfer Intermediate Register when in DMA transfer. Description The update of the frequency data is disabled. The update of the frequency data is enabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 446 (SGPCR) through the DMA Transfer Intermediate Register when in DMA transfer. Description The update of the PWM cycle data (lower byte) is disabled. The update of the PWM cycle data (lower byte) is enabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 447 Writing "1" to the Start bit (ST) does not make the Interrupt status bit (INT) set. Writing "1" to the Start bit (ST) makes the Interrupt status bit (INT) set. Note: − Do not change this setting while operating (ST="1"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 448 When this bit turns from "enabled" to "disabled", the Amplitude Data Register (SGAR) holds the value at that time. [bit10] Reserved : Reserved bit Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 449 This bit controls whether to enable the output of SGO. Description SGO output is disabled. SGO output is enabled. [bit3] SGAOE : SGA signal output enable bit This bit controls whether to enable the output of SGA. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 450 Whether the Sound Generator is stopped or not can be seen on the status bit BUSY. − This bit is cleared also when a software reset is issued (SRST = "1"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 451 (2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse. (The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle) When it meets neither condition, the sound output cannot guarantee the expected duty ratio. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 452 (2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse. (The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle) When it meets neither condition, the sound output cannot guarantee the expected duty ratio. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 453 (2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse. (The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle) When it meets neither condition, the sound output cannot guarantee the expected duty ratio. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 454 (2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse. (The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle) When it meets neither condition, the sound output cannot guarantee the expected duty ratio. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 455 (2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse. (The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle) When it meets neither condition, the sound output cannot guarantee the expected duty ratio. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 456 (2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse. (The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle) When it meets neither condition, the sound output cannot guarantee the expected duty ratio. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 457 − When in reading corresponding registers (not through this register), please make sure the setting of "DMA Transfer Update Enable Register (SGDER)" is available for the target registers. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 458 (2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse. (The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle) When it meets neither condition, the sound output cannot guarantee the expected duty ratio. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 459 The read value is "0". Description Write No effect. Interrupt status bit (SGCR.INT) is cleared. [bit0] Reserved : Reserved bit Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 460 Sound Waveform Generator CHAPTER 19: This chapter explains the sound waveform generator. Overview Configuration and Block Diagram Operation of the Sound Waveform Generator Registers CODE: SOUNDWFG-E1.06-0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 461 Use of the Low Pass Filter can be disabled. When using the Low Pass Filter, the optimum cutoff frequency should be decided upon sufficient evaluation of sound quality on the system. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 462 Configuration and Block Diagram This section shows a block diagram of the sound waveform generator. Figure 2-1 Output Sound waveform generator destination Data request Data request Start Parameter PCM sound source synthesizer S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 463 Start idle time is silence generation time immediately following sound source generation start. End idle time is not supported. As for start idle time, one of 32 idle times from 0 ms to 4 seconds is selectable by software. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 464 If the total of these times exceeds the run time, fade in will start from -96 dB and a switch will be made to fade out before 0 dB is reached. − Each configuration should be under condition below. Attack ≤ FSLEN, Release ≤ FSLEN and Attack + Release ≤ FSLEN S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 465 Sound source generation can also be stopped by WGCHCLR under 4.10. However, there is no control to restart sound source generation from the point it was stopped by WGCHCLR. ALL 0 is output from channels that are stopped by WGCHCLR. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 466 The FLSEN should be configured as longer than RELEASE. Only when the final sound source of consecutive sound generation is generated, RELEASE only performs and FSLEN is ignored in generation time. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 467 See 4.7 in detail. Figure 3-3 Cutoff Frequency 8 kHz filter1 frequency response -100 Frequency (Hz) x 10 Figure 3-4 Cutoff Frequency 5 kHz filter2 frequency response -100 Frequency (Hz) x 10 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 468 CHAPTER 19:Sound Waveform Generator Figure 3-5 Cutoff Frequency 2 kHz filter3 frequency response -100 Frequency (Hz) x 10 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 469 PROT_TYPE INITIAL_VALUE [bit31:5] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". [bit4] CH4EN: Channel 4 operation enable/disable [bit3] CH3EN: Channel 3 operation enable/disable S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 470 There is no sound source output, including ALL 0, from channels that are stopped by this control. The effect on sound source output destinations should be kept firmly in mind when stopping sound source generation. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 471 [bit4] CH4START: Channel 4 sound source generation start [bit3] CH3START: Channel 3 sound source generation start [bit2] CH2START: Channel 2 sound source generation start [bit1] CH1START: Channel 1 sound source generation start S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 472 Changing sound source specifications during sound source generation start standby can result in sound source generation starting while implementation of changes is in progress, resulting in unintended sound being produced. Set sound source specifications while sound source generation is enabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 473 [bit28:16] CH1ADD: Channel 1 output destination address Sets the Channel 1 output destination address as 13 bits. Notes: These bits can be set at the initialization. After that, it should not be changed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 474 [bit12:0] CH0ADD: Channel 0 output destination address Sets the Channel 0 output destination address as 13 bits. Notes: These bits can be set at the initialization. After that, it should not be changed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 475 [bit28:16] CH3ADD: Channel 3 output destination address Sets the Channel 3 output destination address as 13 bits. Notes: These bits can be set at the initialization. After that, it should not be changed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 476 [bit12:0] CH2ADD: Channel 2 output destination address Sets the Channel 2 output destination address as 13 bits. Notes: These bits can be set at the initialization. After that, it should not be changed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 477 [bit12:0] CH4ADD: Channel 4 output destination address Sets the Channel 4 output destination address as 13 bits. Notes: These bits can be set at the initialization. After that, it should not be changed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 478 Always write "0" to this bit. The read value is "0". [bit9:8] CH4MONO Channel 4 output data pattern [bit7:6] CH3MONO Channel 3 output data pattern [bit5:4] CH2MONO Channel 2 output data pattern [bit3:2] CH1MONO Channel 1 output data pattern S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 479 (n=0 to 4) Upper and lower 16 bits output the same data (XXXX_XXXX). Only lower 16 bits of data are output (0000_XXXX). Only upper 16 bits of data are output (XXXX_0000). Setting prohibited S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 480 This bit is reserved. Always write "0" to this bit. The read value is "0". [bit20:16] FSLEN: Run time (Channel n = 0 to 4) Specifies a setting of 1 ms to 4 seconds. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 481 This bit is reserved. Always write "0" to this bit. The read value is "0". [bit9:8] FSINF: Waveform (Channel n = 0 to 4) Bits Description Sine wave Sawtooth wave Square wave S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 482 130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.08 246.94 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 523.25 554.37 587.33 622.25 659.26 698.46 739.99 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 483 Musical Scale 783.99 830.61 880.00 932.33 987.77 1046.50 1108.73 1174.66 1244.51 1318.51 1396.91 1479.98 1567.98 1661.22 1760.00 1864.66 1975.53 2093.00 2217.46 2349.32 2489.02 2637.02 2793.83 2959.96 3135.96 3322.44 3520.00 3729.31 3951.07 4186.01 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 484 This bit is reserved. Always write "0" to this bit. The read value is "0". [bit20:16] ITVAL2: End idle time (Channel n = 0 to 4) This function is not supported. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 485 125ms 10001 150ms 10010 200ms 10011 250ms 10100 300ms 10101 400ms 10110 500ms 10111 750ms 11000 1000ms 11001 1250ms 11010 1500ms 11011 2000ms 11100 2500ms 11101 3000ms 11110 3500ms 11111 4000ms S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 486 PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME Reserved Reserved Reserved ATTACK[4:0] ACCESS_TYPE R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE [bit31:18] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 487 Fade in/fade out control not used. 00001 00010 00011 00100 00101 00110 7.5ms 00111 10ms 01000 15ms 01001 20ms 01010 25ms 01011 30ms 01100 40ms 01101 50ms 01110 75ms 01111 100ms 10000 125ms S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 488 When using fade in control, consecutive fade in control cannot be used without fade out control. Also, when using fade out control, consecutive fade out control cannot be used without fade in control. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 489 Always write "0" to this bit. The read value is "0". [bit4] CH4CL: Channel 4 sound source initialization [bit3] CH3CL: Channel 3 sound source initialization [bit2] CH2CL: Channel 2 sound source initialization [bit1] CH1CL: Channel 1 sound source initialization S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 490 If sound source specifications are initialized, generation cannot be resumed from the point where it was stopped. To generate a source, sound source specifications need to be set again and sound source generation start control is required. See 3.1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 491 [bit12] CH4END: Channel 4 sound source generation end interrupt enable [bit11] CH3END: Channel 3 sound source generation end interrupt enable [bit10] CH2END: Channel 2 sound source generation end interrupt enable [bit9] CH1END: Channel 1 sound source generation end interrupt enable S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 492 [bit7:1] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". [bit0] AHBERR: AHB MASTER INTERFACE bus error interrupt enable Description Disable interrupts. Enable interrupts. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 493 Writing to this bit generates an SWFG AHB Slave interface access error. [bit12] CH4END: Channel 4 sound source generation end interrupt status indication [bit11] CH3END: Channel 3 sound source generation end interrupt status indication S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 494 [bit0] AHBERR: SWFG AHB MASTER INTERFACE bus error interrupt status indication Description No interrupt Interrupt Notes: − This bit is read-only, and writing is prohibited. − Writing to this bit generates an SWFG AHB Slave Interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 495 [bit12] CH4END: Channel 4 sound source generation end interrupt clear [bit11] CH3END: Channel 3 sound source generation end interrupt clear [bit10] CH2END: Channel 2 sound source generation end interrupt clear [bit9] CH1END: Channel 1 sound source generation end interrupt clear S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 496 [bit0] AHBERR: SWFG AHB MASTER INTERFACE bus error interrupt clear Explanation of AHBERR Description Does not have any effect on operation. Clear interrupts. Note: − If interrupt generation and interrupt clear occur simultaneously, interrupt generation is given priority. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 497 Always write "0" to this bit. The read value is "0". This bit is read-only, and writing is prohibited. Writing to this bit generates an SWFG AHB Slave interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 498 Write access to Read Only register Access size error Notes: − This bit is read-only, and writing is prohibited. − Writing to this bit generates an SWFG AHB Slave Interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 499 Sound Mixer CHAPTER 20: This chapter explains the sound mixer. Overview Configuration and Block Diagram Operation of the Sound Mixer Registers Appendix CODE: SOUNDMIX-E1.08-0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 500 Sound mixing supports individual volume control for each channel, so adjustments can be made while evaluating the result on the system. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 501 The AHB master outputs the mixed sound source to the address specified as the output destination. − Every channel of WFG0 to 4 has an input buffer for a word (32bit) in the part of "input control". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 502 In the step 5, completion of the initialization is required before executing the next step. Completion can be confirmed by reading the applicable bit of the MXBUFFCLR register, because the bit is automatically cleared to 0 following initialization. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 503 0 dB to -96 dB. However, this initialization operation is not necessarily required for fade out following fade in. This is because fade in causes gain to become 0 dB. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 504 The fade in/out gain is 0 dB for both the fade in ending point and the fade out starting point. The gain of the overall volume effect is determined in accordance with the volume control gain set by software. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 505 A change in processing mode made while sound source is transferred to the sound source input channels PMIS0 through PMIS4 is prohibited. − Monaural processing cannot be used on a 32-bit stereo sound source. Attempting to do so will result in improper sound. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 506 MX_DMA_REQ[0] is for PMIS Channel 0, while MX_DMA_REQ[4] is for PMIS Channel 4. Notes: If the DMAC is used for the sound source transmission, the corresponding DMAEN bit of MXDRQCTRL is set to 0 after the DMA-transmission is completed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 507 WFG Dedicated AHB Slave Interface 3.7.2. Table 3-4 WFG AHB Slave interface Item Table_Header Burst transfer not support Protection control not support Response OKAY and ERROR only Access size 8,16,32bit only Width of address 10bit S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 508 The configuration of the input buffer is shown in Table 3-6. Table 3-6 Outline of input Buffer Item Description Width of data 32bit Width of address 7bit Depth 160(32×5ch) Composition Dual Port RAM S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 509 Sufficient evaluation with the actual device is recommended. − Filter characteristics have been selected based on Cypress rules. − See 5.3 in detail. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 510 WFG0 ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:10] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". [bit9] PMIS4: PMIS4 input setting [bit8] PMIS3: PMIS3 input setting S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 511 WFGn Description (n=0 to 4) WFGn input invalid WFGn input valid Note: − Configuring invalid, the channel will be out of mixing operation not depending on the left data on buffer. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 512 Reserved Reserved Reserved MACRO[2] MACRO[1] MACRO[0] ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE [bit31:12] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 513 Always write "0" to this bit. The read value is "0". [bit2:0] MACRO[2:0]: Output destination address Bit[2:0] Description Specifies [12:10] of the AHB bus address. Notes: These bits can be set at the initialization. After that, it should not be changed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 514 Always write "0" to this bit. The read value is "0". [bit28] DMAENCH4: DMA transfer to PMIS4 request setting [bit27] DMAENCH3: DMA transfer to PMIS3 request setting [bit26] DMAENCH2: DMA transfer to PMIS2 request setting S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 515 7. This is because twice the buffer capacity is needed to perform the internal process shown in 3.3 on the monaural sound source. − FESTCHn bits must not be changed when DMAENCHn bit is 1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 516 Always write "0" to this bit. The read value is "0". [bit18:16] PMIS4FREQ: Input sampling frequency to PMIS4 [bit15] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 517 Operation when 44.1 kHz is applied to multiple channels cannot be guaranteed from the viewpoint of the mixing process load imposed by the sound mixer. It should be noted that there may limits on specific models concerning the selection of other frequencies. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 518 R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME PMIS3MONO[1:0] PMIS2MONO[1:0] PMIS1MONO[1:0] PMIS0MONO[1:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:10] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 519 Monaural process L (Upper 16 bits = Monaural sound source, Lower 16 bits = ALL 0). Monaural process LR (Upper 16 bits = Lower 16 bits = Monaural sound source). Notes: − These bits must not be changed during sound source transmission of the channel. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 520 [bit23:16] WFG2VOL: Gain setting for WFG2 volume control [bit15:8] WFG1VOL: Gain setting for WFG1 volume control [bit7:0] WFG0VOL: Gain setting for WFG0 volume control For details about Gain settings for volume control, see 5.1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 521 [bit23:16] PMIS1VOL: Gain setting for PMIS1VOL volume control [bit15:8] PMIS0VOL: Gain setting for PMIS0VOL volume control [bit7:0] WFG4VOL: Gain setting for WFG4 volume control For details about Gain settings for volume control, see 5.1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 522 [bit23:16] MXDVOL: Gain setting for mixed sound source volume control [bit15:8] PMIS4VOL: Gain setting for PMIS4VOL volume control [bit7:0] PMIS3VOL: Gain setting for PMIS3VOL volume control For details about Gain settings for volume control, see 5.1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 523 PROT_TYPE INITIAL_VALUE [bit31:11] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". [bit10] MXDMUTE: Mixed sound source MUTE setting Description Disable mute. Enable mute. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 524 [bit2] WFG2MUTE: WFG2 input sound source MUTE setting [bit1] WFG1MUTE: WFG1 input sound source MUTE setting [bit0] WFG0MUTE: WFG0 input sound source MUTE setting WFGnMUTE Description (n=0 to 4) Disable mute. Enable mute. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 525 Always write "0" to this bit. The read value is "0". [bit28:24] WFG1FADEOUT: WFG1 fade out time setting [bit23:21] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 526 Always write "0" to this bit. The read value is "0". [bit4:0] WFG0FADEIN: WFG0 fade in time setting For details about fade in and fade out time settings for volume control, see 5.2. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 527 Always write "0" to this bit. The read value is "0". [bit28:24] WFG3FADEOUT: WFG3 fade out time setting [bit23:21] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 528 Always write "0" to this bit. The read value is "0". [bit4:0] WFG2FADEIN: WFG2 fade in time setting For details about fade in and fade out time settings for volume control, see 5.2. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 529 Always write "0" to this bit. The read value is "0". [bit28:24] PMIS0FADEOUT: PMIS0 fade out time setting [bit23:21] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 530 Always write "0" to this bit. The read value is "0". [bit4:0] WFG4FADEIN: WFG4 fade in time setting For details about fade in and fade out time settings for volume control, see 5.2. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 531 Always write "0" to this bit. The read value is "0". [bit28:24] PMIS2FADEOUT: PMIS2 fade out time setting [bit23:21] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 532 Always write "0" to this bit. The read value is "0". [bit4:0] PMIS1FADEIN: PMIS1 fade in time setting For details about fade in and fade out time settings for volume control, see 5.2. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 533 INITIAL_VALUE [bit31:29] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". [bit28:24] PMIS4FADEOUT: PMIS4 fade out time setting [bit23:21] Reserved This bit is reserved. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 534 Always write "0" to this bit. The read value is "0". [bit4:0] PMIS3FADEIN: PMIS3 fade in time setting For details about fade in and fade out time settings for volume control, see 5.2. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 535 Always write "0" to this bit. The read value is "0". [bit4:0] MXDFADEIN: Mixed sound source fade in time setting For details about fade in and fade out time settings for volume control, see 5.2. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 536 PMIS0FADEEN[1:0] WFG4FADEEN[1:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME WFG3FADEEN[1:0] WFG2FADEEN[1:0] WFG1FADEEN[1:0] WFG0FADEEN[1:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:22] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 537 [bit3:2] WFG1FADEEN: WFG1 fade in/out operation setting [bit1:0] WFG0FADEEN: WFG0 fade in/out operation setting WFGnFADEEN[1:0] Description (n=0 to 4) No fade in/fade out Setting prohibited Enable fade in operation start. Enable fade out operation start. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 538 WFG1 WFG0 BIT_NAME BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:11] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 539 Initialize buffer (This bit automatically cleared to 0 Initialization wait following initialization.) Note: − Every channel of WFG0 to 4 has an input buffer for a word (32bit) in the part of "input control". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 540 INITIAL_VALUE BIT_OFFSET PMIS2 PMIS1 PMIS0 WFG4 WFG3 WFG2 WFG1 WFG0 BIT_NAME ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:11] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 541 Initialize fade state (This bit automatically cleared Initialization wait to 0 following initialization.) Note: − "1" writing to initialize should be done after all the bits of MXFADECLR to be "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 542 PMIS1 PMIS0 BIT_NAME Reserved Reserved Reserved BUFDREQ BUFDREQ BUFDREQ BUFDREQ BUFDREQ ACCESS_TYPE R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE [bit31] AHBERR: AHB Master interface bus error interrupt setting Description Disable interrupts. Enable interrupts. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 543 [bit8] PMIS0BUFOVFL: PMIS0 input buffer overflow interrupt setting PMISnBUFOVFL Description (n=0 to 4) Disable interrupts. Enable interrupts. [bit7:5] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 544 When use of DMA request is disabled by the setting of MSDRQCTRL under 4.3, be sure to disable DMA transfer error interrupt. Failure to do so can result in generation of unexpected interrupts. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 545 R,WX R,WX R,WX PROT_TYPE INITIAL_VALUE [bit31] AHBERR: AHB master interface bus error indication Description No error/no transfer request Error/transfer request present Notes: − This bit is read-only, and writing is prohibited. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 546 [bit11] PMIS3BUFOVFL: PMIS3 input buffer overflow error indication [bit10] PMIS2BUFOVFL: PIS2 input buffer overflow error indication [bit9] PMIS1BUFOVFL: PMIS1 input buffer overflow error indication [bit8] PMIS0BUFOVFL: PMIS0 input buffer overflow error indication S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 547 No error/no transfer request Error/transfer request present Notes: − This bit is read-only, and writing is prohibited. − Writing to this bit generates a sound mixer AHB Slave Interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 548 BUFDREQ ACCESS_TYPE RX,W0 RX,W0 RX,W0 RX,W RX,W RX,W RX,W RX,W PROT_TYPE INITIAL_VALUE [bit31] AHBERR: AHB master interface bus error interrupt clear Description Does not have any effect on operation. Clear interrupts. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 549 PMISnBUFOVFL Description (n=0 to 4) Does not have any effect on operation. Clear interrupts. [bit7:5] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 550 [bit0] PMIS0BUFDREQ: PMIS0 data transfer request interrupt clear PMISnBUFDREQ Description (n=0 to 4) Does not have any effect on operation. Clear interrupts. Note: − If interrupt generation and interrupt clear occur simultaneously, interrupt generation is given priority. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 551 R0,W0 R0,W0 R,WX R,WX R,WX R,WX R,WX R,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME Reserved Reserved Reserved WFG4C WFG3C WFG2C WFG1C WFG0C ACCESS_TYPE R0,W0 R0,W0 R0,W0 R,WX R,WX R,WX R,WX R,WX PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 552 111111 Notes: − This bit is read-only, and writing is prohibited. − Writing to this bit generates a sound mixer AHB Slave Interface access error. [bit15:14] Reserved This bit is reserved. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 553 (n=0 to 4) Without data With data Notes: − This bit is read-only, and writing is prohibited. − Writing to this bit generates a sound mixer AHB Slave Interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 554 Always write "0" to this bit. The read value is "0". This bit is read-only, and writing is prohibited. Writing to this bit generates a sound mixer AHB Slave interface access error. [bit13:8] PMIS4CNT[5:0]: Input buffer used volume indication S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 555 Buffer is empty. 000001 Used input buffer volume 111111 Notes: − This bit is read-only, and writing is prohibited. − Writing to this bit generates a sound mixer AHB Slave Interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 556 This bit is read-only, and writing is prohibited. Writing to this bit generates a sound mixer AHB Slave interface access error. [bit27:24] PMIS4CNT[3:0]: PMIS4 internal buffer used volume indication [bit23:20] PMIS3CNT[3:0]: PMIS3 internal buffer used volume indication S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 557 (n=0 to 4) Buffer is empty. Internal buffer used Notes: − This bit is read-only, and writing is prohibited. − Writing to this bit generates a sound mixer AHB Slave Interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 558 Always write "0" to this bit. The read value is "0". This bit is read-only, and writing is prohibited. Writing to this bit generates a sound mixer AHB Slave interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 559 Buffer is empty. 000001 Output buffer used volume 111111 Notes: − This bit is read-only, and writing is prohibited. − Writing to this bit generates a sound mixer AHB Slave Interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 560 Always write "0" to this bit. The read value is "0". This bit is read-only, and writing is prohibited. Writing to this bit generates a sound mixer AHB Slave interface access error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 561 [bit7:6] WFG3ERR[1:0]: AHB Slave interface WFG3 transfer access error information indication [bit5:4] WFG2ERR[1:0]: AHB Slave interface WFG2 transfer access error information indication [bit3:2] WFG1ERR[1:0]: AHB Slave interface WFG1 transfer access error information indication S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 562 Every address error during transmission to WFG0 through 4 is informed to WFG0ERR[1:0]. It is also informed to CNTREGERR[1:0] during transmission to PMIS0 through 4. − Every write access error of Read Only register is informed to CNTREERR[1:0]. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 563 [bit31:0] WFGnDADR [31:0]: WFGn input data register Notes: − Because Sound waveform generator output has a fixed connection to this register, this register cannot be written to from the CPU. Writing generates an error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 564 R0,W R0,W R0,W PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME PMIS n DADR0 to 15[7:0] ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W PROT_TYPE INITIAL_VALUE [bit31:0] PMISnDADR0 to 15[31:0]: PMIS input data register S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 565 -96.0 00011001 0.000016 -96.0 00011010 0.000016 -96.0 00011011 0.000016 -96.0 00011100 0.000016 -96.0 00011101 0.000016 -96.0 00011110 0.000016 -96.0 00011111 0.000016 -96.0 00100000 0.000016 -96.0 00100001 0.000016 -96.0 00100010 0.000016 -96.0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 566 -83.5 01000001 0.000071 -83.0 01000010 0.000075 -82.5 01000011 0.000079 -82.0 01000100 0.000084 -81.5 01000101 0.000089 -81.0 01000110 0.000094 -80.5 01000111 0.000100 -80.0 01001000 0.000106 -79.5 01001001 0.000112 -79.0 01001010 0.000119 -78.5 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 567 -63.5 01101001 0.000708 -63.0 01101010 0.000750 -62.5 01101011 0.000794 -62.0 01101100 0.000841 -61.5 01101101 0.000891 -61.0 01101110 0.000944 -60.5 01101111 0.001000 -60.0 01110000 0.001059 -59.5 01110001 0.001122 -59.0 01110010 0.001189 -58.5 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 568 -43.5 10010001 0.007079 -43.0 10010010 0.007499 -42.5 10010011 0.007943 -42.0 10010100 0.008414 -41.5 10010101 0.008913 -41.0 10010110 0.009441 -40.5 10010111 0.010000 -40.0 10011000 0.010593 -39.5 10011001 0.011220 -39.0 10011010 0.011885 -38.5 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 569 -23.5 10111001 0.070795 -23.0 10111010 0.074989 -22.5 10111011 0.079433 -22.0 10111100 0.084140 -21.5 10111101 0.089125 -21.0 10111110 0.094406 -20.5 10111111 0.100000 -20.0 11000000 0.105925 -19.5 11000001 0.112202 -19.0 11000010 0.118850 -18.5 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 570 0.630957 -4.0 11100000 0.668344 -3.5 11100001 0.707946 -3.0 11100010 0.749894 -2.5 11100011 0.794328 -2.0 11100100 0.841395 -1.5 11100101 0.891251 -1.0 11100110 0.944061 -0.5 11100111 1.000000 11101000 1.059254 11101001 1.122018 11101010 1.188502 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 571 11110011 1.995262 11110100 2.113489 11110101 2.238721 11110110 2.371374 11110111 2.511886 11111000 2.660725 11111001 2.818383 11111010 2.985383 11111011 10.0 3.162278 11111100 10.5 3.349654 11111101 11.0 3.548134 11111110 11.5 3.758374 11111111 12.0 3.981072 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 572 2000ms (96000 sample) 11001 2000ms (96000 sample) 11010 2000ms (96000 sample) 11011 2000ms (96000 sample) 11100 2000ms (96000 sample) 11101 2000ms (96000 sample) 11110 2000ms (96000 sample) 11111 2000ms (96000 sample) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 573 Figure 5-1 24kHz 11kHz Figure 5-2 12kHz 5kHz Figure 5-3 8kHz 3kHz Figure 5-4 4kHz 1,2kHz Figure 5-5 Figure 5-1 Filter No 1 filter44 frequency response -100 Frequency (Hz) x 10 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 574 CHAPTER 20:Sound Mixer Figure 5-2 Filter No 2 filter24 frequency response -100 Frequency (Hz) x 10 Figure 5-3 Filter No 3 filter12 frequency response -100 Frequency (Hz) x 10 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 575 CHAPTER 20:Sound Mixer Figure 5-4 Filter No 4 filter08 frequency response -100 Frequency (Hz) x 10 Figure 5-5 Filter No 5 filter04 frequency response -100 Frequency (Hz) x 10 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 576 Ethernet MAC CHAPTER 21: This chapter explains the function and operation of the Ethernet MAC module. Overview Configuration and Block Diagram Operation of the Ethernet MAC Registers Functional Limitations CODE: ETHRNET-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 577 Priority based Flow Control (IEEE Std 802.1Qbb) Physical sublayer PPPoE Point-to-Point Protocol over Ethernet Precision Time Protocol (IEEE Std 1588) RFC 791 DARPA Internet Program Protocol Specification SerDes Serialiser/Deserialiser Start of Frame Delimiter S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 578 Serial Gigabit Media Independent Interface SNAP Subnetwork Access Protocol Start Of Frame Transfer Control Protocol Timestamp Timestamp Unit User Datagram Protocol VLAN Virtual LAN (IEEE Std 802.1Q) 10-Gigabit/s Electrical Interface Specification S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 579 CHAPTER 21:Ethernet MAC Configuration and Block Diagram This section shows a block diagram of the Ethernet MAC. Figure 2-1: Ethernet MAC Block Diagram S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 580 The maximum burst lengths the Ethernet MAC will use are programmable. Single accesses and bursts with up to 16 beats can be selected. With 64-bit data path and a burst length setting of 16, 128 Bytes S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 581 Transfer size is set to 64-bit words by default in the Network Configuration register (ETHERNETn_network_configuration) and burst length can be programmed in the range from single access up to 16 accesses per burst using the DMA Configuration register (ETHERNETn_dma_config). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 582 15 and 14 of the Network Configuration register (receive_buffer_offset[1:0]) and bit 2 of Word 0. Table 3-1: Receive Buffer Byte Offset Configuration Receive Buffer Offset Number of Bytes Receive_Buffer_Offset[1] Receive_Buffer_Offset[0] Configuration Bit 2 Offset of Word 0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 583 0 - The frame was not SNAP encoded and/or had a VLAN tag with the CFI bit set. 1 - The frame was SNAP encoded and had either no VLAN tag or a VLAN tag with the CFI bit set. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 584 With ignore FCS mode enabled and jumbo frames disabled: This indicates per frame FCS status as follows: 0 - Frame had good FCS 1 - Frame had bad FCS, but was copied to memory as ignore FCS is enabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 585 Previous buffers will not be recovered. As an example, when receiving frames with CRC errors or excessive length, it is possible that S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 586 Data Buffer Address Mask register for further details. Note that any changes to this register will be ignored while the Ethernet MAC DMA is currently processing a receive packet. It will only affect the next full packet to be written to system memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 587 Wrap - marks last descriptor in transmit buffer descriptor list. This can be set for any buffer within the frame. Retry limit exceeded, transmit error detected Unused S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 588 Length of buffer. When Descriptor Timestamp Capture mode is enabled, the following table identifies the added descriptor words. Function Word 2 31:30 Timestamp seconds [1:0] (see Note1) 29:0 Timestamp nanoseconds [29:0] (see Note1) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 589 For packet buffer mode, the entire contents of the frame are read into the TX Packet Buffer Memory, so the retry attempt will be replayed directly from the TX Packet Buffer Memory rather than having to re-fetch through AXI Master Interface. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 590 Retry collided transmit frames from the buffer, thus saving AXI bus bandwidth. − Implement transmit IP/TCP/UDP checksum generation offload. The following figure illustrates the structure of the Ethernet MAC data paths. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 591 TX DMA interface of the buffer from the MAC Transmitter interface, to update the MAC status/statistics and to generate interrupts in the order in which the packets that they represent were fetched from the system memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 592 For full store and forward, the RX DMA will only begin packet fetches once the status and statistics for a frame are available. If the frame has a bad status due to a frame error, the status and statistics are S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 593 0x480. Every received packet will pass through a programmable screening algorithm which will allocate to that frame a S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 594 When a screener is matched, the received frame will be routed to a queue defined inside bits [3:0] of the screener register (ETHERNETn_screening_type_1_register_i or ETHERNETn_screening_type_2_register_i). Unmatched frames are routed to Queue 0. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 595 [15:8] (1 added so as not to get a divide by zero) divides the frame length to generate the IPG. The IPG Stretch register cannot be used to shrink the IPG below 96 bits. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 596 To calculate these checksums in software requires each byte of the packet to be processed. For TCP and UDP this can use a large amount of processing power. Offloading the checksum calculation to hardware can result in significant performance improvements. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 597 FCS field, by making sure that bit 16 of the transmit descriptor Word 1 is clear (VLAN tagged frames will be recognized but stacked VLAN tagged frames will S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 598 The encoded Type ID match bits (Word 0, bit 22 and bit 23) in the receive buffer descriptor status are set indication which Type ID Match register generated the match, if the receive checksum offload is disabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 599 = da[02] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[01] = da[01] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 600 Bit 16 set to CFI if bit 21 is set. The Ethernet MAC can be configured to reject all frames except VLAN tagged frames by setting the discard non-VLAN frames bit in the Network Configuration register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 601 IEEE Std 1588 version 2 (UDP/IPv4 unicast) IEEE Std 1588 version 2 (UDP/IPv4 unicast with VLAN) IEEE Std 1588 version 2 (UDP/IPv6 multicast) IEEE Std 1588 version 2 (UDP/IPv6 multicast with VLAN) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 602 For IEEE Std 1588 version 1 messages Sync and Delay_Req frames are indicated by the Ethernet MAC if the frames type field indicates TCP/IP, UDP protocol is indicated, the destination IP address is S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 603 DA (Octets 0 – 5) SA (Octets 6 – 11) Type (Octets 12 – 13) 86DDh IP stuff (Octets 14 – 19) UDP (Octet 20) IP stuff (Octets 21 – 37) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 604 00h for Sync, 02h for Pdelay_Req and 03 for Pdelay_Resp: Preamble/SFD 55555555555555D5 DA (Octets 0 – 5) 0180C200000E SA (Octets 6 – 11) Type (Octets 12 – 13) 88F7h message type (Octet 14) version PTP (Octet 15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 605 [29:28] in the DMA Configuration register. The timestamp can be captured for a number of frame types (PTP event or PTP general, or all frames, or none as defined in TX BD Control/RX S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 606 The Ethernet MAC supports both hardware controlled pause of the transmitter upon reception of a pause frame and hardware generated pause frame transmission. Note: See Clause 31, and Annex 31A and 31B of the IEEE Std 802.3 for a full description of pause operation. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 607 Transmitted pause frames comprise of the following: − A destination address of 0180C2000001 − A source address taken from Specific Address 1 register − A Type ID of 8808 (MAC control frame) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 608 0101 Pause frames that have FCS or other errors will be treated as invalid and will be discarded. Valid pause frames received will increment the Pause Frames Received statistic register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 609 Pause Frames Transmitted register. PFC Pause frames can also be transmitted by the MAC using normal frame transmission methods. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 610 If connected to 1000BASE-T PHY using SGMII or RGMII there is nothing more to do. If connected to a backplane using a 1000BASE-KX PHY use firmware to periodically disable the SerDes transmit path. (Write to bit 1.160.0 for 1000BASE-KX.) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 611 10240 bytes. Note: The Jumbo-Frame Maximum Length register must be set to greater 1536 bytes (600 ) when control bit receive_1536_byte_frames in the Network Configuration register (bit 8) is set to “1”. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 612 Specific Address Bottom 2 Register (ETHERNETn_spec_add_bottom_2) Specific Address Top 2 Register (ETHERNETn_spec_add_top_2) Specific Address Bottom 3 Register (ETHERNETn_spec_add_bottom_3) Specific Address Top 3 Register (ETHERNETn_spec_add_top_3) Specific Address Bottom 4 Register (ETHERNETn_spec_add_bottom_4) Specific Address Top 4 Register (ETHERNETn_spec_add_top_4) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 613 Octets Transmitted Bottom Register (ETHERNETn_octets_txed_bottom) Octets Transmitted Top Register (ETHERNETn_octets_txed_top) Frames Transmitted Register (ETHERNETn_frames_txed_ok) Broadcast Frames Transmitted Register (ETHERNETn_broadcast_txed) Multicast Frames Transmitted Register (ETHERNETn_multicast_txed) Pause Frames Transmitted Register (ETHERNETn_pause_frames_txed) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 614 Frame Check Sequence Errors Register (ETHERNETn_fcs_errors) Length Field Frame Errors Register (ETHERNETn_rx_length_errors) Receive Symbol_Errors Register (ETHERNETn_rx_symbol_errors) Alignment Errors Register (ETHERNETn_alignment_errors) Receive Resource Errors Register (ETHERNETn_rx_resource_errors) Receive Over Runs Register (ETHERNETn_rx_overruns) IP Header Checksum Errors Register (ETHERNETn_rx_ip_ck_errors) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 615 RX Buffer Size Queue 1 Register (ETHERNETn_rxbuf_size_q1) RX Buffer Size Queue 2 Register (ETHERNETn_rxbuf_size_q2) RX Buffer Size Queue 3 Register (ETHERNETn_rxbuf_size_q3) CBS Control Register (ETHERNETn_cbs_control) CBS IdleSlope Queue A Register (ETHERNETn_cbs_idleslope_q_a) CBS IdleSlope Queue B Register (ETHERNETn_cbs_idleslope_q_b) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 616 Screening Type 2 Register 12 (ETHERNETn_screening_type_2_register_12) Screening Type 2 Register 13 (ETHERNETn_screening_type_2_register_13) Screening Type 2 Register 14 (ETHERNETn_screening_type_2_register_14) Screening Type 2 Register 15 (ETHERNETn_screening_type_2_register_15) Interrupt Enable Queue 1 Register (ETHERNETn_int_enable_q1) Interrupt Enable Queue 2 Register (ETHERNETn_int_enable_q2) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 617 Type2 Compare Word 1 8 Register (ETHERNETn_type2_compare_8_word_1) Type2 Compare Word 0 9 Register (ETHERNETn_type2_compare_9_word_0) Type2 Compare Word 1 9 Register (ETHERNETn_type2_compare_9_word_1) Type2 Compare Word 0 10 Register (ETHERNETn_type2_compare_10_word_0) Type2 Compare Word 1 10 Register (ETHERNETn_type2_compare_10_word_1) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 618 Type2 Compare Word 0 27 Register (ETHERNETn_type2_compare_27_word_0) Type2 Compare Word 1 27 Register (ETHERNETn_type2_compare_27_word_1) Type2 Compare Word 0 28 Register (ETHERNETn_type2_compare_28_word_0) Type2 Compare Word 1 28 Register (ETHERNETn_type2_compare_28_word_1) Type2 Compare Word 0 29 Register (ETHERNETn_type2_compare_29_word_0) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 619 Type2 Compare Word 1 29 Register (ETHERNETn_type2_compare_29_word_1) Type2 Compare Word 0 30 Register (ETHERNETn_type2_compare_30_word_0) Type2 Compare Word 1 30 Register (ETHERNETn_type2_compare_30_word_1) Type2 Compare Word 0 31 Register (ETHERNETn_type2_compare_31_word_0) Type2 Compare Word 1 31 Register (ETHERNETn_type2_compare_31_word_1) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 620 R0,W PROT_TYPE INITIAL_VALUE BIT_OFFSET stats_write_ inc_all_stat clear_all_st man_port_e enable_tran enable_rec BIT_NAME Reserved s_regs ats_regs smit eive ACCESS_TYPE R0,W R0,W1S R/W0 PROT_TYPE INITIAL_VALUE [bit31:26] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 621 [bit18] flush_rx_pkt_clk: Flush Next Packet From External RX DPRAM Description No effect Writing this bit to "1" will only have an effect if the DMA is currently not reading a packet stored in RX DPRAM to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 622 [bit11] tx_pause_frame_req: Transmit pause frame Description No effect Transmit pause frame. Cleared by hardware. [bit10] tx_halt_clk: Transmit halt Description No effect Halts transmission as soon as any ongoing frame transmission ends. Cleared by hardware. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 623 Frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register (ETHERNETn_receive_q_ptr) is unaffected. Enable the Ethernet MAC to receive data. [bit1:0] Reserved Always read write value. Always write "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 624 6_byte_fra ACCESS_TYPE R/W0 R/W0 PROT_TYPE INITIAL_VALUE BIT_OFFSET discard_non unicast_has multicast_h no_broadca copy_all_fra jumbo_fram BIT_NAME _vlan_fram full_duplex speed h_enable ash_enable ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31] Reserved Always read write value. Always write “0”. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 625 Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required. [bit22:21] data_bus_width: Data bus width Bits Description Reserved 64-bit AMBA AXI data bus width Reserved Reserved S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 626 [bit13] pause_enable: Pause enable Description Disable Transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 627 Only Unicast, Multicast, and Broadcast frames if enabled or frames which match Specific Address 1 to 4 are accepted. All valid frames will be accepted. [bit3] jumbo_frames: Jumbo frames Description Reject jumbo frames. Accept jumbo frames up to 10240 bytes. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 628 Setting not allowed. Full duplex mode. The transmit block ignores the state of state of collision and carrier sense and allows receive while transmitting. [bit0] speed: Speed Description Setting not allowed. 100Mbps operation. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 629 Low-power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit is changed. [bit6] pfc_negotiate_clk: PFC negotiated S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 630 When this bit is set it means PHY management logic is idle (i.e. has completed). [bit1] mdio_in: MDIO_IN status This bit returns the status of the mdio_in pin. [bit0] Reserved Always read "0". Writing has no effect S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 631 ACCESS_TYPE R0,W0 R0,WX PROT_TYPE INITIAL_VALUE 0x04 [bit31] Reserved Always read "0". Writing has no effect. [bit30] dma_addr_bus_width: DMA address bus width Description 32-bit DMA address bus width. Setting not allowed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 632 The value defined by these bits determines the size of the buffer to use in system memory when writing received data. The value is defined in multiples of 64 bytes. Bits Description 0x00 Setting not allowed 0x01 64 Byte 0x02 128 Byte (2 * 64 Byte) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 633 Do not use top two address bits (1 Kbytes) Do not use top address bit (2 Kbytes) Use full configure addressable space (4 Kbytes) [bit7:6] Reserved Always read "0". Always write “0”. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 634 00001 Always use SINGLE data transfers The core will optimally decide the best AXI burst length with up to 16 data transfers if possible, whilst 00000 respecting the 4KB boundary restriction. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 635 Set to "1" when the Ethernet MAC DMA sees BRESP not OK. Cleared by writing a "1" to this bit. [bit7] late_collision_occurred: Late collision occurred Only set.if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 636 In gigabit mode, this status is not set for a late collision.. [bit0] used_bit_read: Used bit read Used bit read Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 637 BIT_NAME dma_rx_q_ptr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[7:2] Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 [bit31:2] dma_rx_q_ptr: Receive buffer queue base address Start address of receive buffer queue in system memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 638 CHAPTER 21:Ethernet MAC [bit1:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 639 OTHER BIT_OFFSET BIT_NAME dma_tx_q_ptr[31:24] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[23:16] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[7:2] Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 640 CHAPTER 21:Ethernet MAC [bit31:2] dma_tx_q_ptr: Transmit buffer queue base address Start address of transmit buffer queue in system memory. [bit1:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 641 This bit is set if the RX Packet Buffer Memory overflows. For DMA operation the buffer will be recovered if an over run occurs. This bit is cleared by writing "1" to it. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 642 This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. This bit is cleared by writing "1" to it. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 643 R,W1C R,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET pause_fram pause_fram e_with_non pause_time resp_not_o receive_ove BIT_NAME Reserved e_transmitt _zero_paus Reserved _elapsed rrun e_quantum _received ACCESS_TYPE R,WX R,W1C R,W1C R,W1C R,W1C R,W1C R,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 644 Interrupt de-asserted. Interrupt asserted. Indicates a PTP Pdelay_Req frame has been transmitted. [bit23] ptp_pdelay_resp_frame_received: PTP Pdelay_Resp frame received Description Interrupt de-asserted. Interrupt asserted. Indicates a PTP Pdelay_Resp frame has been received. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 645 [bit12] pause_frame_with_non_zero_pause_quantum_received: Pause frame with non-zero pause quantum received Description Interrupt de-asserted. Interrupt asserted. Indicates a valid pause has been received that has a non-zero pause quantum field. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 646 Interrupt asserted. Set when a transmit buffer descriptor is read with its used bit set. [bit2] rx_used_bit_read: RX used bit read Description Interrupt de-asserted. Interrupt asserted. Set when a receive buffer descriptor is read with its used bit set. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 647 Interrupt asserted. Set when a frame has been stored in memory. [bit0] management_frame_sent: Management frame sent Description Interrupt de-asserted. Interrupt asserted. Set when the PHY Maintenance register has completed its operation. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 648 INITIAL_VALUE BIT_OFFSET enable_tran enable_retr enable_tx_u enable_rx_ enable_rec enable_ma enable_am BIT_NAME smit_compl y_limit_exc Reserved sed_bit_rea used_bit_re eive_compl nagement_f ba_error eeded rame_sent ACCESS_TYPE R0,W1 R0,W1 R0,W1 R0,WX R0,W1 R0,W1 R0,W1 R0,W1 PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 649 Always read "0". Writing "1" enables PTP Delay_Req frame received interrupt. [bit17:16] Reserved Always read "0". Writing has no effect. [bit15] enable_external_interrupt: Enable External interrupt Always read "0". Writing "1" enables External interrupt S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 650 Always read "0". Writing "1" enables RX used bit read interrupt. [bit1] enable_receive_complete: Enable Receive complete Always read "0". Writing "1" enables Receive complete interrupt. [bit0] enable_management_frame_sent: Enable Management frame sent Always read "0". Writing "1" enables Management frame sent interrupt. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 651 INITIAL_VALUE BIT_OFFSET disable_tran disable_retr disable_tx_ disable_rx_ disable_rec disable_ma disable_am BIT_NAME smit_compl y_limit_exc Reserved used_bit_re used_bit_re eive_compl nagement_f ba_error eeded rame_sent ACCESS_TYPE R,W1 R,W1 R,W1 R0,WX R,W1 R,W1 R,W1 R,W1 PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 652 [bit18] disable_ptp_delay_req_frame_received: Disable PTP Delay_Req frame received Writing "1" disables PTP Delay_Req frame received interrupt. [bit17:16] Reserved Always read "0". Writing has no effect. [bit15] disable_external_interrupt: Disable External interrupt Writing "1" disables External interrupt S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 653 Writing "1" disables RX used bit read interrupt. [bit1] disable_receive_complete: Disable Receive complete Writing "1" disables Receive complete interrupt. [bit0] disable_management_frame_sent: Disable Management frame sent Writing "1" disables Management frame sent interrupt. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 654 _zero_paus BIT_NAME errupt_mas _zero_interr k_interrupt_ rrun_interru _interrupt_ not_used ed_interrupt e_quantum upt_mask mask pt_mask mask _mask _interrupt_ mask ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R1, WX PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 655 A read of this register returns the value of the PTP Pdelay_Resp frame transmitted mask. A write to this register directly affects the state of the corresponding bit in the Interrupt Status register, causing an interrupt to be generated if a "1" is written. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 656 Interrupt Status register, causing an interrupt to be generated if a "1" is written. Description Interrupt is enabled. Interrupt is disabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 657 A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. Description Interrupt is enabled. Interrupt is disabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 658 A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. Description Interrupt is enabled. Interrupt is disabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 659 A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. Description Interrupt is enabled. Interrupt is disabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 660 A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. Description Interrupt is enabled. Interrupt is disabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 661 ACCESS_TYPE R/w0 PROT_TYPE INITIAL_VALUE BIT_OFFSET phy_addres BIT_NAME register_address[4:0] write10[1:0] s[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME phy_write_read_data[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME phy_write_read_data[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 662 [bit15:0] phy_write_read_data: PHY write/read data For a write operation the value in this register is written to the PHY as data. For a read operation this register contains the data read from the PHY. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 663 [bit31:16] Reserved Always read "0". Writing has no effect. [bit15:0] quantum: Received pause quantum Stores the current value of the received pause quantum register which is decremented every 512 bit times. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 664 [bit31:16] quantum_p1: Transmit pause quantum - Priority 1 Write pause quantum value for pause frame transmission of priority 1. [bit15:0] quantum: Transmit pause quantum Write pause quantum value for pause frame transmission. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 665 [bit31] dma_tx_cutthru: TX Partial Store and Forward Description Enable TX Full Store and Forward operation mode. Enable TX Partial Store and Forward operation mode. [bit30:11] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 666 CHAPTER 21:Ethernet MAC [bit10:0] dma_tx_cutthru_threshold: TX partial store and forward threshold Watermark value. This value must be >= 0x14 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 667 [bit31] dma_rx_cutthru: RX Partial Store and Forward Description Enable RX Full Store and Forward operation mode. Enable RX Partial Store and Forward operation mode. [bit30:9] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 668 CHAPTER 21:Ethernet MAC [bit8:0] dma_rx_cutthru_threshold: RX partial store and forward threshold Watermark value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 669 ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:16] Reserved Always read "0". Writing has no effect. [bit15:0] jumbo_max_length: Jumbo-Frame maximum length Defines the maximum Jumbo-Frame size in Bytes. Reset value corresponds to 10240 Bytes. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 670 Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel. Bits Description 0x00 The maximum number of outstanding write requests is 1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 671 Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel. Bits Description 0x00 The maximum number of outstanding read requests is 1. 0x0F The maximum number of outstanding read requests is 16. 0x10 – Setting reserved. 0xFF S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 672 PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:0] address: Hash address [31:0] The lower 32 bits of the hash address register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 673 PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address[47:40] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address[39:32] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:0] address: Hash address [63:32] The upper 32 bits of the hash address register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 674 Least significant 32 bits of the destination address, which is bits [31:0]. Bit 0 indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 675 When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 676 When set to "1", the filter is a source address filter. [bit15:0] address: Specific address i [47:32] The most significant bits of the destination/source address that is to be compared, that is bits [47:32]. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 677 Enable copying of Type ID match, matched frames. [bit30:16] Reserved Always read "0". Writing has no effect. [bit15:0] match: Type ID match Type ID match. For use in comparisons with received frames Type ID/length field. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 678 If the resulting number is greater than 96 and bit 28 is set in the Network Configuration register then the resulting number is used for the transmit Interpacket Gap. 1 is added to bits [15:8] to prevent a divide by zero. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 679 VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 680 Transmit Pause Quantum register. For each entry equal to "1" in the Transmit PFC Pause register [15:8], the pause quantum associated with that entry will be "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 681 If bit 17 of the Network Control register is written with a "1" then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 682 INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address_mask[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:0] address_mask: Specific Address Mask [31:0] Setting a bit to "1" masks the corresponding bit in the Specific Address Bottom i register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 683 [bit31:16] Reserved Always read "0". Writing has no effect. [bit15:0] address_mask: Specific Address Mask [47:32] Setting a bit to "1" masks the corresponding bit in the Specific Address Top i register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 684 INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:0] address: Unicast IP destination address Used for detection of PTP frames on receive path. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 685 INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME address[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:0] address: Unicast IP destination address Used for detection of PTP frames on transmit path. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 686 DMA is currently processing a receive packet. It will only affect the next full packet to be written to system memory. [bit27:4] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 687 Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to system memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 688 Always read "0". Writing has no effect. [bit21:0] comparison_value: IEEE 1588 Timer comparison value nanoseconds [21:0] The register value is compared to bits [45:24] of the IEEE 1588 Timer count value (upper 22 bits of nanosecond value). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 689 BIT_OFFSET BIT_NAME comparison_value[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:0] comparison_value: IEEE 1588 Timer comparison value seconds [31:0] The register value is compared to bits [31:0] of the IEEE 1588 Timer count value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 690 Always read "0". Writing has no effect. [bit15:0] comparison_value: IEEE 1588 Timer comparison value seconds [47:32] The register value is compared to bits [47:32] of the IEEE 1588 Timer count value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 691 PTP transmit primary event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP sync or Delay_Req frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 692 PTP receive primary event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Sync or Delay_Req frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 693 PTP transmit peer event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Pdelay_Req or Pdelay_Resp frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 694 PTP transmit peer event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Pdelay_Req or Pdelay_Resp frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 695 ACCESS_TYPE R,WX PROT_TYPE INITIAL_VALUE (product specification) [bit31:16] module_identification_number[15:0]: Module identification number Module identification number for the Ethernet MAC. [bit15:0] module_revision[15:0]: Module revision number Module revision number for the Ethernet MAC. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 696 The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers (ETHERNETn_octets_txed_top and ETHERNETn_octets_txed_bottom). This count does not include octets from automatically generated pause frames. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 697 The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers (ETHERNETn_octets_txed_top and ETHERNETn_octets_txed_bottom). This count does not include octets from automatically generated pause frames. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 698 PROT_TYPE INITIAL_VALUE 0x00 [bit31:0] count: Frames transmitted without error A 32-bit register counting the number of frames successfully transmitted, i.e. no under run and not too many retries. Excludes pause frames. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 699 [bit31:0] count: Broadcast frames transmitted without error A 32-bit register counting the number of broadcast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 700 [bit31:0] count: Multicast frames transmitted without error A 32-bit register counting the number of multicast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 701 A 16-bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through the External FIFO Interface are counted in the frames transmitted counter. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 702 [bit31:0] count: 64 byte frames transmitted without error A 32-bit register counting the number of 64 byte frames successfully transmitted without error, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 703 [bit31:0] count: 65 to 127 byte frames transmitted without error A 32-bit register counting the number of 65 to 127 byte frames successfully transmitted without error, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 704 [bit31:0] count: 128 to 255 byte frames transmitted without error A 32-bit register counting the number of 128 to 255 byte frames successfully transmitted without error, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 705 [bit31:0] count: 256 to 511 byte frames transmitted without error A 32-bit register counting the number of 256 to 511 byte frames successfully transmitted without error, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 706 [bit31:0] count: 512 to 1023 byte frames transmitted without error A 32-bit register counting the number of 512 to 1023 byte frames successfully transmitted without error, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 707 [bit31:0] count: 1024 to 1518 byte frames transmitted without error A 32-bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 708 [bit31:0] count: Greater than 1518 Byte frames transmitted without error A 32-bit register counting the number of 1518 or above byte frames successfully transmitted without error, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 709 [bit31:0] count: Greater than 1518 Byte frames transmitted without error A 32-bit register counting the number of 1518 or above byte frames successfully transmitted without error, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 710 [bit9:0] count: Transmit under runs A 10-bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 711 Always read "0". Writing has no effect. [bit17:0] count: Single collision frames An 18-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no under run. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 712 [bit17:0] count: Multiple collision frames An 18-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 713 [bit31:10] Reserved Always read "0". Writing has no effect. [bit9:0] count: Excessive collision frames A 10-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 714 A 10-bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 MBit/s mode, late collisions are counted twice i.e. both as a collision and a late collision. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 715 An 18-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit under run. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 716 (no under run). Only incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behaviour of the other statistics registers is unaffected by the detection of a carrier sense error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 717 The number of octets received in valid frames of any type. This counter is 48-bits, and is read through two registers (ETHERNETn_octets_rxed_top and ETHERNETn_octets_rxed_bottom). This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 718 The number of octets received in valid frames of any type. This counter is 48-bits, and is read through two registers (ETHERNETn_octets_rxed_top and ETHERNETn_octets_rxed_bottom). This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 719 [bit31:0] count: Frames received without error A 32-bit register counting the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 720 [bit31:0] count: Broadcast frames received without error A 32-bit register counting the number of broadcast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 721 [bit31:0] count: Multicast frames received without error A 32-bit register counting the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 722 ACCESS_TYPE R,WX PROT_TYPE INITIAL_VALUE 0x00 [bit31:16] Reserved Always read "0". Writing has no effect. [bit15:0] count: Received pause frames A 16-bit register counting the number of pause frames received without error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 723 A 32-bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 724 A 32-bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 725 A 32-bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 726 A 32-bit register counting the number of 256 to 511 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 727 A 32-bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 728 A 32-bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 729 Maximum frame size is determined by the Network Configuration register bit 8 (1536 maximum frame size) or bit 3 (jumbo frame size). Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 730 [bit9:0] count: Undersized frames received A 10-bit register counting the number of frames received less than 64 bytes in length (10/100 MBit/s mode) that do not have either a CRC error or an alignment error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 731 Network Configuration register, 10240 bytes if bit 3 is set in the Network Configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 732 Network Configuration register, 10240 bytes if bit 3 is set in the Network Configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 733 This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being enabled in bit 26 of the Network Configuration register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 734 (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600 (1536)), the frame is not of excessive length and checking is enabled through bit 16 of the Network Configuration register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 735 8 is set in the Network Configuration register, 10240 bytes if bit 3 is set in the Network Configuration register). If the frame is larger it will be recorded as a jabber error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 736 (1536 if bit 8 set in Network Configuration register, 10240 bytes if bit 3 is set in the Network Configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 737 (correct address matched frame and adequate slot time) but could not be copied to memory because no receive buffer was available. This occurs when the Ethernet MAC reads a buffer descriptor with its ownership (or used) bit set. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 738 Always read "0". Writing has no effect. [bit9:0] count: Receive over runs A 10-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive over run. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 739 64 and 1518 bytes (1536 bytes if bit 8 is set in the Network Configuration register or 10240 bytes if bit 3 is in the Network Configuration register) and do not have a CRC error, an alignment error, nor a symbol error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 740 64 and 1518 bytes (1536 bytes if bit 8 is set in the Network Configuration register or 10240 bytes if bit 3 is in the Network Configuration register) and do not have a CRC error, an alignment error, nor a symbol error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 741 64 and 1518 bytes (1536 bytes if bit 8 is set in the Network Configuration register or 10240 bytes if bit 3 is in the Network Configuration register) and do not have a CRC error, an alignment error, nor a symbol error. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 742 When partial store and forward mode is enabled and an AMBA AXI error is encountered while writing the packet data to system memory. When bit 18 of the Network Control register (software S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 743 CHAPTER 21:Ethernet MAC action to flush a packet from the head of the PBUF queue) is pulsed and the Ethernet MAC DMA is not currently busy. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 744 Lower significant bits of IEEE 1588 Timer Increment [15:0] register giving a 24-bit timer_increment counter. These bits are the sub-ns value which the IEEE 1588 Timer will increment each clock cycle. Bit n = 2(n-16) nsec giving a resolution of approximately 15.2E-15 sec. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 745 (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). Note: The value of this register is used only when the lower 32-bit register is written to. This is to ensure a single update of the 48-bit seconds value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 746 The 48-bit counter increments by one when the IEEE 1588 Timer Nanoseconds counter counts to one second. It may also be incremented or decremented when the IEEE 1588 Timer Adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 747 IEEE 1588 Timer Adjust register causes a decrement the seconds register will be decremented if necessary and the nanoseconds register will roll back to 9999999xx(dec)). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 748 [bit29:0] increment_value: IEEE 1588 Timer increment value The number of nanoseconds to increment or decrement the IEEE 1588 Timer Nanoseconds register. If necessary the IEEE 1588 Timer Seconds register will be incremented or decremented. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 749 The number of increments after which the alternative increment is used. [bit15:8] alt_count: Alternative count of nanoseconds Alternative count of nanoseconds by which the IEEE 1588 Timer Nanoseconds register will be incremented each clock cycle. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 750 CHAPTER 21:Ethernet MAC [bit7:0] count: Count of nanoseconds A count of nanoseconds by which the IEEE 1588 Timer Nanoseconds register will be incremented each clock cycle. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 751 SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Sync or Delay_Req frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 752 SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Sync or Delay_Req frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 753 SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Sync or Delay_Req frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 754 SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Sync or Delay_Req frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 755 SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Pdelay_Req or Pdelay_Resp frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 756 SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Pdelay_Req or Pdelay_Resp frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 757 PTP receive peer event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Pdelay_Req or Pdelay_Resp frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 758 SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the Ethernet MAC recognizes the frame as a PTP Pdelay_Req or Pdelay_Resp frame. An interrupt is issued when the register is updated. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 759 Written with the pause quantum value for pause frame transmission of priority 3. [bit15:0] quantum_p2: Transmit pause quantum prio 2 Written with the pause quantum value for pause frame transmission of priority 2. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 760 Written with the pause quantum value for pause frame transmission of priority 5. [bit15:0] quantum_p4: Transmit pause quantum prio 4 Written with the pause quantum value for pause frame transmission of priority 4. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 761 Written with the pause quantum value for pause frame transmission of priority 7. [bit15:0] quantum_p6: Transmit pause quantum prio 6 Written with the pause quantum value for pause frame transmission of priority 6. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 762 Always read "0". Writing has no effect. [bit15:0] count: Count of RX LPI transitions A count of the number of times there is a transition from receiving normal idle to receiving low power idle. Cleared on read. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 763 Always read "0". Writing has no effect. [bit23:0] lpi_time: Time in LPI This register increments once every 16 clock cycles when the LPI Indication bit 7 is set in the Network Status register. Cleared on read. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 764 Always read "0". Writing has no effect. [bit15:0] count: Count of TX LPI transitions A count of the number of times the Enable LPI transmission bit 19 goes from low to high in the Network Control register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 765 Always read "0". Writing has no effect. [bit23:0] lpi_time: Time in LPI This register increments once every 16 clock cycles when the Enable LPI transmission bit 19 is set in the Network Control register. Cleared on read. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 766 INITIAL_VALUE 0x00 [bit31:30] Reserved Always read "0". Writing has no effect. [bit29:24] num_spec_add_filters: Takes the value of `num_spec_add_filters. Writing has no effect. [bit23:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 767 [bit31:20] Reserved Always read "0". Writing has no effect. [bit19:16] tx_base2_fifo_size: Takes the value of `gem_tx_base2_fifo_size. Writing has no effect. [bit15:0] tx_fifo_size: Takes the value of `gem_tx_fifo_size. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 768 Takes the value of `gem_axi_prot_value. Writing has no effect. [bit28] tsu_clk: Takes the value of `gem_tsu_clk. Writing has no effect. [bit27:20] rx_buffer_length_def: Takes the value of `gem_rx_buffer_length_def. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 769 Takes the value of `gem_tsu. Writing has no effect. [bit7:4] tx_fifo_cnt_width: Takes the value of `gem_tx_fifo_cnt_width. Writing has no effect. [bit3:0] rx_fifo_cnt_width: Takes the value of `gem_rx_fifo_cnt_width. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 770 R,WX R,WX R,WX R,WX R,WX R,WX R0,WX PROT_TYPE INITIAL_VALUE (product specification) [bit31:26] Reserved: Always read “0”. Writing has no effect. [bit25] pbuf_cutthru: Takes the value of `gem_pbuf_cutthru. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 771 Takes the value of `gem_ dma_priority_queue7. Writing has no effect. [bit6] dma_priority_queue6: Takes the value of `gem_ dma_priority_queue6. Writing has no effect. [bit5] dma_priority_queue5: Takes the value of `gem_ dma_priority_queue5. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 772 Takes the value of `gem_ dma_priority_queue2. Writing has no effect. [bit1] dma_priority_queue1: Takes the value of `gem_ dma_priority_queue1. Writing has no effect. [bit0] Reserved: Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 773 Takes the value of `gem_ tx_pbuf_num_segments_q7. Writing has no effect. [bit27:24] tx_pbuf_num_segments_q6: Takes the value of `gem_ tx_pbuf_num_segments_q6. Writing has no effect. [bit23:20] tx_pbuf_num_segments_q5: Takes the value of `gem_ tx_pbuf_num_segments_q5. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 774 Takes the value of `gem_ tx_pbuf_num_segments_q2. Writing has no effect. [bit7:4] tx_pbuf_num_segments_q1: Takes the value of `gem_ tx_pbuf_num_segments_q1. Writing has no effect. [bit3:0] tx_pbuf_num_segments_q0: Takes the value of `gem _tx_pbuf_num_segments_q0. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 775 Takes the value of `gem_ num_type1_screeners. Writing has no effect. [bit23:16] num_type2_screeners: Takes the value of `gem_ num_type2_screeners. Writing has no effect. [bit15:8] num_scr2_ethtype_regs: Takes the value of `gem_ num_scr2_ethtype_regs. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 776 CHAPTER 21:Ethernet MAC [bit7:0] num_scr2_compare_regs: Takes the value of `gem_ num_scr2_compare_regs. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 777 Takes the value of `gem_ tx_pbuf_num_segments_q15. Writing has no effect. [bit27:24] tx_pbuf_num_segments_q14: Takes the value of `gem_ tx_pbuf_num_segments_q14. Writing has no effect. [bit23:20] tx_pbuf_num_segments_q13: Takes the value of `gem_ tx_pbuf_num_segments_q13. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 778 Takes the value of `gem_ tx_pbuf_num_segments_q10. Writing has no effect. [bit7:4] tx_pbuf_num_segments_q9: Takes the value of `gem_ tx_pbuf_num_segments_q9. Writing has no effect. [bit3:0] tx_pbuf_num_segments_q8: Takes the value of `gem _tx_pbuf_num_segments_q8. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 779 Takes the value of `gem_ emac_bus_width. Writing has no effect. [bit27:24] tx_pbuf_data: Takes the value of `gem_ tx_pbuf_data. Writing has no effect. [bit23:20] rx_pbuf_data: Takes the value of `gem_ rx_pbuf_data. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 780 Takes the value of `gem_ axi_rx_desc_rd_buff_bits. Writing has no effect. [bit7:4] axi_tx_desc_wr_buff_bits: Takes the value of `gem_ axi_tx_desc_wr_buff_bits. Writing has no effect. [bit3:0] axi_rx_desc_wr_buff_bits: Takes the value of `gem _axi_rx_desc_wr_buff_bits. Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 781 R0,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET retry_limit_e transmit_co xceeded_or rx_used_bit receive_co BIT_NAME amba_error Reserved Reserved mplete _late_collisi _read mplete ACCESS_TYPE R0,WX R0,WX PROT_TYPE INITIAL_VALUE [bit31:12] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 782 Interrupt asserted. Set when a receive buffer descriptor is read with its used bit set. [bit1] receive_complete: Receive complete Description Interrupt de-asserted. Interrupt asserted. Set when a frame has been stored in memory. [bit0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 783 OTHER BIT_OFFSET BIT_NAME dma_tx_q_ptr[31:24] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[23:16] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[7:2] Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 784 CHAPTER 21:Ethernet MAC [bit31:2] dma_tx_q_ptr: Transmit buffer queue base address Start address of transmit buffer queue. [bit1:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 785 OTHER BIT_OFFSET BIT_NAME dma_tx_q_ptr[31:24] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[23:16] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[7:2] Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 786 CHAPTER 21:Ethernet MAC [bit31:2] dma_tx_q_ptr: Transmit buffer queue base address Start address of transmit buffer queue. [bit1:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 787 OTHER BIT_OFFSET BIT_NAME dma_tx_q_ptr[31:24] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[23:16] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_tx_q_ptr[7:2] Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 788 CHAPTER 21:Ethernet MAC [bit31:2] dma_tx_q_ptr: Transmit buffer queue base address Start address of transmit buffer queue. [bit1:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 789 OTHER BIT_OFFSET BIT_NAME dma_rx_q_ptr[31:24] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[23:16] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[7:2] Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 790 CHAPTER 21:Ethernet MAC [bit31:2] dma_rx_q_ptr: Receive buffer queue base address Start address of receive buffer queue. [bit1:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 791 OTHER BIT_OFFSET BIT_NAME dma_rx_q_ptr[31:24] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[23:16] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[7:2] Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 792 CHAPTER 21:Ethernet MAC [bit31:2] dma_rx_q_ptr: Receive buffer queue base address Start address of receive buffer queue. [bit1:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 793 OTHER BIT_OFFSET BIT_NAME dma_rx_q_ptr[31:24] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[23:16] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME dma_rx_q_ptr[7:2] Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 794 CHAPTER 21:Ethernet MAC [bit31:2] dma_rx_q_ptr: Receive buffer queue base address Start address of receive buffer queue. [bit1:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 795 The value defined by these bits determines the size of the buffer to use in system memory when writing received data. The value is defined in multiples of 64 bytes. Bits Description 0x00 Setting not allowed 0x01 64 Byte S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 796 1536 Byte (24 * 64 Byte) one maximum length frame/buffer 0xA0 10240 Byte (160 * 64 Byte) one jumbo frame/buffer 0xF0 15360 Byte (240 * 64 Byte) 0xFF 16320 Byte (255 * 64 Byte) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 797 INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME Reserved ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET cbs_enable cbs_enable BIT_NAME Reserved _queue_b _queue_a ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 [bit31:2] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 798 CBS on Queue B disabled. CBS on Queue B enabled. [bit0] cbs_enable_queue_a: Enable Credit Based Shaping on Highest Priority Queue Description CBS on Queue A disabled. CBS on Queue A enabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 799 [bit31:0] idleslope_a: IdleSlope Value for Queue A Contains the idleSlope value for queue A in bytes per second. Queue A is the queue with the highest priority, i.e. queue number 3. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 800 [bit31:0] idleslope_b: IdleSlope Value for Queue B Contains the idleSlope value for queue B in bytes per second. Queue B is the queue with the second highest priority, i.e. queue number 2. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 801 INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME msb_buff_q_base_addr[23:16] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME msb_buff_q_base_addr[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME msb_buff_q_base_addr[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:0] msb_buff_q_base_addr: Upper 32-bit Buffer Queue Base Address S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 802 [bit5:4] tx_bd_ts_mode: TX Descriptor Timestamp Insertion mode Bits Description TS insertion disable TS inserted for PTP Event Frames only TS inserted for All PTP Frames only TS insertion for All Frames S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 803 CHAPTER 21:Ethernet MAC [bit3:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 804 [bit5:4] rx_bd_ts_mode: RX Descriptor Timestamp Insertion mode Bits Description TS insertion disabled TS inserted for PTP Event Frames only TS inserted for All PTP Frames only TS insertion for All Frames S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 805 CHAPTER 21:Ethernet MAC [bit3:0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 806 INITIAL_VALUE BIT_OFFSET BIT_NAME udp_port_match[11:4] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME udp_port_match[3:0] dstc_match[7:4] ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME dstc_match[3:0] queue_number[3:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:30] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 807 DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers is matched against this value. [bit3:0] queue_number: Queue number Queue Number (0 - 15). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 808 R0,WX PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET compare_a BIT_NAME compare_b[4:0] compare_a[4:3] _enable ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME compare_a[2:0] ethertype_enable index[2:0] vlan_enable ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME Reserved vlan_priority[2:0] queue_number[3:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 809 [bit8] vlan_enable: VLAN enable Description Disable Enable [bit7] Reserved Always read write value. Writing always “0”. [bit6:4] vlan_priority: VLAN Priority VLAN priority. [bit3:0] queue_number: Queue number Queue Number (0 - 15). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 810 Reserved used_bit_re Reserved ete_interrup _due_to_a ete_interrup ate_collisio ad_interrupt mba_error_i n_interrupt nterrupt ACCESS_TYPE R0,W1 R0,W1 R0,W1 R0,WX R0,W1 R0,W1 R0,WX PROT_TYPE INITIAL_VALUE [bit31:12] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 811 [bit2] enable_rx_used_bit_read_interrupt: Enable RX used bit read interrupt Writing "1" enables RX used bit read interrupt. [bit1] enable_receive_complete_interrupt: Enable Receive complete interrupt Writing "1" enables Receive complete interrupt. [bit0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 812 _corruption eive_compl BIT_NAME eeded_or_l Reserved used_bit_re Reserved ete_interrup _due_to_a ete_interrup ate_collisio ad_interrupt mba_error_i n_interrupt nterrupt ACCESS_TYPE R0,W1 R0,W1 R0,W1 R0,WX R0,W1 R0,W1 R0,WX PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 813 [bit2] disable_rx_used_bit_read_interrupt: Disable RX used bit read interrupt Writing "1" disables RX used bit read interrupt. [bit1] disable_receive_complete_interrupt: Disable Receive complete interrupt Writing "1" disables Receive complete interrupt. [bit0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 814 PROT_TYPE INITIAL_VALUE BIT_OFFSET transmit_fra retry_limit_e me_corrupti transmit_co rx_used_bit receive_co xceeded_or on_due_to_ _late_collisi BIT_NAME mplete_inte Reserved _read_interr mplete_inte Reserved amba_error on_interrupt rrupt_mask _interrupt_ upt_mask rrupt_mask _mask mask ACCESS_TYPE R0,WX R0,WX PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 815 A write to this register directly affects the state of the corresponding bit in the Interrupt Status Queue i register, causing an interrupt to be generated if a "1" is written. Description Interrupt disabled Interrupt enabled [bit4:3] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 816 A write to this register directly affects the state of the corresponding bit in the Interrupt Status Queue i register, causing an interrupt to be generated if a "1" is written. Description Interrupt disabled Interrupt enabled [bit0] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 817 BIT_OFFSET BIT_NAME compare_value[15:8] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET BIT_NAME compare_value[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:16] Reserved Always read "0". Writing has no effect. [bit15:0] compare_value: Compare value EtherType 2 compare value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 818 The byte stored in bits [31:24] is compared against the 2nd byte of the 2 bytes extracted from the frame. [bit15:0] mask_value: Mask value 2 byte Mask Value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 819 PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET compare_of BIT_NAME Reserved fset[1] ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET compare_of BIT_NAME offset_value[6:0] fset[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE 0x00 [bit31:9] Reserved Always read "0". Writing has no effect. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 820 Offset from beginning of frame. Offset from byte after EtherType. Offset from byte following end of IP header. Offset from byte following end of TCP/UDP header. [bit6:0] offset_value[6:0]: Offset value Offset value in bytes. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 821 Doing the two step time stamping if VLAN tagged IEEE Std version 1 frames will be used. 5.7. PTP/gPTP - The ptp_sync_frame_transmitted interrupt The interrupt bit21 (ptp_sync_frame_transmitted) won't be generated for the transmission of the multicast SYNC frames satisfying all of the following conditions: S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 822 0x0, the TSU timer comparison won't be executed. And, as a result, the interrupt request won't be generated. The condition will be avoidable in the normal use cases. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 823 Media Local Bus Interface (MediaLB) CHAPTER 22: This chapter explains the functions and operations of the MediaLB. Overview Configuration and Block Diagram Operation of the MediaLB Registers CODE: MEDIA_LB-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 824 Configurable protection for read and write accesses to registers in MediaLB  Programmable for 256Fs, 512Fs and 1024Fs transfer rates of operation at either 44.0kHz, 48.0kHz, or 48.1kHz.  3-pin MediaLB Mode S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 825 Circular buffering Performs data transfers repeatedly for the data storage area indicated by the current buffer. No interrupt occurs at the completion of a transfer. Indicates a logical channel number (n=0..15) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 826 MediaLB DIM (OS62400) MediaLB Channel Arbiter MediaLB MediaLB Local Channel Clocks, MediaLB Channel Configuration Buffer (SRAM) Power and Buffer Logic Logic Reset MediaLB Link Logic MediaLB Core I/O Port MLBn_CLK MLBn_DAT MLBn_SIG S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 827 Channel n Current Buffer Configuration Register (MLBn_CCBCRn) for MediaLB is output as the address of the AHB bus. In the DMA mode, two types of buffering is supported: Ping-Pong and circular buffering. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 828 *Data interrupts (mlb_dint[30:0]) provided by SMSC IP OS62400 are not supported. Reason is that data interrupts are provided for customers who want to attach an external DMA Controller directly to OS62400 and load/unload the local channel buffers in IO Mode. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 829 All channels (both transmission/reception) MASK[2] STS[10] MLBn_CECRn: Writing "1" to STS[11] Previous buffer start All channels (both transmission/reception) MASK[3] STS[11] *Cannot be masked. Setting the cause factor flag to "1" triggers an interrupt. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 830 During the loop back mode, the Next Buffer Ready bits for Channels 0 and 1 remains cleared (MLBn_CSCR0:RDY=MLBn_CSCR1:RDY="0"). During the loop back mode, little-endian mode must be disabled (MLBn_DCCR=MLE="0"). During the loop back mode, ishochronous packet lengths must be quadlet multiples. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 831 This chapter lists the various references to other documents, used in this specification.  OS62400 MediaLB Device Interface Macro Advanced Product Data Sheet (DS62400AP5) by SMSC, issued on October 2006.  MediaLB Specification by SMSC (TB0400AN3V0, rev 3.0 issued on February 2006) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 832 MediaLBn Channel Current Buffer Configuration Register (MLBn_CCBCR0 - MLBn_CCBCR15)  MediaLBn Channel Next Buffer Configuration Register (MLBn_CNBCR0 - MLBn_CNBCR15)  MediaLBn Local Channel Buffer Configuration Register (MLBn_LCBCR0 - MLBn_LCBCR15)  MediaLBn Module Identification Register (MLBn_MID) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 833 00000000 00000000 00000000 00000000 MLBn_CNBCR0 0x0000004C 00000000 00000000 00000000 00000000 MLBn_CECR1 0x00000050 00000000 00000000 00000000 00000000 MLBn_CSCR1 0x00000054 10000000 00000000 00000000 00000000 MLBn_CCBCR1 0x00000058 00000000 00000000 00000000 00000000 MLBn_CNBCR1 0x0000005C 00000000 00000000 00000000 00000000 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 834 10000000 00000000 00000000 00000000 MLBn_CCBCR6 0x000000A8 00000000 00000000 00000000 00000000 MLBn_CNBCR6 0x000000AC 00000000 00000000 00000000 00000000 MLBn_CECR7 0x000000B0 00000000 00000000 00000000 00000000 MLBn_CSCR7 0x000000B4 10000000 00000000 00000000 00000000 MLBn_CCBCR7 0x000000B8 00000000 00000000 00000000 00000000 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 835 00000000 00000000 00000000 00000000 MLBn_CSCR12 0x00000104 10000000 00000000 00000000 00000000 MLBn_CCBCR12 0x00000108 00000000 00000000 00000000 00000000 MLBn_CNBCR12 0x0000010C 00000000 00000000 00000000 00000000 MLBn_CECR13 0x00000110 00000000 00000000 00000000 00000000 MLBn_CSCR13 0x00000114 10000000 00000000 00000000 00000000 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 836 00000000 01000000 00000000 00000000 MLBn_LCBCR7 0x0000029C 00000000 01000000 00000000 00000000 MLBn_LCBCR8 0x000002A0 00000000 01000000 00000000 00000000 MLBn_LCBCR9 0x000002A4 00000000 01000000 00000000 00000000 MLBn_LCBCR10 0x000002A8 00000000 01000000 00000000 00000000 MLBn_LCBCR11 0x000002AC 00000000 01000000 00000000 00000000 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 837 0x000002B4 00000000 01000000 00000000 00000000 MLBn_LCBCR14 0x000002B8 00000000 01000000 00000000 00000000 MLBn_LCBCR15 0x000002BC 00000000 01000000 00000000 00000000 0x000002C0 - reserved 0x000002F8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX MLBn_MID 0x000002FC 00000000 00000000 00000000 00000000 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 838 ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME MDA[7] MDA[6] MDA[5] MDA[4] MDA[3] MDA[2] MDA[1] MDA[0] ACCESS_TYPE R/W/ PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 839 3-pin MediaLB mode 5-pin MediaLB mode Note: − This device does not support 5-pin MediaLB interface and therefore writing "1" to this bit is prohibited. Make sure the bit is set to "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 840 Even when the MLBn_DCCR:MHRE bit is "1" and the reset operation by the receipt of the reset command is in progress, this bit is reset to "0" after the execution of the reset command. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 841 The DA is used by the system channel MlbScan and MlbReset commands. The received DA (DA[15:0]) operates as the command target when DA[15:9] and DA[0] are "0" and DA[8:1] matches this bit field. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 842 ACCESS_TYPE R0WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME SSRE SDMU SDML SDSC SDCS SDNU SDNL ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:8] read0 : - S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 843 This bit is set to indicate that the MediaLB Device has received the MlbScan (0xE4) System Command. The target DeviceAddress is stored in the MLBn_SDCR register. If not masked by the System Mask S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 844 MediaLB interface. System software must service status events before the start of the next MediaLB frame to prevent the current frame status from being lost. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 845 MLBn_SDCR is updated once per frame by hardware during the MediaLB System Channel. System software must read MLBn_SDCR before the start of the next MediaLB frame to prevent the current frame data from being lost. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 846 ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME read0 SMMU SMML SMSC SMCS SMNU SMNL ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE [bit31:8] read0 : - S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 847 The receipt of the system command, MOST_Unlock(0xE2) is indicated by MLBn_SSCR:SDNU. Description Interrupt due to the receipt of the MOST_Unlock(0xE2) system command is not masked. Interrupt due to the receipt of the MOST_Unlock(0xE2) system command is masked. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 848 The receipt of system command, MlbReset(0xFE)is indicated by MLBn_SSCR:SDR. Description Interrupt due to the receipt of the MlbReset(0xFE) system command is not masked. Interrupt due to the receipt of the MlbReset(0xFE) system command is masked. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 849 R,WX R,WX R,WX R,WX R,WX R,WX R,WX PROT_TYPE INITIAL_VALUE [bit31:24] UMA[7:0] : User Major Revision Code User Major Revision Code. [bit23:16] UMI[7:0] : User Minor Revision Code User Minor Revision Code. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 850 MediaLB Minor Revision Code. This field identifies the minor revision of the MediaLB module (OS62400) implemented on this device. This value is hard-coded by the vendor. Note: − For OS62400 version code information, refer to the device datasheet. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 851 This base address is shared by all synchronous receive channels and defines the upper 16 bits of the 32-bit address for these channels. This bit field is only used in DMA mode. In IO mode these bits are not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 852 This base address is shared by all synchronous transmit channels and defines the upper 16 bits of the 32-bit address for these channels. This bit field is only used in DMA mode. In IO mode these bits are not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 853 This base address is shared by all asynchronous receive channels and defines the upper 16 bits of the 32-bit system bus address for these channels. This bit field is only used in DMA mode. In IO mode these bits are not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 854 This base address is shared by all asynchronous transmit channels and defines the upper 16 bits of the 32-bit system bus address for these channels. This bit field is only used in DMA mode. In IO mode these bits are not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 855 This base address is shared by all control receive channels and defines the upper 16 bits of the 32-bit system bus address for these channels. This bit field is only used in DMA mode. In IO mode these bits are not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 856 This base address is shared by all control transmit channels and defines the upper 16 bits of the 32-bit system bus address for these channels. This bit field is only used in DMA mode. In IO mode these bits are not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 857 This base address is shared by all isochronous receive channels and defines the upper 16 bits of the 32-bit system bus address for these channels. This bit field is only used in DMA mode. In IO mode these bits are not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 858 This base address is shared by all isochronous transmit channels and defines the upper 16 bits of the 32-bit system bus address for these channels. This bit field is only used in DMA mode. In IO mode these bits are not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 859 CNSU[n] indicates whether there is an interrupt for Channel n. Description If CNSU[n] is "0" there is no interrupt for Channel n. If CNSU[n] is "1" Channel n has an interrupt. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 860 MLBn_CSCRn register. For example, if MLBn_CNSU[4] is set, writing FFFFh to MLBn_CSCR4[15:0] releases the channel interrupt (MLBn_CINT) and clears MLBn_CICR[4]. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 861 EQ[3] EQ[2] EQ[1] EQ[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31:16] MAXTRANS[15:0] Always write "0" to this register. Read value is "X". [bit15:0] MCYCNONREQ[15:0] Always write "0" to this register. Read value is "X". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 862 MASK[1] MASK[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME IPL[7] IPL[6] IPL[5] IPL[4] IPL[3] IPL[2] IPL[1] IPL[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME CA[7] CA[6] CA[5] CA[4] CA[3] CA[2] CA[1] CA[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 863 [bit26:25] MDS[1:0] : Channel Mode Select Sets the channel mode. Bits Description DMA mode enable (Ping-pong buffering) DMA mode enable (Circular buffering) IO mode enable Reserved. It is prohibited to set MDS[1:0] = "11" S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 864 MASK[0] - Sets whether the channel interrupt due a protocol error should be masked. The status bit targeted for masking is CSCRn:STS[0]. Description Protocol error channel interrupt is not masked Protocol error channel interrupt is masked S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 865 ChannelAddress of each received physical channel from the MediaLB Controller. There is a ChannelAddress match if and only if the ChannelAddress recovered from the MediaLB input, MLBn_MLBSIG, equals the ChannelAddress defined by: CA[15:0] = {7'h00, CA[8:1], 1'b0} S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 866 BIT_OFFSET BIT_NAME read0 read0 read0 read0 IVB[1] IVB[0] ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R,WX R,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME STS[3] STS[2] STS[1] STS[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME ACCESS_TYPE PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 867 ReceiverBreak (0x70) and stop the transfer. This bit is set by system software and cleared by hardware. [bit16] RDY : Next Buffer Ready This bit has a different interpretation depending on DMA-mode or IO-mode. In IO Mode this bit is not used. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 868 ControlStart (0x30) or AsyncStart (0x20). This status bit can be used by system software to detect when it has reached the end of an aborted packet. This bit is valid for asynchronous and control RX channels only. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 869 The setting of this bit generates a non-maskable channel interrupt to system software. Write "1" to clear this bit. Writing "0" has no effect. Once set, this bit holds until it is cleared by software. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 870 (0x36) or AsyncBreak (0x26), while processing the Current Buffer. The setting of this bit generates a maskable channel interrupt to system software. This bit is valid for asynchronous and control channels S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 871 RX channel types and valid for only asynchronous and control TX channels. Write "1" to clear this bit. Writing "0" has no effect. Once set, this bit holds until it is cleared by software. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 872 In DMA mode, the BCA field defines a 16-bit address pointer, which identifies the lower half of the beginning address of the Current Buffer in system memory. The BCA[15:2] bits are loaded from S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 873 In IO mode, this bit field defines the Receive Data Buffer bits - RDB[15:0]. This field contains the lower half of the next quadlet of receive data when the logical channel is configured as receive channel. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 874 [bit31:16] BSA[15:0] : Buffer Start Address bits This bit field has different interpretations for DMA mode and IO mode. In DMA mode, the BSA field defines a 16-bit address pointer, which identifies the lower half of the S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 875 In IO mode, this bit field defines the Transmit Data Buffer bits - TDB[15:0]. This field contains the lower half of the next quadlet of transmit data when the logical channel is configured as transmit channel. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 876 ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME read0 read0 SA[5] SA[4] SA[3] SA[2] SA[1] SA[0] ACCESS_TYPE R0,WX R0,WX PROT_TYPE INITIAL_VALUE [bit31:29] read0 : - S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 877 The initial value of SA[5:0] is n*4, where n is the channel number (0,1,2 ... 15). The initial value of SA[5:0] for Channel 0 is 0x0, for Channel 1 is 0x4, for Channel 2 is 0x8 and so on. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 878 This register helps in developing software to the hardware version implemented in the device. Note: − Please refer to the device specific data sheet for the MID value. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 879 Stereo Audio DAC CHAPTER 23: This chapter presents the Stereo Audio Digital to Analog Converter(DAC). Overview Configuration and Block Diagram Operation Registers CODE: ADAC-T01P01R02L01-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 880 Dual port AHB IF FIFO R-BUS IF DAC IF Analog output 32bit * 24 DMA IF STATEI[1:0] STATEO[1:0] DACRDAEI DACRDAEO DACRINII DACRINIO CPU IF BUSYI BUSYO D/A TEST IF TEST MODE IF S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 881 DAE bit of the DACR register during power up or power down. Add external circuitry to suppress such pop noises if necessary. − Do not change the DPCR register dynamically. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 882 (0.5 + 0.3365 × (-3/32768)) × AVCC(DAC) FFFEH (0.5 + 0.3365 × (-2/32768)) × AVCC(DAC) FFFFH (0.5 + 0.3365 × (-1/32768)) × AVCC(DAC) Note: − The Stereo Audio DAC does not feature integrated output voltage buffers. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 883 This interrupt indicates an under-run of the FIFO buffer for data samples. I.e. the analog DAC has tried to read a data sample from the FIFO buffer when it was empty. 4. DMA Block Error Interrupt S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 884 DADR0-15. Table 4 Outline of FIFO Item Content Width of data 32bit Width of address 5bit Depth Composition Register S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 885 11.2896 11.025kHz 2.8224MHz 22.5792 5.6448MHz 45.1584 1/10 28.224 1/10 56.448 1/16 45.1584 1/16 90.3168 3.072 6.144 6.144 12.288 12kHz 3.072MHz 24.576 6.144MHz 49.152 1/10 30.72 1/10 61.44 1/16 49.152 1/16 98.304 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 886 1/16 180.6336 1/16 361.2672 12.288 24.576 24.576 49.152 48kHz 12.288MHz 98.304 24.576MHz 196.608 1/10 122.88 1/10 245.76 1/16 196.608 1/16 393.216 Note: − DACCLK is DACCLK field of the DAOSR register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 887 L ≠ R is input. − Do not set the value of the DPCR register to 00b or 11b. Because the amplitude is counterbalanced when connecting it with one speaker S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 888 Reserved Reserved Reserved Reserved ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME Reserved DACCLK2 DACCLK1 DACCLK0 Reserved Reserved OSR1 OSR0 ACCESS_TYPE R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 889 Always write "0" to this bit. The read value is "0". [bit1:0] OSR[1:0]:Over sampling Explanation of OSR[1:0] Bits Description Over sampling ratio : 64 Over sampling ratio : 128 Over sampling ratio : 256 Over sampling ratio : 512 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 890 Reserved Reserved Reserved Reserved ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE [bit31:9] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 891 Always write "0" to this bit. The read value is "0". [bit0] DAE: DAC enable Explanation of DAC enable Description Disable operation. The analog DAC output pins will output 0.0V. (default) Normal operation. The analog DAC output pins will be enabled. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 892 Always write "0" to this bit. The read value is "0". [bit0] DABUSY: DAOSR/DACR BUSY Explanation of DAOSR/DACR Description The write access to the DAOSR/DACR register is possible. The write access to the DAOSR/DACR register is impossible. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 893 CLKDA. DABUSY field indicates that the write access to DAOSR / DACR register has not been completed. Write access to DAOSR / DACR register is discarded in the case of DABUSY=1. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 894 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE [bit31:21] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". [bit20:16] FEST[4:0]:FIFO Empty threshold Explanation of FEST[4:0] S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 895 The DMA interface is enabled Notes: − This bit must not be changed during the DMA transfers [bit7:0] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 896 [bit31:1] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". [bit0] FLUSH: FIFO FLUSH Explanation of FIFO FLUSH Description No change Enable FIFO FLUSH Mode S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 897 CHAPTER 23:Stereo Audio DAC Note: − The write access to this register is effective at DACR_INIT=1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 898 Reserved Reserved Reserved DMA_ERR UDRN OVFL DREQ ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE [bit31:4] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 899 The FIFO overflow error interrupt is disabled (default) The FIFO overflow error interrupt is enabled [bit0] DREQ: Date Request Explanation of DREQ Description The FIFO data request interrupt is disabled (default) The FIFO data request interrupt is enabled S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 900 R0,W0 R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE [bit31:4] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". [bit3] DMA_ERR: DMA Block Error Explanation of DMA_ERR S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 901 − DREQ bit is set to "0" by a reset input. However, DREQ bit is set to "1" by releasing the reset. Because FIFO is empty after the reset is released S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 902 UDRN OVFL DREQ ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W R0,W R0,W R0,W PROT_TYPE INITIAL_VALUE [bit31:4] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 903 − DREQ bit is set to "0" by a reset input. However, DREQ bit is set to "1" by releasing the reset. Because FIFO is empty after the reset is released S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 904 Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 PROT_TYPE INITIAL_VALUE [bit31:2] Reserved This bit is reserved. Always write "0" to this bit. The read value is "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 905 Explanation of PCL Description No influence LDATA Polarity conversion [bit0] PCR: The lower 16bits (Right-DATA) polarity conversion Explanation of PCR Description Leave the FIFO under-run error interrupt unchanged RDATA Polarity conversion S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 906 Notes: − The DADR register accepts 32 bit word writes only. Please set the same value as DADR[31:16] and DADR[15:0] when outputting it by monaural. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 907 This chapter explains the functions and operations of the serial audio interface that is the Inter IC Sound (I2S). Overview Configuration and Block Diagram Operations of the I2S Registers CODE: I2S-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 908 Frequency dividing ratio is settable within 0-126 in multiple of 2 (when the ratio is "0", frequency dividing source is bypassed)  Data transfer to system memory by DMA, interrupt, and polling  Debug support S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 909 The supply clock of I2S can be internal or external (ECLK) source. This clock is then pre-scaled to required frequency through I2S control register bits I2Sn_CNTREG:CKRT[5:0]  Frame frequency can be adjusted using I2Sn_CNTREG:OVHD[9:0] bits S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 910 Pulse width of WS can be set to 1 bit or 1 channel length by setting I2Sn_CNTREG:FSLN  Frame sync phase of WS can be set to "0" or "1" clock through I2Sn_CNTREG:FSPH  In this construction, settings of I2Sn_MCR0REG:S1CHN and I2Sn_MCR2REG:S1WDL are ignored S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 911 1 channel is determined by the channel length of sub frame "0"  Frame sync phase of WS can be set to "0" or "1" clock through I2Sn_CNTREG:FSPH bit S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 912 FIFO status is always confirmed. If transmission empty frame is output. FIFO is not empty, frame synchronous signal is output to perform frame transmission. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 913 I2Sn_STATUS:FERR is set to "1". If the next frame synchronous signal is input before completing 1 frame transmission in the burst mode, I2Sn_STATUS:FERR is set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 914 FIFO occurs while it is empty. If frame synchronous signal is not input with the frame rate defined by the register setting, I2Sn_STATUS:FERR bit is set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 915 FIFO status is always confirmed. If transmission FIFO is not empty transmission FIFO is empty. and reception FIFO is not full, frame synchronous signal is output to perform frame transmission/reception. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 916 I2Sn_OPRREG:RXENB status. The clock supply to the internal serial control part stops regardless of I2Sn_OPRREG:TXENB and I2Sn_OPRREG:RXENB status. SCK output to the external part and frame synchronous signal output is also stopped. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 917 I2Sn_STATUS:RXOVR is set to "1". I2Sn_STATUS:FERR is set to "1". If the following frame synchronous signal is input before completing one frame transmission in the burst mode, I2Sn_STATUS:FERR is set to "1". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 918 AB0, AB1, AB2, AB3, AH0, AH1, and AW on the above chart indicate byte 0, byte 1, byte 2, byte 3, half word 0, half word 1, and word at write accessing to I2Sn_TXFDAT0 to 15 on AHB bus S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 919 Therefore, read access should be performed from AHB bus to I2Sn_RXFDAT0 to 15 in order to read as follows: Word length: − 8 or less: byte 0 − 9- 16: half word 0 − 17-32: all words S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 920 From I2Sn_TXFDAT0~15 register To transmssion pin When I2Sn_CNTREG:TXDIS = "0" and I2Sn_CNTREG:RXDIS = "0", the mode is set to simultaneous transfer mode which operates with 66-word x 32-bit transmission and reception FIFOs. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 921 To transmssion pin When I2Sn_CNTREG:TXDIS = "0" and I2Sn_CNTREG:RXDIS = "1", the mode is set to transmission only mode which operates with a 132-word x 32-bit transmission FIFO, and reception is not performed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 922 To transmssion pin When I2Sn_CNTREG:TXDIS = "1" and I2Sn_CNTREG:RXDIS = "0", the mode is set to reception only mode which operates with a 132-word x 32-bit reception FIFO, and transmission is not performed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 923 Rewrite to I2Sn_CNTREG, I2Sn_MCR0REG, I2Sn_MCR1REG, and I2Sn_MCR2REG is prohibited after I2Sn_OPRREG:START is set  Rewrite to I2Sn_CNTREG, I2Sn_MCR0REG, I2Sn_MCR1REG, and I2Sn_MCR2REG is prohibited while DBGE is set to "1" and the processor is in debug state S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 924 00000000 00000000 00000000 00000000 I2Sn_RXFDAT5 0x00000014 B,H,W 00000000 00000000 00000000 00000000 I2Sn_RXFDAT6 0x00000018 B,H,W 00000000 00000000 00000000 00000000 I2Sn_RXFDAT7 0x0000001C B,H,W 00000000 00000000 00000000 00000000 I2Sn_RXFDAT8 0x00000020 B,H,W 00000000 00000000 00000000 00000000 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 925 00000000 00000000 00000000 00000000 I2Sn_TXFDAT11 0x0000006C B,H,W 00000000 00000000 00000000 00000000 I2Sn_TXFDAT12 0x00000070 B,H,W 00000000 00000000 00000000 00000000 I2Sn_TXFDAT13 0x00000074 B,H,W 00000000 00000000 00000000 00000000 I2Sn_TXFDAT14 0x00000078 B,H,W 00000000 00000000 00000000 00000000 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 926 00000000 00000000 00000000 00000000 I2Sn_DMAACT 0x000000A0 B,H,W 00000000 00000000 00000000 00000000 I2Sn_DEBUG 0x000000A4 B,H,W 00000000 00000000 00000000 00000000 I2Sn_MIDREG 0x000000A8 B,H,W 00000000 00000000 00000000 00000000 reserved 0x000000AC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 927 For the case that word length set to I2Sn_MCR0REG:S1WDL is 32 bits or less, reception data of sub frame 1 is written to reception FIFO after higher order bit is extended. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 928 (I2Sn_STATUS:RXUDR) flag is set, if the read cycle was initiated by the AHB master other than the DAP controller. If the DAP controller reads this register while the Rx FIFO is empty, the I2Sn_STATUS:RXUDR flag is not set. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 929 I2Sn_MCR0REG:S0WDL and I2Sn_MCR0REG:S1WDL (when frame is 2 sub frame). The data read from I2Sn_TXFDAT0 returns "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 930 OVHD[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME read0 MSKB MSMD SBFN RHLL ECKM BEXT FRUN ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME MSLB TXDIS RXDIS SMPL CPOL FSPH FSLN FSPL ACCESS_TYPE PROT_TYPE INITIAL_VALUE S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 931 For the case that transmission word length is shorter than the channel length, MSKB is driven to the rest of bit in transmission channel (channel length - word length). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 932 Description Extended by "0" Extended by sign bit (if MSB of word/half word is "1", then it is extended by "1", if MSB is "0" then it is extended by "0") S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 933 SCK polarity which drives/samples serial data is specified. Description Data is driven at rising edge of SCK, and sampled at falling edge Data is driven at falling edge of SCK, and sampled at rising edge S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 934 I2Sn_MCR0REG:S0CHN = 0x0 and I2Sn_CNTREG:SBFN = "0". [bit0] FSPL : Frame Sync Polarity Polarity of WS is set. Description Frame synchronous signal becomes valid when WS is "1" Frame synchronous signal becomes valid when WS is "0" S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 935 BIT_OFFSET BIT_NAME read0 S0CHN[4] S0CHN[3] S0CHN[2] S0CHN[1] S0CHN[0] S0CHL[4] S0CHL[3] ACCESS_TYPE R0,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME S0CHL[2] S0CHL[1] S0CHL[0] S0WDL[4] S0WDL[3] S0WDL[2] S0WDL[1] S0WDL[0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit31] read0 : - S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 936 S1WDL needs to be set less than or equal to the value set in I2Sn_MCR0REG:S1CHL. Setting examples are shown below. Bits Description 00000-00101 Setting is prohibited 00110 Sub frame 1 word length is 7 bits 00111 Sub frame 1 word length is 8 bits S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 937 Sub frame 0 becomes 2 channel construction 00010 Sub frame 0 becomes 3 channel construction 11110 Sub frame 0 becomes 31 channel construction 11111 Sub frame 0 becomes 32 channel construction S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 938 Sub frame 0 word length is 32 bits Notes: − 1. If I2Sn_CNTREG:RHLL is "1", set word length to 16 bits or less. − 2. If I2Sn_CNTREG:RHLL is "0", set word length to 32 bits or less. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 939 0, S0CH[31] bit controls 31st channel of sub frame 0). Description The corresponding channel is disabled Transmission/reception is not performed to the disabled channel. The corresponding channel is enabled Transmission/reception is performed to the enabled channel. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 940 (I2Sn_CNTREG:SBFN is "0"), this is invalid. Description The corresponding channel is disabled Transmission/reception is not performed to the disabled channel. The corresponding channel is enabled Transmission/reception is performed to the enabled channel. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 941 When RXENB is "0", the data received from serial reception bus is not written to reception FIFO. DMA reception channel stops during DMA transfer. Receiving operation is enabled [bit23:17] read0 : - S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 942 I2S is stopped and internal transmission/reception FIFO becomes empty by writing "0" to this bit I2S is operable. When START is "1", it is prohibited to rewrite I2Sn_CNTREG, I2Sn_MCR0REG, I2Sn_MCR1REG, and I2Sn_MCR2REG registers. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 943 There is no influence to registers other than I2Sn_STATUS, I2Sn_INTCNT, and I2Sn_DMAACT registers. When read value is "0" after writing "1", it indicates software reset is completed. "1" indicates software reset is in process. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 944 Interrupt to CPU by I2Sn_STATUS:TXUDR1 is masked [bit29] TBERM : Tx Block Size Error Interrupt Mask This is interrupt mask bit of block size error of transmission channel. It becomes "1" by software reset. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 945 This is transmission FIFO interrupt mask bit. It becomes "1" by software reset. Description Interrupt to CPU by I2Sn_STATUS:TXFI is not masked Interrupt to CPU by I2Sn_STATUS:TXFI is masked [bit23:22] read0 : - S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 946 Rx DMA block transfer has completed and there is no Rx block size error. DMA transfer is not requested [bit16] RXFIM : Rx FIFO Interrupt Mask This is reception FIFO interrupt mask bit. It becomes "1" by software reset. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 947 Number of receive words in reception FIFO is more than threshold value, previous Rx DMA block transfer has completed, there is no Rx block size error and I2Sn_INTCNT:RXFDM is "0": DMA is requested to DMAC. Note: − These bits must not be changed during DMA transfers S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 948 I2Sn_INTCNT:TFTH + 1, this bit is set to 1 and the DMA transmission channel is stopped. When TBERR is "1" and I2Sn_INTCNT:TBERM is "0", interrupt to CPU occurs. This bit becomes "0" by software reset. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 949 FIFO is full. The value "1" indicates 1 word or more of transmission data is ignored. When TXOVR is "1" and I2Sn_INTCNT:TXOVM is "0", interrupt to CPU occurs. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 950 When EOPI is "1" and I2Sn_INTCNT:EOPM is "0", interrupt to CPU occurs. Writing "1" from CPU clears the value to "0". This bit becomes "0" by software reset. [bit18] BSY : Serial Tx Busy S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 951 Reception FIFO Data Registers. Maximum value of 66 can be displayed in the simultaneous transfer mode and value of 132 in the reception mode. This field becomes "00000000" by software reset. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 952 R0,WX R0,WX R0,WX R0,WX R0,WX PROT_TYPE INITIAL_VALUE BIT_OFFSET BIT_NAME read0 read0 read0 read0 read0 read0 read0 RDMACT ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX PROT_TYPE INITIAL_VALUE [bit31:24] read0 : - S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 953 Writing "0" from CPU clears the value to "0". This bit becomes "0" by software reset. Description DMA reception channel is disabled DMA reception channel is enabled Clearing RDMACT also clears reception transfer request. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 954 [bit0] DBGE : Debug Enable (DBGE) This bit is used to enable/disable debug mode for I2S. Description Debug mode disabled Debug mode enabled This bit takes effect only in master mode (i.e. I2Sn_CNTREG:MSMD = "1"). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 955 SCK output. The activity on the serial clock resumes either when the processor leaves debug state or DBGE is set to "0". S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 956 This read-only register gives the unique module identification number of I2S module. The unique Module ID number identifies the version of the I2S module used in the MCU. Refer to the device specific datasheet for the module identification number of its I2S. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 957 Programmable CRC CHAPTER 25: This chapter explains the function and operation of the Programmable CRC. Overview Configuration and Block Diagram Operation of the Programmable CRC Registers CODE: PRGCRC-S6J3200-E1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 958 Programmable CRC module can be configured to widely used common CRC standards, some of them are listed below:  CRC-32-IEEE 802.3  CRC-16-CCITT  CRC-8-CCITT  CRC-5-USB  CRC-XMODEM  12-bit CRC  10-bit CRC  8-bit CRC S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 959 3.2, and on an example for CRC calculation see Section 3.3 3.1. CRC Operation Flowcharts The flowcharts Figure 3-1, Figure 3-2 , and Figure 3-3 show the steps to configure CRC registers and to perform a CRC calculation. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 960 CRC engine is CRCn_CFG:LOCK == ’0’ busy CRC input data left? Note: This is polling based CRC calculation. The CPU polls CRCn_CFG:LOCK bit status for the next CRC calculation. Read CRCn_RD S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 961 ISR for CRC−IRQ Clear CRCn_CFG:CIRQ CRC input data left? Note: Write next input data Read checksum from CPU clears interrupt flag CRCn_CFG:CIRQ, by writing ’1’ to CRCn_CFG:CIRQCLR bit. to CRCn_WR register CRCn_RD S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 962 Next block to be written? Note: Re−configure DMA transfer DMA request is cleared on receiving DMA acknowledgment from DMA controller. Enable CRC DMA request Read checksum from CRCn_RD CRCn_CFG:CDEN = ’1’ S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 963 If the input data size is less than 32-bit (SZ < "11"), then the remaining bits (8-,16-, or 24-bit) of the data are considered as don’t care (X) as shown in below table. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 964 "preliminary checksum #1" S[(LEN-1):0] will be located in "preliminary checksum #2" after CRCn_CFG:ROBIT/ROBYT settings have been applied. Only some examples of different CRCn_CFG:LEN configurations are shown. Note: − Only some examples for CRCn_CFG:LEN are shown. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 965 7. The checksum after applying settings of CRCn_CFG:ROBIT/ROBYT is "preliminary checksum #2". 8. The "preliminary checksum #2" is XOR’ed with the contents of CRCn_FXOR register to get the "final checksum". 9. The "final checksum" gets available at CRCn_RD register. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 966 If the new CRC calculation should start from the seed value instead of from the last CRC result, then the CRCn_SEED register needs to be re-written (even if it is the same seed value as before). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 967 11111111 11111111 11111111 11111111 CRCn_CFG 0x0000000C B, H, W 00000000 11100000 00000000 00000000 CRCn_WR 0x00000010 B, H, W 00000000 00000000 00000000 00000000 CRCn_RD 0x00000014 B, H, W 00000000 00000000 00000000 00000000 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 968 If the polynomial length as defined by CRCn_CFG:LEN is less than 32-bit, then the upper bits [31:LEN] must be written to "0" by the programmer. The highest order degree must not be set to "1" while configuring CRCn_POLY register, as it is implicitly defined by CRCn_CFG:LEN. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 969 The CRCn_SEED register should be configured with respect to the polynomial length (CRCn_CFG:LEN). If the polynomial length is less than 32-bit, then the upper bits [31:LEN] must be written to "0" by the programmer. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 970 The bits of this register affect the corresponding bits of the CRCn_RD register. Therefore, the bits not belonging to the checksum should be written to "0". For the position of the checksum bits depending on the used output bit/byte reflection refer to Table 3-3. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 971 CRC engine is busy and writing to CRC registers is not possible. If the data is written to the CRC registers when LOCK bit is "1", then an error response is generated [bit27] read0 : - S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 972 These bits are used to configure the length (degree) of CRC polynomial/checksum as follows: Bits Description 100000 011111 ..000010 Notes: − The following settings are not supported: − CRCn_CFG:LEN > 32 − CRCn_CFG:LEN < 2 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 973 [bit7:1] read0 : - [bit0] CIRQCLR : Interrupt Clear This bit clears the CRC interrupt flag. Description Write "0" is ignored, reading this bit always returns "0" Clear CRC interrupt flag (CRCn_CFG:CIRQ) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 974 The size of input data is configured by CRCn_CFG:SZ, where 8, 16, 24, and 32 bits are only supported as data size. If the input data size is less than 32-bit (i.e. 8, 16, or 24 bits), then the invalid/unused bits are considered as don’t care (X). S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 975 CRCn_FXOR register are not programmed to "0", then these bits in CRCn_RD register might also be "1"). The bit/byte reflection settings (CRCn_CFG:ROBIT/ROBYT) can influence the checksum in CRCn_RD register. For the position of the checksum bits refer toTable 3-3. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 976 PCMPWM CHAPTER 26: This chapter explains the function and operation of the PCMPWM module. Overview Configuration and Block Diagram Operation of the PCMPWM Registers CODE: PCMPWM-S6J3200-E1.1 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 977  FIFO input buffer for PCM samples, with a depth 24  Programmable clock divider for PWM cycle time  Optional output of silence signals in debug mode and normal mode S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 978 These blocks represent the actual PCM to PWM conversion units. Each channel uses its own converter block. Output Control This block controls the PWM signal outputs. It e.g. defines the signals’ output polarity and keeps unused outputs at their inactive levels. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 979 In the simplified H-bridge mode two outputs are used to drive a speaker. A pair of complementary emitter followers is connected to each output. Figure 2-3 depicts the circuit for simplified H-bridge mode. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 980 PCM data samples. The PCMPWM_i_Bx output pair is activated for negative PCM data samples. If the PCM data sample is zero, no branch of the H-bridge is activated. The PCMPWM_i_Ax and PCMPWM_i_Bx branches are never active at the same time. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 981 FIFO buffer to the PCM to PWM conversion units in stereo mode. Figure 2-6 Stereo Mode FIFO Buffer Conversion data[31:16] Unit Ch #1 Conversion data[15:0] Unit Ch #0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 982 FIFO is stopped. Also the FIFO is flushed. The FIFO can then be filled again via DMA or the CPU. As soon as the number of empty entries in the FIFO is equal or less than PCMPWMi_CONTROL:FEST, reading from the FIFO is resumed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 983 Table 2-1 shows the inactive values of all outputs depending on the selected polarity. Table 2-1 Inactive Output Values PCMPWMi_OCTRL:LEVL0/LEVL1 PCMPWM_i_AH/BH PCMPWM_i_AL/BL S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 984 ↓ ↑ compare value PCM sample negative ↓ ↑ Note: − In case the PCM compare value is zero, the event given for equality with the PCM compare value takes precedence. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 985 0 to its maximum value as well as the PCM samples and the corresponding PCM compare value. Figure 3-1 PCM to PWM Conversion in Low-Pass Filter Mode S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 986 CHAPTER 26:PCMPWM Figure 3-2 PCM to PWM Conversion in Simplified H-Bridge Mode S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 987 CHAPTER 26:PCMPWM Figure 3-3 PCM to PWM Conversion in Full H-Bridge Mode S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 988 CHAPTER 26:PCMPWM Figure 3-4 PCM to PWM Conversion in Full H-Bridge Mode (with Dead Timer) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 989 COUNTP Resolution PWM_CLK sample 80 MHz 4,095 19.53 kHz 12 bit 80 MHz 65,535 1.22 kHz 16 bit 80 MHz 78.13 kHz 8 bit 100 MHz 1,023 48.83 kHz 10 bit S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 990 − If the PCM data sample of count period CP is negative, then output signals PCMPWM_i_AL/AH are masked, although this doesn't happen in usual setup. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 991 PCMPWM Count Period Register (PCMPWMi_COUNTP)  PCM Offset Register (PCMPWMi_PCMOFFS)  PCM Interrupt Enable Register (PCMPWMi_INTREN)  PCM Interrupt Status Register (PCMPWMi_INTRSTAT)  PCM Interrupt Clear Register (PCMPWMi_INTRCLR)  PCM Data Register 0..15 (PCMPWMi_DATA) S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 992 This field defines the number of PWM_CLK cycles after the trailing edge for which the opposite phase of the PWM outputs in full H-Bridge Mode are masked with inactive value. Setting of this field to a value greater than or equal to PCMPWMi_COUNTP:COUNTP is not allowed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 993 The module generates silence when the CPU is in debug state; no data is fetched from the FIFO buffer [bit8] DMAEN : DMA Mode Enable This bit controls the module's DMA interface. Description The DMA interface is disabled The DMA interface is enabled S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 994 PCMPWM is disabled; if the module is switched off via this bit, the PWM output stops immediately and the outputs are set to their inactive values; no interrupts and DMA transfers can be requested PCMPWM is enabled S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 995 [bit17] LEVL1 : Output Level Select Channel #1 This bit selects the output polarity of channel #1. Description PCMPWM_1_AH/BH are low-active and PCMPWM_1_AL/BL are high-active PCMPWM_1_AH/BH are high-active and PCMPWM_1_AL/BL are low-active S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 996 [bit0] EN0 : Output Enable Channel #0 This bit enables or disables PWM signal generation on channel #0. Description PCMPWM_0_AH/BH/AL/BL are set to the inactive value The PWM signal is enabled on channel #0 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 997 Divide by 1: Conversion counter clock = PWM_CLK Divide by 2: Conversion counter clock = PWM_CLK/2 Divide by 4: Conversion counter clock = PWM_CLK/4 Divide by 8: Conversion counter clock = PWM_CLK/8 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 998 [bit15:0] COUNTP : Count Period This field defines the value of the PCMPWM conversion counter after which it continues to count from 0. Setting of this field to 0 is not allowed. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 999 BIT_NAME PCM_OFFS[7:0] ACCESS_TYPE PROT_TYPE INITIAL_VALUE [bit15:0] PCM_OFFS : PCM Offset This field defines the offset value used in the PCM signed to unsigned conversion in low-pass filter and simplified H-bridge mode. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...
Page 1000 Description The DMA block error interrupt is disabled The DMA block error interrupt is enabled [bit2] UDRN : FIFO Under-Run Error This bit enables or disables the FIFO under-run error interrupt. S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G...