Sci Interrupt Vector Offset 0 (Sciintvect0); Sci Interrupt Vector Offset 0 (Sciintvect0) Field Descriptions - Texas Instruments TMS320 Series User Manual

www.ti.com
Table 14. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit Field
0 BRKDT
6.9

SCI Interrupt Vector Offset 0 (SCIINTVECT0)

The SCI Interrupt Vector Offset 0 (SCIINTVECT0) is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions
Bit Field
31-5 Reserved
4-0 INTVECT0
6.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1)
The SCI Interrupt Vector Offset 1 (SCIINTVECT1) is shown in
SPRUGE2A – May 2009 – Revised June 2009
Submit Documentation Feedback
Value Description
SCI break-detect flag.
Compatible mode only This bit is set when the SCI detects a break condition on the LINRX pin. A
break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a
missing first stop bit, that is, after a framing error. Detection of a break condition causes the SCI to
generate an error interrupt if the BRKDT INT ENA bit is set.
The BRKDT bit is cleared by the following:
• Reading the corresponding interrupt offset in the SCIINTVECT0/1 register.
• Setting the SWnRESET bit (SCIGCR1.7)
• RESET bit (SCIGCR0.0)
• System reset
• By writing a 1 to this bit.
Read:
0 No break condition detected
1 Break condition detected
Write:
0 No effect
1 Clears this bit to 0
Figure 29. SCI Interrupt Vector Offset 0 (SCIINTVECT0)
Reserved
R-0
Value Description
Reads return zero and writes have no effect.
0–1Fh Interrupt vector offset for INT0.
This register indicates the offset for interrupt line INT0. A read to this register updates its value to
the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset
that was read. See Table 3
Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be
cleared by reading the corresponding offset vector in this register (see detailed description in
SCIFLR register).
Preliminary
Figure 29
Reserved
R-0
5
for list of interrupts.
Figure 30
Local Interconnect Network (LIN) Module
SCI/BLIN Control Registers
and described in Table 15.
4
INTVECT0
R-0
and described in Table 16.
16
0
67