Atmel AT91SAM9RL-EK User Manual page 14

– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation, Manchester
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– High-speed Synchronous Communications
One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
One Four-channel 16-bit PWM Controller (PWMC)
Two Two-wire Interfaces (TWI)
– Compatible with Standard Two-wire Serial Memories
– One, Two or Three Bytes for Slave Address
– Sequential Read/Write Operations
– Master, Multi-master and Slave Mode Operation
– Bit Rate: Up to 400 Kbits
– General Call Supported in Slave mode
– Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers
SAM-BA Boot Assistant
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
– 1.08 to 1.32V for VDDCORE, VDDPLLB and VDDBU
– 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMI and VDDIOP
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM
Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package
AT91SAM9RL-EK Evaluation Board User Guide
Encoding/Decoding
in Master Mode Only (TWI0 only)
Board Description
3-3
6325A–ATARM–08-Jan-08