Configuration
NI 6520/6521 User Guide
Change Detection .............................................................................9
Watchdog Timer...............................................................................10
Digital I/O................................................................................................10
I/O Connector ...................................................................................10
Pin Assignments ...............................................................................11
Signal Descriptions...........................................................................12
Mechanical Relays............................................................................15
Relay Forms ..............................................................................15
Power Connections ..................................................................................17
Isolation Circuitry.............................................................................17
Isolation Voltages.............................................................................17
Specifications...........................................................................................22
The NI 6520/6521 device is completely software configurable, so it is not
necessary to set jumpers for I/O configuration.
The PCI-6520/6521 is fully compliant with the PCI Local Bus
Specification, Revision 2.1, and the PXI-6521 devices are fully compliant
with the PXI Hardware Specification, Revision 2.1. The PCI/PXI system
automatically allocates all device resources, including the base address and
interrupt level. The NI 6520/6521 base address is mapped into PCI memory
space. It is not necessary to perform configuration steps after the system
powers up.
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