Table of Contents
Advertisement
CPU & PCI Bus Control
PCI Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero-wait
states.
The Choices: Enabled (Default) / Disabled
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification.
The Choices: Enabled (Default) / Disabled
DRDY_Timing
The Choices: Optimize (Default) / Slowest / Default
Memory Hole
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved it cannot be cached. Check the user
information of peripherals that need to use this area of system memory
for the memory requirements.
The Choices: Disabled (Default) / 15M-16M
CX70M-PE
39
Advertisement
Table of Contents
