Page 1 TMS320C645x Serial Rapid IO (SRIO) User's Guide Literature Number: SPRU976 March 2006...
Page 2 SPRU976 – March 2006 Submit Documentation Feedback...
Page 3: Table Of Contents
Preface Overview General RapidIO System RapidIO Feature Support in SRIO Standards External Devices Requirements SRIO Functional Description Overview SRIO Pins Functional Operation Logical/Transport Error Handling and Logging Interrupt Conditions CPU Interrupts General Description Interrupt Condition Control Registers Interrupt Status Decode Registers Interrupt Generation Interrupt Pacing Interrupt Handling...
Page 4 5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) 5.26 DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) 5.27 DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) 5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) 5.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) 5.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) 5.31...
Page 5 5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) 5.74 Base Device ID CSR (BASE_ID) 5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) 5.76 Component Tag CSR (COMP_TAG) 5.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) 5.78 Port Link Time-Out Control CSR (SP_LT_CTL) 5.79...
Page 6 RapidIO Architectural Hierarchy RapidIO Interconnect Architecture Serial RapidIO Device to Device Interface Diagrams SRIO Peripheral Block Diagram Operation Sequence 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) Serial RapidIO Control Symbol Format SRIO Conceptual Block Diagram Load/Store Data Transfer Diagram Load/Store Registers for RapidIO (Address Offset: LSU1 0x400-0x418, LSU2 0x420-0x438, LSU3 0x440-0x458, LSU4 0x460-0x478) LSU Registers Timing Example Burst NWRITE_R...
Page 7 Load/Store Module Interrupt Condition Routing Registers Error, Reset, and Special Event Interrupt Condition Routing Registers Sharing of ISDR Bits Example Diagram of Interrupt Status Decode Register Mapping INTDSTn_Decode Interrupt Status Decode Register INTDSTn_RATE_CNTL Interrupt Rate Control Register Peripheral ID Register (PID) Peripheral Control Register (PCR) Peripheral Settings Control Register (PER_SET_CNTL) Peripheral Global Enable Register (GBL_EN)
Page 8 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP) Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP) Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKSn) Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Receive CPPI Control Register (RX_CPPI_CNTL) Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0)
Page 9 Port Error Rate Threshold CSR n (SPn_ERR_THRESH) Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) Port IP Mode CSR (SP_IP_MODE) Serial Port IP Prescalar (IP_PRESCAL) Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPTn) Port Reset Option CSR n (SPn_RST_OPT) Port Control Independent Register n (SPn_CTL_INDEP) Port Silence Timer n (SPn_SILENCE_TIMER) Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) Port Control Symbol Transmit n (SPn_CS_TX)
Page 10 RapidIO Documents and Links Packet Type Pin Description Bits of SERDES_CFGn_CNTL Register (0x120 - 0x12c) Line Rate versus PLL Output Clock Frequency RATE Bit Effects Frequency Range versus MPY Bits of SERDES_CFGRXn_CNTL Registers EQ Bits Bits of SERDES_CFGTXn_CNTL Registers SWING Bits DE Bits Control/Command Register Field Mapping Status Fields...
Page 11 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions LSU Status Interrupt Register (LSU_ICSR) Field Descriptions LSU Clear Interrupt Register (LSU _ICCR) Field Descriptions Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) Field Descriptions Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) Field Descriptions DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) Field Descriptions DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) Field Descriptions...
Page 12 Source Operations CAR (SRC_OP) Field Descriptions Destination Operations CAR (DEST_OP) Field Descriptions Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions Base Device ID CSR (BASE_ID) Field Descriptions Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions Component Tag CSR (COMP_TAG) Field Descriptions...
Page 13: Preface
TMS320C645x DSP Peripherals Overview Reference Guide (literature number SPRUE52) provides a brief description of the peripherals available on the TMS320C645x digital signal processors (DSPs). TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234) is a download with the latest chip support libraries.
Page 14: Overview
Overview The RapidIO peripheral used in the TMS320C645x is called a serial RapidIO (SRIO). This chapter describes the general operation of a RapidIO system, how this module is connected to the outside world, the definitions of terms used within this document, and the features supported and not supported for SRIO.
Page 15: Rapidio Architectural Hierarchy
www.ti.com Figure 1. RapidIO Architectural Hierarchy Logical specification Information necessary for the end point to process the transaction (i.e., transaction type, size, physical address) Transport specification Information to transport packet from end to end in the system (i.e., routing address) Physical specification Information necessary to move packet between two physical devices (i.e., electrical...
Page 16: Rapidio Interconnect Architecture
Overview 1.1.2 RapidIO Interconnect Architecture The interconnect architecture is defined as a packet switched protocol independent of a physical layer implementation. Figure 2 illustrates the interconnection system. Figure 2. RapidIO Interconnect Architecture Host Subsystem Memory Memory Host Host Processor Processor RapidIO RapidIO RapidIO...
Page 17: Rapidio Feature Support In Srio
www.ti.com Figure 3. Serial RapidIO Device to Device Interface Diagrams Serial RapidIO 1x Device to 1x Device Interface Diagram Serial RapidIO 4x Device to 4x Device Interface Diagram RapidIO Feature Support in SRIO Features Supported in SRIO: RapidIO Interconnect Specification V1.2 compliance, Errata 1.2 LP-Serial Specification V1.2 compliance 4X Serial RapidIO with auto-negotiation to 1X port, optional operation for four 1X ports Integrated clock recovery with TI SERDES...
Page 18: Standards
Overview Features Not Supported: Compliance with the Global Shared Memory specification (GSM) 8/16 LP-LVDS compatible Destination support of RapidIO Atomic Operations Simultaneous mixing of frequencies between 1X ports (all ports must be the same frequency) Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal L2 memory and registers Standards The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specification and V1.2 of the...
Page 19: Srio Functional Description
www.ti.com SRIO Functional Description Overview 2.1.1 Peripheral Data Flow This peripheral is designed to be an external slave module that is capable of mastering the internal DMA. This means that an external device can push (burst write) data to the DSP as needed, without having to generate an interrupt to the CPU.
Page 20: Srio Peripheral Block Diagram
SRIO Functional Description 1.25-3.125 Gbps differential data Rx Clock recovery Clock recovery Clock recovery Clock recovery Within the physical layer, the data next goes to the 8b/10b decode block. 8b/10b encoding is used by RapidIO to ensure adequate data transitions for the clock recovery circuits. Here the 20% encoding overhead is removed as the 10-bit data is decoded to the raw 8-bit data.
Page 21: Operation Sequence
www.ti.com SRIO endpoints are typically not connected directly to each other but instead have intervening connection fabric devices. Control symbols are used to manage the flow of transactions in the SRIO physical interconnect. Control symbols are used for packet acknowledgment, flow control information, and maintenance functions.
Page 22: 1X/4X Rapidio Packet Data Stream (Streaming-Write Class)
SRIO Functional Description Figure 6. 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) address rsrv xamsbs prio tt ftype destID acklD rsv sourcelD acklD sourcelD address rsrv xamsbs destiD prio ftype Note: Figure 6 assumes that addresses are 32-bit and device IDs are 8-bit. The device ID, being an 8-bit field, will address up to 256 nodes in the system.
Page 23: Packet Type
www.ti.com The type of received packet determines how the packet routing is handled. Reserved or undefined packet types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous allocation of resources to them. Unsupported packet types are responded to with an error response packet.
Page 24: Srio Pins
SRIO Functional Description SRIO Pins The SRIO device pins are high-speed differential signals based on Current-Mode Logic (CML) switching levels. The transmit and receive buffers are self-contained within the clock recovery blocks. The reference clock input is not incorporated into the SERDES macro. It uses a common LVDS input buffer that aligns interfaces with crystal oscillator manufacturers.
Page 25: Srio Conceptual Block Diagram
www.ti.com Figure 8. SRIO Conceptual Block Diagram DMA bus 128-bit Load/store unit (LSU) Tx direct I/O Maintenance 4.5 KB Tx shared buffer 128-bit TX buffering 32 x 276B 8 buffers per 1X port - all priorities 32 buffers per 4X port - 8 per priority Port 0 8 x 276 TX 8 x 276 RX...
Page 26: Bits Of Serdes_Cfgn_Cntl Register (0X120 - 0X12C)
SRIO Functional Description 2.3.2 SERDES and its Configurations SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can be used for all three frequency nodes specified in V1.2 of the RapidIO specification (1.25, 2.5, and 3.125 Gbps).
Page 27: Line Rate Versus Pll Output Clock Frequency
www.ti.com Table 4. Bits of SERDES_CFGn_CNTL Register (0x120 - 0x12c) (continued) Name Value Description PLL multiply. Select PLL multiply factors between 4 and 60. Multiply modes shown below. 0000 0001 0010 0011 Reserved 0100 0101 0110 0111 12.5x 1000 1001 1010 1011 Reserved...
Page 28: Frequency Range Versus Mpy
SRIO Functional Description Here is the frequency range versus MPY: RIOCLK and RIOCLK Range (MHz) 250 - 425 200 - 425 167 - 354.167 125 - 265.625 100 - 212.5 83.33 - 177.08 12.5x 80 - 170 66.67 - 141.67 50 - 106.25 40 - 85 25 - 42.5...
Page 29 www.ti.com Table 8. Bits of SERDES_CFGRXn_CNTL Registers (continued) Field Value 15:14 13:12 ALIGN Reserved 10:8 TERM INVPAIR RATE BUS- WIDTH Reserved ENRX SPRU976 – March 2006 Submit Documentation Feedback Description Loss of signal. Enables loss of signal detection with 2 selectable thresholds. Disabled.
Page 30: Eq Bits
SRIO Functional Description CFGRX[22:19] 0000 0001 001x 01xx 1000 1001 1010 1011 1100 1101 1110 1111 2.3.2.3 Enabling the Transmitter To enable a transmitter for serialization, the ENTX bit of the associated SERDES_CFGTXn_CNTL registers (0x110 – 0x10c) must be set high. When ENTX is low, all digital circuitry within the transmitter will be disabled, and clocks will be gated off, with the exception of the transmit clock (TXBCLK[n]) output, which will continue to operate normally.
Page 31: Swing Bits
www.ti.com Table 10. Bits of SERDES_CFGTXn_CNTL Registers (continued) Field Value BUS- WIDTH Reserved ENTX CFGTX[11:9] CFGTX[15:12] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SPRU976 – March 2006 Submit Documentation Feedback Description Bus width.
Page 32: Load/Store Data Transfer Diagram
SRIO Functional Description 2.3.2.4 SERDES Configuration Example rdata = SRIO_REGS->SERDES_CFG0_CNTL; wdata = 0x00000001; mask = 0x00000FFF; mdata = (wdata & mask) | (rdata & ~mask); SRIO_REGS->SERDES_CFG0_CNTL SRIO_REGS->SERDES_CFG1_CNTL SRIO_REGS->SERDES_CFG2_CNTL SRIO_REGS->SERDES_CFG3_CNTL SRIO_REGS->SERDES_CFGRX0_CNTL SRIO_REGS->SERDES_CFGRX1_CNTL SRIO_REGS->SERDES_CFGRX2_CNTL SRIO_REGS->SERDES_CFGRX3_CNTL SRIO_REGS->SERDES_CFGTX0_CNTL SRIO_REGS->SERDES_CFGTX1_CNTL SRIO_REGS->SERDES_CFGTX2_CNTL SRIO_REGS->SERDES_CFGTX3_CNTL 2.3.3 DirectIO The DirectIO (Load/Store) module serves as the source of all outgoing direct I/O packets. With Direct I/O, the RapidIO packet contains the specific address where the data should be stored or read in the destination device.
Page 33: Load/Store Registers For Rapidio (Address Offset: Lsu1 0X400-0X418, Lsu2 0X420-0X438, Lsu3 0X440-0X458, Lsu4 0X460-0X478)
www.ti.com Figure 10. Load/Store Registers for RapidIO (Address Offset: LSU1 0x400-0x418, LSU2 0x420-0x438, LSU_Reg0 LSU_Reg1 LSU_Reg2 LSU_Reg3 LSU_Reg4 OutPortID LSU_Reg5 Drbll Info LSU_Reg6 Mapping of command register fields to RapidIO packet header fields is as follows: Table 13. Control/Command Register Field Mapping Control/Command Register RapidIO Packet Header Field Field...
Page 34: Status Fields
SRIO Functional Description Table 13. Control/Command Register Field Mapping (continued) Control/Command Register RapidIO Packet Header Field Field Packet Type 4 msb = 4b ftype field for all packets and 4 lsb = 4b trans field for packet types 2,5,8. OutPortID Not available in RapidIO header.
Page 35: Lsu Registers Timing
www.ti.com LSU_Reg1 LSU_Reg2 LSU_Reg3 LSU_Reg4 LSU_Reg5 Rdy/BSY Completion The following code illustrates an LSU registers programming example. SRIO_REGS->;LSU1_Reg0 = //poll mode, extended address type 2,5,6 SRIO_REGS->;LSU1_Reg1 = //32bit = type 2,5,6. 24bit = type 8 SRIO_REGS->;LSU1_Reg2 = SRIO_REGS->;LSU1_Reg3 = SRIO_REGS->;LSU1_Reg4 = SRIO_REGS->;LSU1_Reg5 = Figure 12 illustrates an example of the data flow and field mappings for a burst NWRITE_R transaction:...
Page 36: Example Burst Nwrite_R
SRIO Functional Description Priority OutPortID LSUn_REG5 Drbll Hop Count Packet 16 15 ackID prio ftype destID sourceID For WRITE commands, the payload is combined with the header information from the control/command registers and buffered in the shared TX buffer resource pool. Finally, it is forwarded to the TX FIFO for transmission.
Page 37: Load/Store Module Data Flow
www.ti.com UDI interface RapidIO transport and physical layers Port x transmission FIFO queues FIFO FIFO 2.3.3.2 TX Operation WRITE Transactions: The TX buffers are implemented in a single SRAM and shared between multiple cores. A state machine arbitrates and assigns available buffers between the LSUs. When the DMA bus read request is transmitted, the appropriate TX buffer address is specified within it.
Page 38 SRIO Functional Description For posted WRITE operations, which do not require a RapidIO response packet, a core may submit multiple outstanding requests. For instance, a single core may have many streaming write packets buffered at any given time, given outgoing resources. In this application, the control/command registers can be released (BSY = 0) to the CPU as soon as the header info is written into the shared TX buffer pool.
Page 39 www.ti.com Segmentation: The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count of Read/Write requests exceeds 256 bytes (up to 4KB). The second type is when Read/Write request RapidIO address is non-64b aligned. In both cases, the outgoing request must be broken up into multiple RapidIO request packets.
Page 40 SRIO Functional Description So the general flow is as follows: Previously, the control/command registers were written and the request packet was sent Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not based on priority) targetTID is examined to determine routing of a response to the appropriate core The status field of the response packet is checked for ERROR, RETRY or DONE If the field is DONE, it submits DMA bus request and transmits the payload (if any) to DSP address.
Page 41: Cppi Rx Scheme For Rapidio
www.ti.com 2.3.4.1 RX Operation As message packets are received by the RapidIO ports, the data must be written into memory while maintaining accurate state information that is needed for future processing. For instance, if a message spans multiple packets, information must be saved that allows re-assembly of those packets by the CPU. The CPPI module provides a scheme for tracking single and multi-packet messages, linking messages in queues, and generating interrupts.
Page 42: Queue Mapping Table (Address Offset: 0X0800 - 0X08Fc)
SRIO Functional Description This allows the letter and mailbox fields to instead allow four concurrent single-segment messages to sixty-four possible mailboxes (256 total locations) for a source and destination pair. The mailbox mapper directs the inbound messages to the appropriate queue based on a pre-programmed routing table. It bases the decision on the SOURCEID, MSGLEN, MBOX, LETTER, and XMBOX fields of the RapidIO packet.
Page 43: Queue Mapping Register Rxu_Map_Ln
www.ti.com Figure 17. Queue Mapping Register RXU_MAP_Ln Letter Mask Mailbox Mask R/W-11 R/W-111111 LEGEND: R = Read, W = Write, n = value at reset Figure 18. Queue Mapping Register RXU_MAP_Hn Reserved LEGEND: R = Read, W = Write, n = value at reset The packet manager maintains the RX DMA state of free and used data buffers within the memory space.
Page 44: Rx Buffer Descriptor Fields
SRIO Functional Description If a multi-segment buffer descriptor queue is not currently free, and an Rx port receives another multi-segment message that is destined for that queue, the RX CPPI must send a RETRY RESPONSE packet (Type 13) to the sender, indicating that an internal buffering problem exists. If a multi-segment buffer descriptor queue is busy and there is another incoming multi-segment message with the same SOURCEID, MAILBOX, and LETTER, an ERROR response is sent.
Page 45: Rx Buffer Descriptor Field Descriptions
www.ti.com Table 17. RX Buffer Descriptor Field Descriptions Field next_descriptor_pointer buffer_pointer Sop = 1 Eop = 1 ownership Teardown_Complete message_length Src_id SPRU976 – March 2006 Submit Documentation Feedback Description Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer descriptor in the RX queue.
Page 46 SRIO Functional Description Table 17. RX Buffer Descriptor Field Descriptions (continued) Field mailbox Although the switch fabric must deliver the segments of multi-packet messages in the order they were sent, buffer resources at the receiving endpoint may only become available after the initial segment(s) of a message have had to be retried.
Page 47: Rx Cppi Mode Explanation
www.ti.com Scenario A - Default Open Switch Retry Scenario B - In order mode Open Switch Retry In addition, multiple messages can be interleaved at the receive port due to ordering within a connected switch’s output queue. This can occur when using a single or multiple priorities. The RX CPPI block must handle simultaneous interleaved multi-segment messages.
Page 48: Cppi Boundary Diagram
SRIO Functional Description Teardown of an Rx queue causes the following actions: If teardown is issued by software during the time when the RX state machine is idle, then the state machine will immediately start the teardown procedure: – If the queue to be torn down is in-message (waiting for one or more segments), then the queue will be torn down and reported with the current buffer descriptor (teardown bit set, ownership bit cleared, CC = 100b).
Page 49: Tx Buffer Descriptor Fields
www.ti.com 2.3.4.2 TX Operation Outgoing messages are handled similarly, with buffer descriptor queues that are assigned by the CPUs. The queues are configured and initialized upon reset. When a CPU wants to send a message to an external RapidIO device, it writes the buffer descriptor information via the configuration bus into the SRAM.
Page 50 SRIO Functional Description Table 20. TX Buffer Descriptor Field Definitions (continued) Field ownership Teardown_Complete retry_count message_length Dest_id Serial RapidIO (SRIO) Description Ownership: Indicates ownership of the message and is valid only on sop. This bit is set by the host and cleared by the port when the message has been transmitted. The host uses this bit to reclaim buffers.
Page 51 www.ti.com Table 20. TX Buffer Descriptor Field Definitions (continued) Field PortID SSIZE mailbox Once the port controls the buffer descriptor, the DEST_ID field can be queried to determine flow control. If the transaction has been flow controlled, the DMA bus READ request is postponed so that the TX buffer space is not wasted.
Page 52: Weighted Round Robin Programming Registers (Address Offset 0X7E0 - 0X7Ec)
SRIO Functional Description Figure 23. Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) TX_QUEUE_CNTL0- Address Offset (0x7E0) TX_Queue_Map3 TX_Queue_Map1 TX_QUEUE_CNTL1- Address Offset (0x7E4) TX_Queue_Map7 TX_Queue_Map5 TX_QUEUE_CNTL2- Address Offset (0x7E8) TX_Queue_Map11 TX_Queue_Map9 TX_QUEUE_CNTL3- Address Offset (0x7EC) TX_Queue_Map15 TX_Queue_Map13 Table 21. Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) Name Access TX_Queue_Map0...
Page 53 www.ti.com Table 21. Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) Name Access TX_Queue_Map10 [23:16] TX_Queue_Map11 [31:24] TX_Queue_Map12 [7:0] TX_Queue_Map13 [15:8] TX_Queue_Map14 [23:16] TX_Queue_Map15 [31:24] The TX queues are treated differently than the RX queues. A TX queue can mix single and multi-segment message buffer descriptors.
Page 54 SRIO Functional Description Essentially, instead of the 24-bit value representing the period of the response timer, the period is now defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 – 89.5Mhz for a 6 –...
Page 55 www.ti.com The CPPI module can be powered down if the message passing protocol is not being supported in the application. For example, if the direct I/O protocol is being used for data transfers, powering down the CPPI module will save power. In this situation, the buffer descriptor queue SRAMs and mailbox mapper logic should be powered down.
Page 56: Queue Mapping
SRIO Functional Description This value is compared against the port written value in the TX DMA State CP register, if equal, the interrupt is deasserted. Initialization Example SRIO_REGS->Queue0_RXDMA_HDP SRIO_REGS->Queue1_RXDMA_HDP SRIO_REGS->Queue2_RXDMA_HDP SRIO_REGS->Queue3_RXDMA_HDP SRIO_REGS->Queue4_RXDMA_HDP SRIO_REGS->Queue5_RXDMA_HDP SRIO_REGS->Queue6_RXDMA_HDP SRIO_REGS->Queue7_RXDMA_HDP SRIO_REGS->Queue8_RXDMA_HDP SRIO_REGS->Queue9_RXDMA_HDP SRIO_REGS->Queue10_RXDMA_HDP SRIO_REGS->Queue11_RXDMA_HDP SRIO_REGS->Queue12_RXDMA_HDP SRIO_REGS->Queue13_RXDMA_HDP SRIO_REGS->Queue14_RXDMA_HDP SRIO_REGS->Queue15_RXDMA_HDP...
Page 57: Rx Buffer Descriptor
www.ti.com Descriptor Descriptor TX Buffer Descriptor TX_DESCP0_0->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER,(int )TX_DESCP0_1 ); //link to TX_DESCP0_1 //NDP TX_DESCP0_0->TXDESC1 = CSL_FMK( SRIO_TXDESC1_B_POINTER,(int )&xmtBuff1[0] ); //Buffer Pointer TX_DESCP0_0->TXDESC2 = CSL_FMK( SRIO_TXDESC2_DESTID, 0xBEEF)| CSL_FMK( SRIO_TXDESC2_PRI, 1)| CSL_FMK( SRIO_TXDESC2_TT, 1)| CSL_FMK( SRIO_TXDESC2_PORTID, 3)| CSL_FMK( SRIO_TXDESC2_SSIZE, SSIZE_256B)| CSL_FMK( SRIO_TXDESC2_MAILBOX, 0);...
Page 58: Maintenance
SRIO Functional Description Descriptor Descriptor Start Message Passing SRIO_REGS->Queue0_RXDMA_HDP SRIO_REGS->Queue0_TxDMA_HDP 2.3.5 Maintenance The type 8 MAINTENANCE packet format accesses the RapidIO capability registers (CARs), command and status registers (CSRs), and data structures. Unlike other request formats, the type 8 packet format serves as both the request and the response format for maintenance operations.
Page 59: Doorbell Operation
www.ti.com 2.3.6 Doorbell The doorbell operation, consisting of the DOORBELL and RESPONSE transactions (typically a DONE response), as shown in Figure another processing element through the interconnect fabric. The DOORBELL transaction contains the info field to hold information and does not have a data payload. This field is software-defined and can be used for any desired purpose;...
Page 60 SRIO Functional Description 2.3.7 Congestion Control The RapidIO Flow Control specification is referenced in and implementation of congestion control within the peripheral. The peripheral is notified of switch fabric congestion through type 7 RapidIO packets. The packets are referred to as Congestion Control Packets (CCPs). The purpose of these packets is to turn off (Xoff), or turn on (Xon) specific flows defined by DESTID and PRIORITY of outgoing packets.
Page 61: Flow Control Table Entry Registers (Address Offset 0X0900 - 0X093C)
www.ti.com Figure 27. Flow Control Table Entry Registers (Address Offset 0x0900 - 0x093C) RIO_FLOW_CNTL0 RIO_FLOW_CNTL1 RIO_FLOW_CNTL2 RIO_FLOW_CNTL15 Table 22. Flow Control Table Entry Registers (Address Offset 0x0900 - 0x093C) Name Access [17:16] Flow_Cntl_ID0 [15:0] Flow_Cntl_ID1 [15:0] Flow_Cntl_ID2 [15:0] Flow_Cntl_ID3 [15:0] Flow_Cntl_ID4 [15:0] Flow_Cntl_ID5...
Page 62: Transmit Source Flow Control Masks
SRIO Functional Description Figure 28. Transmit Source Flow Control Masks 31-16 RIO_LSUn_FLOW_MASKS Reserved (Address Offsets: 0x041C, 0x043C, 0x045C, 0x047C) R, 0x0000 31-16 RIO_TX_CPPI_FLOW_MASKS0 TX Queue1 Flow Mask (Address Offsets: 0x0704) R/W, 0xFFFF 31-16 TX Queue3 RIO_TX_CPPI_FLOW_MASKS1 (Address Offsets: 0x0708) Flow Mask R/W, 0xFFFF 31-16 RIO_TX_CPPI_FLOW_MASKS2...
Page 63: Configuration Bus Example
www.ti.com 2.3.8 Endianness RapidIO is based on big endian. This is discussed in detail in section 2.4 of the RapidIO Interconnect specification. Essentially, big endian specifies the address ordering as the most significant bit/byte first. For example, in the 29-bit address field of a RapidIO packet (shown in transmitted first in the serial bit stream is the MSB of the address.
Page 64: Dma Example
SRIO Functional Description DMA Example The desired operation is to send a Type 8 maintenance request to an external device. The goal is to read 16B of RapidIO MMR from an external device, starting offset 0x0000. This operation involves the LSU block and utilizes the DMA for transferring the response packet payload.
Page 65: Gbl_En (Address 0X0030)
www.ti.com 2.3.9.1 Reset Summary After reset, the state of the peripheral depends on the default register values and the BLKn_EN_INIT tieoff values. You can also perform a hard reset using the software of each logical block within the peripheral via the GBL_EN and BLKn_EN bits.
Page 66: Blk0_En_Stat (Address 0X003C)
SRIO Functional Description LEGEND: R = Read, W = Write, n = value at reset LEGEND: R = Read, W = Write, n = value at reset LEGEND: R = Read, W = Write, n = value at reset LEGEND: R = Read, W = Write, n = value at reset LEGEND: R = Read, W = Write, n = value at reset Table 24.
Page 67 www.ti.com Table 24. Enable and Enable Status Bit Field Descriptions (continued) Name BLK1_EN BLK1_EN_STAT BLK2_EN BLK2_EN_STAT BLK3_EN BLK3_EN_STAT BLK4_EN BLK4_EN_STAT BLK5_EN BLK5_EN_STAT BLK6_EN BLK6_EN_STAT BLK7_EN BLK7_EN_STAT BLK8_EN SPRU976 – March 2006 Submit Documentation Feedback Access Description Controls reset to logical block 1, which is the LSU. 0 = Logical block 1 disabled (held in reset, clocks disabled) 1 = Logical block 1 enabled Indicates state of BLK1_EN reset signal.
Page 68: Emulation Control (Peripheral Control Register Pcr 0X0004)
SRIO Functional Description Table 24. Enable and Enable Status Bit Field Descriptions (continued) Name BLK8_EN_STAT The GBL_EN register is implemented with a single ENABLE bit. This bit is logically ORd with the reset input to the module and is fanned out to all logical blocks within the peripheral. 2.3.9.3 Software Shutdown Details Power consumption must be minimized for all logical blocks that are in shutdown.
Page 69: Emulation Control Signals
www.ti.com Name Access Free Soft PEREN Reserved 31:3 Free Run Mode: (default mode) Peripheral does not respond to EMUSUSP assertion. Module functions normally, irrespective of CPU emulation state. Soft Stop Mode: Peripheral gracefully halts operations. The peripheral halts operation at a point that makes sense both to the internal DMA/data access operation and to the pin interface as described below, after finishing packet reception or transmission in progress: DMA bus DMA master: DMA bus requests in progress are allowed to complete (DMA bus has no...
Page 70 SRIO Functional Description 2.3.11.2 PLL, Ports, Device ID and Data Rate Initializations For example, Enable pll, 333MHz, 4p1x, x20. 3.125 Gbps, full rate, ½ rate, ¼ rate: if (srio4p1x_mode){ rdata = SRIO_REGS->PER_SET_CNTL; wdata = 0x0000014F; 4p1x mask = 0x000001FF; mdata = (wdata & mask) | (rdata & ~mask); SRIO_REGS->PER_SET_CNTL = mdata ;...
Page 71 www.ti.com else{ SRIO_REGS->SP_IP_MODE = 0x04000000; // Jadis mltc/rst/pw enable, clear SRIO_REGS->IP_PRESCAL SRIO_REGS->SP0_SILENCE_TIMER = 0x20000000; SRIO_REGS->SP1_SILENCE_TIMER = 0x20000000; SRIO_REGS->SP2_SILENCE_TIMER = 0x20000000; SRIO_REGS->SP3_SILENCE_TIMER = 0x20000000; SRIO_REGS->PER_SET_CNTL SRIO_REGS->SP_LT_CTL SRIO_REGS->SP_RT_CTL SRIO_REGS->SP_GEN_CTL SRIO_REGS->SP0_CTL SRIO_REGS->SP1_CTL SRIO_REGS->SP2_CTL SRIO_REGS->SP3_CTL SRIO_REGS->ERR_RPT_BH SRIO_REGS->ERR_DET SRIO_REGS->ERR_EN SRIO_REGS->H_ADDR_CAPT SRIO_REGS->ADDR_CAPT SRIO_REGS->ID_CAPT SRIO_REGS->CTRL_CAPT SRIO_REGS->SP_IP_MODE SRIO_REGS->SP_IP_PW_IN_CAPT0 = 0x00000000 ; // clear SRIO_REGS->SP_IP_PW_IN_CAPT1 = 0x00000000 ;...
Page 72: Bootload Operation
SRIO Functional Description 2.3.12 Bootload Capability 2.3.12.1 Configuration It is assumed that an external device will initiate the bootload data transfer and master the DMA interface. Upon reset, the following sequence of events must occur: 1. DSP is placed in SRIO boot mode by HW mode pins. 2.
Page 73: Logical/Transport Error Handling And Logging
www.ti.com Logical/Transport Error Handling and Logging Error management registers allow detection and logging of logical/transport layer errors. illustrates the detectable errors. IO ERR Rspns Msg ERR Rspns GSM ERR Rspns ERR MSG Format ILL Trans Decode R/W0c, 0b R/W0c, 0b PKT Rspns Unsolicited Rspns Timeout...
Page 74: Interrupt Conditions
Interrupt Conditions Interrupt Conditions This section defines the CPU interrupt capabilities and requirements of the peripheral. CPU Interrupts The following interrupts are supported by the RIO peripheral. Error Status: Event indicating that a run-time error was reached. The CPU should reset/resynchronize the peripheral.
Page 75: Interrupt Condition Control Registers
www.ti.com The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers. Each bit can be assigned to any core as described by the Interrupt Condition Routing Registers. Additionally, each status bit is user-defined for the application.
Page 76: Doorbell0 Interrupt Registers For Direct I/O Transfers
Interrupt Conditions Table 26. Interrupt Source Configuration Options Field Access Reset Value ICSx ICCx Figure 43. DOORBELL0 Interrupt Registers for Direct I/O Transfers DOORBELL0 Interrupt Condition Status Registers (ICSR) (Address Offset 0x0200) ICS15 ICS14 ICS13 ICS12 ICS11 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value at reset...
Page 77: Doorbell2 Interrupt Registers For Direct I/O Transfers
www.ti.com Where ICS0 - Doorbell1, bit 0, through ICS15 - Doorbell1, bit 15. Figure 45. DOORBELL2 Interrupt Registers for Direct I/O Transfers DOORBELL2 Interrupt Condition Status Registers (ICSR) (Address Offset 0x0220) ICS15 ICS14 ICS13 ICS12 ICS11 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value at reset DOORBELL2 Interrupt Condition Clear Registers (ICCR) (Address Offset 0x0228)
Page 78: Rx_Cppi Interrupts Using Messaging Mode Data Transfers
Interrupt Conditions Figure 47. RX_CPPI Interrupts Using Messaging Mode Data Transfers RX_CPPI Interrupt Condition Status Registers (ICSR) (Address Offset 0x0240) ICS15 ICS14 ICS13 ICS12 ICS11 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value at reset RX_CPPI Interrupt Condition Clear Registers (ICCR) (Address Offset 0x0248) ICC15 ICC14...
Page 79: Lsu Load/Store Module Interrupts
www.ti.com Where ICS0 - TX CPPI interrupt, buffer descriptor queue 0, through ICS15 - TX CPPI interrupt, buffer descriptor queue 15. Clearing of any ICSR bit is dependent on the CPU writing to the TX DMA State CP. The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value.
Page 80: Err_Rst_Evnt Error, Reset, And Special Event Interrupt
Interrupt Conditions Bit 21- Transaction was not sent due to DMA data transfer error, LSU3 Bit 22- Retry Doorbell response received or Atomic Test-and-swap was not allowed (semaphore in use), LSU3 Bit 23- Packet not sent due to unavailable outbound credit at given priority, LSU3 Bit 24- Transaction complete, No Errors (Posted/Non-posted), LSU4 –...
Page 81: Doorbell 0 Interrupt Condition Routing Registers
www.ti.com The interrupt conditions are programmable to select the interrupt output that will be driven. Each condition is independently programmable to use any of the interrupt destinations supported by the device. For example, a quad core device may support four CPU servicing interrupt destinations, one per core (INTDST0 for Core0, INTDST1 for Core1, INTDST2 for Core2, and INTDST3 for Core3).
Page 82: Load/Store Module Interrupt Condition Routing Registers
Interrupt Conditions Figure 52. Load/Store Module Interrupt Condition Routing Registers ICR7 R/W-0000 ICR3 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset ICR15 R/W-0000 ICR11 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset ICR23 R/W-0000 ICR19...
Page 83: Interrupt Status Decode Registers
www.ti.com Figure 53. Error, Reset, and Special Event Interrupt Condition Routing Registers ERR_RST_EVNT_ICRR (Address Offset 0x02F0) Reserved LEGEND: R = Read, W = Write, n = value at reset ERR_RST_EVNT_ICRR2 (Address Offset 0x02F4) ICR11 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset ERR_RST_EVNT_ICRR3 (Address Offset 0x02F8) LEGEND: R = Read, W = Write, n = value at reset Interrupt Status Decode Registers...
Page 84: Example Diagram Of Interrupt Status Decode Register Mapping
Interrupt Conditions ISDR bits: ISDR bits: As an example, if bit 29 of the ISDR is set, this indicates that there is a pending interrupt on either the TX CPPI queue 2 or RX CPPI queue 2. Figure 55. Example Diagram of Interrupt Status Decode Register Mapping TX CPPI ICRR TX CPPI ICSR TX CPPI ICRR...
Page 85: Interrupt Generation
www.ti.com LSU bits within the ICSR are logically grouped for a given core and ORd together into a single bit of the decode register. Similarly, the Error/Reset/Special event bits within the ICSR are ORd together into a single bit of the decode register. When either of these bits are set in the decode register, the CPU must make additional reads to the corresponding ICSRs to determine that exact interrupt source.
Page 86: Interrupt Handling
Interrupt Conditions Figure 57. INTDSTn_RATE_CNTL Interrupt Rate Control Register LEGEND: R = Read, W = Write, n = value at reset Offsets: INTDST0 – 0x0320 INTDST1 – 0x0324 INTDST2 – 0x0328 INTDST3 – 0x032C INTDST4 – 0x0330 INTDST5 – 0x0334 INTDST6 –...
Page 87 www.ti.com interruptStatus[11] = SRIO_REGS->ERR_RST_EVNT_ICSR; interruptStatus[12] = SRIO_REGS->ERR_RST_EVNT_ICCR; SRIO_REGS->DOORBELL0_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL1_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL2_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL3_ICCR=0xFFFFFFFF; SRIO_REGS->INTDST0_Rate_CNTL=1; SRIO_REGS->LSU_ICCR = 0xFFFF; SRIO_REGS->INTDST1_Rate_CNTL = 1; SPRU976 – March 2006 Submit Documentation Feedback Interrupt Conditions Serial RapidIO (SRIO)
Page 88: Srio Registers
SRIO Registers SRIO Registers Introduction Table 28 lists the memory-mapped registers for the Serial Rapid IO (SRIO). See the device-specific data manual for the memory address of these registers. Offset Acronym 0x0000 0x0004 0x0020 PER_SET_CNTL 0x0030 GBL_EN 0x0034 GBL_EN_STAT 0x0038 BLK0_EN 0x003C BLK0_EN_STAT...
Page 89 www.ti.com Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x0110 SERDES_CFGTX0_ CNTL 0x0114 SERDES_CFGTX1_ CNTL 0x0118 SERDES_CFGTX2_ CNTL 0x011C SERDES_CFGTX3_ CNTL 0x0120 SERDES_CFG0_CN 0x0124 SERDES_CFG1_CN 0x0128 SERDES_CFG2_CN 0x012C SERDES_CFG3_CN 0x0200 DOORBELL0_ICSR 0x0208 DOORBELL0_ICCR 0x0210 DOORBELL1_ICSR 0x0218 DOORBELL1_ICCR 0x0220 DOORBELL2_ICSR 0x0228 DOORBELL2_ICCR...
Page 90 SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x02EC LSU_ICRR3 0x02F0 ERR_RST_EVNT_IC 0x02F4 ERR_RST_EVNT_IC 0x02F8 ERR_RST_EVNT_IC 0x0300 INTDST0_DECODE 0x0304 INTDST1_DECODE 0x0308 INTDST2_DECODE 0x030C INTDST3_DECODE 0x0310 INTDST4_DECODE 0x0314 INTDST5_DECODE 0x0318 INTDST6_DECODE 0x031C INTDST7_DECODE 0x0320 INTDST0_RATE_CN 0x0324 INTDST1_RATE_CN 0x0328 INTDST2_RATE_CN 0x032C...
Page 91 www.ti.com Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x0444 LSU3_REG1 0x0448 LSU3_REG2 0x044C LSU3_REG3 0x0450 LSU3_REG4 0x0454 LSU3_REG5 0x0458 LSU3_REG6 0x045C LSU3_FLOW_MASK 0x0460 LSU4_REG0 0x0464 LSU4_REG1 0x0468 LSU4_REG2 0x046C LSU4_REG3 0x0470 LSU4_REG4 0x0474 LSU4_REG5 0x0478 LSU4_REG6 0x047C LSU4_FLOW_MASK 0x0500 QUEUE0_TXDMA_H...
Page 92 SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x0584 QUEUE1_TXDMA_C 0x0588 QUEUE2_TXDMA_C 0x058C QUEUE3_TXDMA_C 0x0590 QUEUE4_TXDMA_C 0x0594 QUEUE5_TXDMA_C 0x0598 QUEUE6_TXDMA_C 0x059C QUEUE7_TXDMA_C 0x05A0 QUEUE8_TXDMA_C 0x05A4 QUEUE9_TXDMA_C 0x05A8 QUEUE10_TXDMA_ 0x05AC QUEUE11_TXDMA_ 0x05B0 QUEUE12_TXDMA_ 0x05B4 QUEUE13_TXDMA_ 0x05B8 QUEUE14_TXDMA_ 0x05BC QUEUE15_TXDMA_ 0x0600...
Page 93 www.ti.com Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x0630 QUEUE12_RXDMA_ 0x0634 QUEUE13_RXDMA_ 0x0638 QUEUE14_RXDMA_ 0x063C QUEUE15_RXDMA_ 0x0680 QUEUE0_RXDMA_C Queue Receive DMA Completion Pointer Register 0 0x0684 QUEUE1_RXDMA_C Queue Receive DMA Completion Pointer Register 1 0x0688 QUEUE2_RXDMA_C Queue Receive DMA Completion Pointer Register 2 0x068C QUEUE3_RXDMA_C Queue Receive DMA Completion Pointer Register 3 0x0690...
Page 94 SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x071C TX_CPPI_FLOW_MA Transmit CPPI Supported Flow Mask Register 6 SKS6 0x0720 TX_CPPI_FLOW_MA Transmit CPPI Supported Flow Mask Register 7 SKS7 0x0740 RX_QUEUE_TEAR_ DOWN 0x0744 RX_CPPI_CNTL 0x07E0 TX_QUEUE_CNTL0 0x07E4 TX_QUEUE_CNTL1 0x07E8 TX_QUEUE_CNTL2...
Page 95 www.ti.com Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x0890 RXU_MAP_L18 0x0894 RXU_MAP_H18 0x0898 RXU_MAP_L19 0x089C RXU_MAP_H19 0x08A0 RXU_MAP_L20 0x08A4 RXU_MAP_H20 0x08A8 RXU_MAP_L21 0x08AC RXU_MAP_H21 0x08B0 RXU_MAP_L22 0x08B4 RXU_MAP_H22 0x08B8 RXU_MAP_L23 0x08BC RXU_MAP_H23 0x08C0 RXU_MAP_L24 0x08C4 RXU_MAP_H24 0x08C8 RXU_MAP_L25 0x08CC RXU_MAP_H25...
Page 96 SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x1008 ASBLY_ID 0x100C ASBLY_INFO 0x1010 PE_FEAT 0x1018 SRC_OP 0x101C DEST_OP 0x104C PE_LL_CTL 0x1058 LCL_CFG_HBAR 0x105C LCL_CFG_BAR 0x1060 BASE_ID 0x1068 HOST_BASE_ID_LO 0x106C COMP_TAG 0x1100 SP_MB_HEAD 0x1120 SP_LT_CTL 0x1124 SP_RT_CTL 0x113C SP_GEN_CTL 0x1140...
Page 97 www.ti.com Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x2048 SP0_ERR_ATTR_CA Port 0 Attributes Error Capture CSR 0 PT_DBG0 0x204C SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Error Capture CSR 1 0x2050 SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Error Capture CSR 2 0x2054 SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Error Capture CSR 3 0x2058...
Page 98 SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x2128 SP3_ERR_RATE 0x212C SP3_ERR_THRESH 0x12000 SP_IP_DISCOVERY _TIMER 0x12004 SP_IP_MODE 0x12008 IP_PRESCAL 0x12010 SP_IP_PW_IN_CAPT Port-Write-In Capture CSR Register 0 0x12014 SP_IP_PW_IN_CAPT Port-Write-In Capture CSR Register 1 0x12018 SP_IP_PW_IN_CAPT Port-Write-In Capture CSR Register 2 0x1201C SP_IP_PW_IN_CAPT Port-Write-In Capture CSR Register 3 0x14000...
Page 99: Peripheral Identification Register (Pid)
www.ti.com Peripheral Identification Register (PID) The peripheral identification register (PID) is a constant register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral. All bits within this register are read-only (writes have no effect) meaning that the values within this register should be hard-coded with the appropriate values and must not change from their reset state.
Page 100: Peripheral Control Register (Pcr)
SRIO Registers Peripheral Control Register (PCR) The peripheral control register (PCR) contains a bit that enables or disables the entire peripheral and one bit for every module within the peripheral where this level of control is desired. The module control bits can only be written when the peripheral itself is enabled.
Page 101: Peripheral Settings Control Register (Per_Set_Cntl)
www.ti.com Peripheral Settings Control Register (PER_SET_CNTL) Figure 60. Peripheral Settings Control Register (PER_SET_CNTL) 31-27 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 14-12 TX_P TX_PRI0_WM CBA_TRANS_PRI RI1_W RW-0x03 0x02 LEGEND: R = Read only; -n = value after reset Table 31.
Page 102 SRIO Registers Table 31. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Field Value Description 17-15 TX_PRI1_WM Transmit credit threshold. Sets the required number of logical layer TX buffers needed to send priority 1 packets across the UDI interface. This is valid for all ports in 1X mode only. Required buffer count for transmit credit threshold 1 value TX_PRI1_WM: 000 8, 7, 6, 5, 4, 3, 2, 1 001 8, 7, 6, 5, 4, 3, 2...
Page 103 www.ti.com Table 31. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Field Value Description ENPLL3 Drives SERDES Macro 3 PLL Enable signal Disables macro 3 PLL Enables macro 3 PLL ENPLL2 Drives SERDES Macro 2 PLL Enable signal Disables macro 2 PLL Enables macro 2 PLL ENPLL1 Drives SERDES Macro 1 PLL Enable signal...
Page 104: Peripheral Global Enable Register (Gbl_En)
SRIO Registers Peripheral Global Enable Register (GBL_EN) Figure 61. Peripheral Global Enable Register (GBL_EN) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 32. Peripheral Global Enable Register (GBL_EN) Field Descriptions Field Value Description...
Page 105: Peripheral Global Enable Status Register (Gbl_En_Stat)
www.ti.com Peripheral Global Enable Status Register (GBL_EN_STAT) Figure 62. Peripheral Global Enable Status Register (GBL_EN_STAT) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 33. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions Field Value Description...
Page 106: Block N Enable Register (Blkn_En)
SRIO Registers Block n Enable Register (BLKn_EN) There are nine of these registers, one for each of nine logical blocks in the peripheral. LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 34.
Page 107: Block N Enable Status Register (Blkn_En_Stat)
www.ti.com Block n Enable Status Register (BLKn_EN_STAT) There are nine of these registers, one for each of nine logical blocks in the peripheral. Figure 64. Block n Enable Status Register (BLKn_EN_STAT) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 108: Rapidio Deviceid1 Register (Deviceid_Reg1)
SRIO Registers RapidIO DEVICEID1 Register (DEVICEID_REG1) Figure 65. RapidIO DEVICEID1 Register (DEVICEID_REG1) 31-24 Reserved R-0x0000 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 36. RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions Field Value Description...
Page 109: Rapidio Deviceid2 Register (Deviceid_Reg2)
www.ti.com 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) Figure 66. RapidIO DEVICEID2 Register (DEVICEID_REG2) 31-24 Reserved R-0x0000 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 37. RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions Field Value Description...
Page 110: Packet Forwarding Register N For 16B Deviceids (Pf_16B_Cntln)
SRIO Registers 5.11 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTLn) There are four of these registers, to support four ports. Figure 67. Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTLn) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 111: Packet Forwarding Register N For 8B Deviceids (Pf_8B_Cntln)
www.ti.com 5.12 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTLn) There are four of these registers, to support four ports. Figure 68. Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTLn) LEGEND: R = Read only; -n = value after reset 15-8 8BIT_DEVID_UP_BOUND RW-0xFF...
Page 112: Serdes Receive Channel Configuration Registers N (Serdes_Cfgrxn_Cntl)
SRIO Registers 5.13 SERDES Receive Channel Configuration Registers n (SERDES_CFGRXn_CNTL) There are four of these registers, to support four ports. Figure 69. SERDES Receive Channel Configuration Registers n (SERDES_CFGRXn_CNTL) Reserved ALIGN Reserv R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value at reset Table 40.
Page 113: Eq Bits
www.ti.com Table 40. SERDES Receive Channel Configuration Registers n (SERDES_CFGRXn_CNTL) Field Field Value Description Reserved Reserved. 10:8 TERM Termination. Selects input termination options suitable for a variety of AC or DC coupled scenarios. Common point connected to VDDT. This configuration is for DC coupled systems using CML transmitters.
Page 114: Serdes Transmit Channel Configuration Registers N (Serdes_Cfgtxn_Cntl)
SRIO Registers 5.14 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTXn_CNTL) There are four of these registers, to support four ports. Figure 70. SERDES Transmit Channel Configuration Registers n (SERDES_CFGTXn_CNTL) R/W-0 LEGEND: R = Read, W = Write, n = value at reset Table 42.
Page 115: Swing Bits
www.ti.com CFGTX[11:9] CFGTX[15:12] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SPRU976 – March 2006 Submit Documentation Feedback Table 43. SWING Bits Amplitude (mV dfpp 1000 1125 1250 Table 44. DE Bits Amplitude Reduction 4.76 -0.42...
Page 116: Serdes Macro Configuration Register N (Serdes_Cfgn_Cntl)
SRIO Registers 5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) There are four of these registers, to support four ports. Figure 71. SERDES Macros CFG (0-3) Registers (SERDES_CFGn_CNTL) Reserved LEGEND: R = Read, W = Write, n = value at reset Table 45.
Page 117: Doorbelln Interrupt Status Register (Doorbelln_Icsr)
www.ti.com 5.16 DOORBELLn Interrupt Status Register (DOORBELLn_ICSR) Each of the four doorbells is supported by a register of this type. Figure 72. DOORBELLn Interrupt Status Register (DOORBELLn_ICSR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 46.
Page 118: Doorbelln Interrupt Clear Register (Doorbelln_Iccr)
SRIO Registers 5.17 DOORBELLn Interrupt Clear Register (DOORBELLn_ICCR) Each of the four doorbells is supported by a register of this type. Figure 73. DOORBELLn Interrupt Clear Register (DOORBELLn_ICCR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 47.
Page 119: Rx Cppi Interrupt Status Register (Rx_Cppi_Icsr)
www.ti.com 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Figure 74. RX CPPI Interrupt Status Register (RX_CPPI_ICSR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 48. RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Field Descriptions Field Value Description...
Page 120: Rx Cppi Interrupt Clear Register (Rx_Cppi_Iccr)
SRIO Registers 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Figure 75. RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 49. RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Field Descriptions Field Value Description...
Page 121: Tx Cppi Interrupt Status Register (Tx_Cppi_Icsr)
www.ti.com 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Figure 76. TX CPPI Interrupt Status Register (TX_CPPI_ICSR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 50. TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions Field Value Description...
Page 122: Tx Cppi Interrupt Clear Register (Tx_Cppi_Iccr)
SRIO Registers 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Figure 77. TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 51. TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions Field Value Description...
Page 123: Lsu Status Interrupt Register (Lsu_Icsr)
www.ti.com 5.22 LSU Status Interrupt Register (LSU_ICSR) Figure 78. LSU Status Interrupt Register (LSU_ICSR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 52. LSU Status Interrupt Register (LSU_ICSR) Field Descriptions Field Value Description...
Page 124: Lsu Clear Interrupt Register (Lsu
SRIO Registers 5.23 LSU Clear Interrupt Register (LSU _ICCR) Figure 79. LSU Clear Interrupt Register (LSU _ICCR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 53. LSU Clear Interrupt Register (LSU _ICCR) Field Descriptions Field Value Description...
Page 125: Error, Reset, And Special Event Status Interrupt Register (Err_Rst_Evnt_Icsr)
www.ti.com 5.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) Figure 80. Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) LEGEND: R = Read only; -n = value after reset 15-12 Reserved ICS11 R-0x00 R/W- 0x00 LEGEND: R = Read only; -n = value after reset Table 54.
Page 126: Error, Reset, And Special Event Clear Interrupt Register (Err_Rst_Evnt_Iccr)
SRIO Registers 5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) Figure 81. Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) LEGEND: R = Read only; -n = value after reset 15-12 Reserved ICC11 R-0x00 0x00 LEGEND: R = Read only; -n = value after reset Table 55.
Page 127: Doorbelln Interrupt Condition Routing Register (Doorbelln_Icrr)
www.ti.com 5.26 DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) Each of the four doorbells is supported by a register of this type. Figure 82. DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) ICR7 R/W-0x00 ICR3 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 56.
Page 128: Doorbelln Interrupt Condition Routing Register 2 (Doorbelln_Icrr2)
SRIO Registers 5.27 DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) Each of the four doorbells is supported by a register of this type. Figure 83. DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) ICR15 R/W-0x00 ICR11 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 57.
Page 129: Rx Cppi Interrupt Condition Routing Register (Rx_Cppi
www.ti.com 5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) Figure 84. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) ICR7 R/W-0x00 ICR3 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 58. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) Field Descriptions Field Value Description...
Page 130: Rx Cppi Interrupt Condition Routing Register (Rx_Cppi
SRIO Registers 5.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) Figure 85. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) ICR15 R/W-0x00 ICR11 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 131: Tx Cppi Interrupt Condition Routing Register (Tx_Cppi
www.ti.com 5.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) Figure 86. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) ICR7 R/W-0x00 ICR3 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 60. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) Field Descriptions Field Value Description...
Page 132: Tx Cppi Interrupt Condition Routing Register (Tx_Cppi
SRIO Registers 5.31 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) Figure 87. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) ICR15 R/W-0x00 ICR11 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 61. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) Field Descriptions Field Value Description...
Page 133: Lsu Module Interrupt Condition Routing Register 0 (Lsu_Icrr0)
www.ti.com 5.32 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) Figure 88. LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) ICR7 R/W-0000 ICR3 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset Table 62. LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) Field Descriptions Field Value Description...
Page 134: Lsu Module Interrupt Condition Routing Register 1 (Lsu_Icrr1)
SRIO Registers 5.33 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) Figure 89. LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) ICR15 R/W-0000 ICR11 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset Table 63. LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) Field Descriptions Field Value Description...
Page 135: Lsu Module Interrupt Condition Routing Register 2 (Lsu_Icrr2)
www.ti.com 5.34 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) Figure 90. LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) ICR23 R/W-0000 ICR19 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset Table 64. LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) Field Descriptions Field Value Description...
Page 136: Lsu Module Interrupt Condition Routing Register 3 (Lsu_Icrr3)
SRIO Registers 5.35 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) Figure 91. LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) ICR31 R/W-0000 ICR27 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset Table 65. LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) Field Descriptions Field Value Description...
Page 137: Error, Reset, And Special Event Interrupt Condition Routing Register (Err_Rst_Evnt_Icrr)
www.ti.com 5.36 Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) Figure 92. Error, Reset, and Special Event Interrupt Condition Routing Register LEGEND: R = Read only; -n = value after reset 15-12 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 66.
Page 138: (Err_Rst_Evnt_Icrr2)
SRIO Registers 5.37 Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) Figure 93. Error, Reset, and Special Event Interrupt Condition Routing Register 2 LEGEND: R = Read only; -n = value after reset 15-12 ICR11 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 67.
Page 139: (Err_Rst_Evnt_Icrr3)
www.ti.com 5.38 Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3) Figure 94. Error, Reset, and Special Event Interrupt Condition Routing Register 3 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 68.
Page 140: Intdstn Interrupt Status Decode Registers (Intdstn_Decode)
SRIO Registers 5.39 INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE) There are eight of these registers. Figure 95. INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 69.
Page 141: Intdstn Interrupt Rate Control Registers (Intdstn_Rate_Cntl)
www.ti.com 5.40 INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL) There are eight of these registers. Figure 96. INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 70.
Page 142: Lsun Control Register 0 (Lsun_Reg0)
SRIO Registers 5.41 LSUn Control Register 0 (LSUn_REG0) There are four of these registers, one for each LSU. Figure 97. LSUn Control Register 0 (LSUn_REG0) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 71.
Page 143: Lsun Control Register 1 (Lsun_Reg1)
www.ti.com 5.42 LSUn Control Register 1 (LSUn_REG1) There are four of these registers, one for each LSU. Figure 98. LSUn Control Register 1 (LSUn_REG1) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 72.
Page 144: Lsun Control Register 2 (Lsun_Reg2)
SRIO Registers 5.43 LSUn Control Register 2 (LSUn_REG2) There are four of these registers, one for each LSU. Figure 99. LSUn Control Register 2 (LSUn_REG2) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 73.
Page 145: Lsun Control Register 3 (Lsun_Reg3)
www.ti.com 5.44 LSUn Control Register 3 (LSUn_REG3) There are four of these registers, one for each LSU. Figure 100. LSUn Control Register 3 (LSUn_REG3) LEGEND: R = Read only; -n = value after reset 15-12 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 74.
Page 146: Lsun Control Register 4 (Lsun_Reg4)
SRIO Registers 5.45 LSUn Control Register 4 (LSUn_REG4) There are four of these registers, one for each LSU. Figure 101. LSUn Control Register 4 (LSUn_REG4) 31-30 29-28 27-26 OUTPORTID PRIORITY XAMBS RW-0x00 RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset 15-8 DESTID RW-0x00...
Page 147: Lsun Control Register 5 (Lsun_Reg5)
www.ti.com 5.46 LSUn Control Register 5 (LSUn_REG5) There are four of these registers, one for each LSU. Figure 102. LSUn Control Register 5 (LSUn_REG5) LEGEND: R = Read only; -n = value after reset 15-8 HOP_COUNT RW-0x00 LEGEND: R = Read only; -n = value after reset Table 76.
Page 148: Lsun Control Register 6 (Lsun_Reg6)
SRIO Registers 5.47 LSUn Control Register 6 (LSUn_REG6) There are four of these registers, one for each LSU. Figure 103. LSUn Control Register 6 (LSUn_REG6) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 77.
Page 149: Lsu Congestion Control Flow Mask N (Lsu_Flow_Masks N)
www.ti.com 5.48 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) Figure 104. LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 78.
Page 150: Queue Transmit Dma Head Descriptor Pointer Registers (Queuen_Txdma_Hdp)
SRIO Registers 5.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) There are sixteen of these registers. Figure 105. Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 79.
Page 151: Queue Transmit Dma Completion Pointer Registers (Queuen_Txdma_Cp)
www.ti.com 5.50 Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) There are sixteen of these registers. Figure 106. Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 80.
Page 152: Queue Receive Dma Head Descriptor Pointer Registers (Queuen_Rxdma_Hdp)
SRIO Registers 5.51 Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP) There are sixteen of these registers. Figure 107. Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 81.
Page 153: Queue Receive Dma Completion Pointer Registers (Queuen_Rxdma_Cp)
www.ti.com 5.52 Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP) There are sixteen of these registers. Figure 108. Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 82.
Page 154: Transmit Queue Teardown Register (Tx_Queue_Tear_Down)
SRIO Registers 5.53 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Figure 109. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) LEGEND: R = Read only; -n = value after reset QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU E15_T E14_T E13_T E12_T E11_T E10_T E9_TE E8_TE E7_TE E6_TE E5_TE E4_TE E3_TE E2_TE E1_TE E0_TE EAR_ EAR_...
Page 155: Transmit Cppi Supported Flow Mask Registers N (Tx_Cppi_Flow_Masksn)
www.ti.com 5.54 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKSn) There are eight registers of this type. See Figure 110. Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKSn) Transmit CPPI Supported Flow Mask Register 0 (TX_CPPI_FLOW_MASKS0) 31-16 QUEUE1_FLOW_MASK RW-0x01 LEGEND: R = Read only; -n = value after reset Transmit CPPI Supported Flow Mask Register 1 (TX_CPPI_FLOW_MASKS1) 31-16 QUEUE3_FLOW_MASK...
Page 156: Transmit Cppi Supported Flow Mask Registers N (Tx_Cppi_Flow_Masksn) Field Descriptions
SRIO Registers Transmit CPPI Supported Flow Mask Register 7 (TX_CPPI_FLOW_MASKS7) 31-16 QUEUE15_FLOW_MASK RW-0x01 LEGEND: R = Read only; -n = value after reset Table 84. Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKSn) Field Field Value Description QUEUEn_FLOW_ Flow mask queue n MASK Transmit source does not support flow n from table entry for QUEUEn Transmit source does support flow n from table entry for QUEUEn...
Page 157: Receive Queue Teardown Register (Rx_Queue_Tear_Down)
www.ti.com 5.55 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Figure 111. Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) LEGEND: R = Read only; -n = value after reset QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU E15_T E14_T E13_T E12_T E11_T E10_T E9_TE E8_TE E7_TE E6_TE E5_TE E4_TE E3_TE E2_TE E1_TE E0_TE EAR_ EAR_...
Page 158: Receive Cppi Control Register (Rx_Cppi_Cntl)
SRIO Registers 5.56 Receive CPPI Control Register (RX_CPPI_CNTL) Figure 112. Receive CPPI Control Register (RX_CPPI_CNTL) LEGEND: R = Read only; -n = value after reset QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU QUEU E15_I E14_I E13_I...
Page 159: Transmit Cppi Weighted Round Robin Control Register 0 (Tx_Queue_Cntl0)
www.ti.com 5.57 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) Figure 113. Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) 31-28 TX_QUEUE_MAP3_NUM_MSG TX_QUEUE_MAP3_QUEUE_PT RW-0x00 LEGEND: R = Read only; -n = value after reset 15-12 TX_QUEUE_MAP1_NUM_MSG TX_QUEUE_MAP1_QUEUE_PT RW-0x00 LEGEND: R = Read only;...
Page 160: Transmit Cppi Weighted Round Robin Control Register 1 (Tx_Queue_Cntl1)
SRIO Registers 5.58 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) Figure 114. Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) 31-28 TX_QUEUE_MAP7_NUM_MSG TX_QUEUE_MAP7_QUEUE_PT RW-0x00 LEGEND: R = Read only; -n = value after reset 15-12 TX_QUEUE_MAP5_NUM_MSG TX_QUEUE_MAP5_QUEUE_PT RW-0x00 LEGEND: R = Read only;...
Page 161: Transmit Cppi Weighted Round Robin Control Register 2 (Tx_Queue_Cntl2)
www.ti.com 5.59 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) Figure 115. Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) 31-28 TX_QUEUE_MAP11_NUM_MSG TX_QUEUE_MAP11_QUEUE_P TX_QUEUE_MAP10_NUM_MSG TX_QUEUE_MAP10_QUEUE_P RW-0x00 LEGEND: R = Read only; -n = value after reset 15-12 TX_QUEUE_MAP9_NUM_MSG TX_QUEUE_MAP9_QUEUE_PT RW-0x00 LEGEND: R = Read only;...
Page 162: Transmit Cppi Weighted Round Robin Control Register 3 (Tx_Queue_Cntl3)
SRIO Registers 5.60 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) Figure 116. Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) 31-28 TX_QUEUE_MAP15_NUM_MSG TX_QUEUE_MAP15_QUEUE_P TX_QUEUE_MAP14_NUM_MSG TX_QUEUE_MAP14_QUEUE_P RW-0x00 LEGEND: R = Read only; -n = value after reset 15-12 TX_QUEUE_MAP13_NUM_MSG TX_QUEUE_MAP13_QUEUE_P TX_QUEUE_MAP12_NUM_MSG TX_QUEUE_MAP12_QUEUE_P RW-0x00 LEGEND: R = Read only;...
Page 163: Mailbox-To-Queue Mapping Register Ln (Rxu_Map_Ln)
www.ti.com 5.61 Mailbox-to-Queue Mapping Register Ln (RXU_MAP_Ln) Figure 117. Mailbox-to-Queue Mapping Register Ln (RXU_MAP_Ln) 31-30 29-24 LETTER_MAS MAILBOX_MASK RW-0x03 RW-0x3F LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 91.
Page 164: Mailbox-To-Queue Mapping Register Hn (Rxu_Map_Hn)
SRIO Registers 5.62 Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Figure 118. Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) LEGEND: R = Read only; -n = value after reset 15-10 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 92. Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Field Descriptions Field Value Description...
Page 165: Flow Control Table Entry Registers (Flow_Cntln)
www.ti.com 5.63 Flow Control Table Entry Registers (FLOW_CNTLn) There are sixteen of these registers. Figure 119. Flow Control Table Entry Registers (FLOW_CNTLn) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 93.
Page 166: Device Identity Car (Dev_Id)
SRIO Registers 5.64 Device Identity CAR (DEV_ID) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 94. Device Identity CAR (DEV_ID) Field Descriptions Field Value Description 31-16 DEVICEIDENTIT Identifies the type of device.
Page 167: Device Information Car (Dev_Info)
www.ti.com 5.65 Device Information CAR (DEV_INFO) Figure 121. Device Information CAR (DEV_INFO) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 95. Device Information CAR (DEV_INFO) Field Descriptions Field Value Description...
Page 168: Assembly Identity Car (Asbly_Id)
SRIO Registers 5.66 Assembly Identity CAR (ASBLY_ID) Figure 122. Assembly Identity CAR (ASBLY_ID) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 96. Assembly Identity CAR (ASBLY_ID) Field Descriptions Field Value Description...
Page 169: Assembly Information Car (Asbly_Info)
www.ti.com 5.67 Assembly Information CAR (ASBLY_INFO) Figure 123. Assembly Information CAR (ASBLY_INFO) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 97. Assembly Information CAR (ASBLY_INFO) Field Descriptions Field Value Description...
Page 170: Processing Element Features Car (Pe_Feat)
SRIO Registers 5.68 Processing Element Features CAR (PE_FEAT) Figure 124. Processing Element Features CAR (PE_FEAT) BRIDG MEMO PROC SWIT ESSO 0x00 0x00 0x01 0x00 LEGEND: R = Read only; -n = value after reset 15-8 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 98.
Page 171: Source Operations Car (Src_Op)
www.ti.com 5.69 Source Operations CAR (SRC_OP) LEGEND: R = Read only; -n = value after reset READ WRIT STRE WRIT DATA AM_W E_WIT _MES RITE H_RE 0x00 0x00 0x00 0x00 0x00 LEGEND: R = Read only; -n = value after reset Table 99.
Page 172: Destination Operations Car (Dest_Op)
SRIO Registers 5.70 Destination Operations CAR (DEST_OP) Figure 126. Destination Operations CAR (DEST_OP) LEGEND: R = Read only; -n = value after reset READ WRIT STRE WRIT DATA AM_W E_WIT _MES RITE H_RE 0x00 0x00 0x00 0x00 0x00 LEGEND: R = Read only; -n = value after reset Table 100.
Page 173: Processing Element Logical Layer Control Csr (Pe_Ll_Ctl)
www.ti.com 5.71 Processing Element Logical Layer Control CSR (PE_LL_CTL) Figure 127. Processing Element Logical Layer Control CSR (PE_LL_CTL) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 101. Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions Field Value Description...
Page 174: Local Configuration Space Base Address 0 Csr (Lcl_Cfg_Hbar) Field Descriptions
SRIO Registers 5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Figure 128. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Reserv 0x00 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 102.
Page 175: Local Configuration Space Base Address 1 Csr (Lcl_Cfg_Bar) Field Descriptions
www.ti.com 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Figure 129. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 103.
Page 176: Base Device Id Csr (Base_Id) Field Descriptions
SRIO Registers 5.74 Base Device ID CSR (BASE_ID) 31-24 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 104. Base Device ID CSR (BASE_ID) Field Descriptions Field Value Description...
Page 177: Host Base Device Id Lock Csr (Host_Base_Id_Lock) Field Descriptions
www.ti.com 5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) See Section 2.4.2 of the RapidIO Specification for description of this register. It provides a lock function that is write-once/reset-able. Figure 131. Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 178: Component Tag Csr (Comp_Tag) Field Descriptions
SRIO Registers 5.76 Component Tag CSR (COMP_TAG) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 106. Component Tag CSR (COMP_TAG) Field Descriptions Field Value Description 31-0 COMPONENT_T Software defined component Tag for PE.
Page 179: X/4X Lp_Serial Port Maintenance Block Header Register (Sp_Mb_Head)
www.ti.com 5.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Figure 133. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 107.
Page 180: Port Link Timeout Control Csr (Sp_Lt_Ctl) Field Descriptions
SRIO Registers 5.78 Port Link Time-Out Control CSR (SP_LT_CTL) Figure 134. Port Link Time-Out Control CSR (SP_LT_CTL) LEGEND: R = Read only; -n = value after reset 15-8 TIMEOUT_VALUE RW-0xFFFFFF LEGEND: R = Read only; -n = value after reset Table 108.
Page 181: Port Response Time-Out Control Csr (Sp_Rt_Ctl) Field Descriptions
www.ti.com 5.79 Port Response Time-Out Control CSR (SP_RT_CTL) Figure 135. Port Response Time-Out Control CSR (SP_RT_CTL) LEGEND: R = Read only; -n = value after reset 15-8 TIMEOUT_VALUE RW-0xFFFFFF LEGEND: R = Read only; -n = value after reset Table 109. Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions Field Value Description...
Page 182: Port General Control Csr (Sp_Gen_Ctl) Field Descriptions
SRIO Registers 5.80 Port General Control CSR (SP_GEN_CTL) Figure 136. Port General Control CSR (SP_GEN_CTL) HOST MAST DISCO ER_E VERE NABL 0x00 0x00 0x00 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 110.
Page 183: Port Link Maintenance Request Csr N (Spn_Lm_Req) Field Descriptions
www.ti.com 5.81 Port Link Maintenance Request CSR n (SPn_LM_REQ) Each of the four ports is supported by a register of this type. Figure 137. Port Link Maintenance Request CSR n (SPn_LM_REQ) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 184: Port Link Maintenance Response Csr N (Spn_Lm_Resp) Field Descriptions
SRIO Registers 5.82 Port Link Maintenance Response CSR n (SPn_LM_RESP) Each of the four ports is supported by a register of this type. Figure 138. Port Link Maintenance Response CSR n (SPn_LM_RESP) RESP ONSE _VALI 0x00 LEGEND: R = Read only; -n = value after reset 15-10 Reserved R-0x00...
Page 185: Port Local Ackid Status Csr N (Spn_Ackid_Stat) Field Descriptions
www.ti.com 5.83 Port Local AckID Status CSR n (SPn_ACKID_STAT) Each of the four ports is supported by a register of this type. Figure 139. Port Local AckID Status CSR n (SPn_ACKID_STAT) 31-29 Reserved INBOUND_ACKID R-0x00 LEGEND: R = Read only; -n = value after reset 15-13 Reserved OUTSTANDING_ACKID...
Page 186: Port Error And Status Csr N (Spn_Err_Stat) Field Descriptions
SRIO Registers 5.84 Port Error and Status CSR n (SPn_ERR_STAT) Each of the four ports is supported by a register of this type. Figure 140. Port Error and Status CSR n (SPn_ERR_STAT) 31-27 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-11 Reserved R-0x00...
Page 187 www.ti.com Table 114. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions (continued) Field Value Description PORT_OK The input and output ports are initialized and the port is exchanging error-free control symbols with the attached device (read-only). PORT_UNINITIA Input and output ports are not initialized. This bit and bit 1 are mutually exclusive (read-only). LIZED SPRU976 –...
Page 188: Port Control Csr N (Spn_Ctl) Field Descriptions
SRIO Registers 5.85 Port Control CSR n (SPn_CTL) Each of the four ports is supported by a register of this type. 31-30 29-27 PORT_WIDTH INITIALIZED_PORT_WI PORT_WIDTH_OVERRI PORT R-0x01 R-0x00 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 115.
Page 189 www.ti.com Table 115. Port Control CSR n (SPn_CTL) Field Descriptions (continued) Field Value Description INPUT_PORT_E Input port receive enable NABLE Port is stopped and only enabled to route or respond I/O logical MAINTENANCE packets, depending upon the functionality of the processing element. Other packets generate packet-not-accepted control symbols to force an error condition to be signaled by the sending device.
Page 190: Error Reporting Block Header (Err_Rpt_Bh) Field Descriptions
SRIO Registers 5.86 Error Reporting Block Header (ERR_RPT_BH) Figure 142. Error Reporting Block Header (ERR_RPT_BH) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 116. Error Reporting Block Header (ERR_RPT_BH) Field Descriptions Field Value Description...
Page 191: Logical/Transport Layer Error Detect Csr (Err_Det) Field Descriptions
www.ti.com 5.87 Logical/Transport Layer Error Detect CSR (ERR_DET) Figure 143. Logical/Transport Layer Error Detect CSR (ERR_DET) IO_ER MSG_ GSM_ ERR_ ILL_T R_RS ERR_ ERR_ MSG_ RANS RSPN RSPN FORM _DEC 0x00 0x00 0x00 0x00 0x00 LEGEND: R = Read only; -n = value after reset 15-8 Reserved R-0x00...
Page 192: Logical/Transport Layer Error Enable Csr (Err_En) Field Descriptions
SRIO Registers 5.88 Logical/Transport Layer Error Enable CSR (ERR_EN) Figure 144. Logical/Transport Layer Error Enable CSR (ERR_EN) IO_ERR_ MSG_E GSM_E ERR_MS RESP_EN RR_RE RR_RE G_FORM ABLE SP_EN SP_EN AT_ENAB ECODE ARGET UT_ENAB ABLE ABLE RW-0x00 RW-0x00 0x00 0x00 LEGEND: R = Read only; -n = value after reset 15-8 Reserved R-0x00...
Page 193: Logical/Transport Layer High Address Capture Csr (H_Addr_Capt) Field Descriptions
www.ti.com 5.89 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Figure 145. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 119. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions Field Value Description...
Page 194: Logical/Transport Layer Address Capture Csr (Addr_Capt) Field Descriptions
SRIO Registers 5.90 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Figure 146. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 120. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions Field Value Description...
Page 195: Logical/Transport Layer Device Id Capture Csr (Id_Capt) Field Descriptions
www.ti.com 5.91 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Figure 147. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) 31-24 MSB_DESTID R-0x00 LEGEND: R = Read only; -n = value after reset 15-8 MSB_SOURCEID R-0x00 LEGEND: R = Read only; -n = value after reset Table 121.
Page 196: Logical/Transport Layer Control Capture Csr (Ctrl_Capt) Field Descriptions
SRIO Registers 5.92 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Figure 148. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) 31-28 FTYPE R-0x00 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 122.
Page 197: Port-Write Target Device Id Csr (Pw_Tgt_Id) Field Descriptions
www.ti.com 5.93 Port-Write Target Device ID CSR (PW_TGT_ID) Figure 149. Port-Write Target Device ID CSR (PW_TGT_ID) 31-24 DEVICEID_MSB RW-0x00 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 123. Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions Field Value Description...
Page 198: Port Error Detect Csr N (Spn_Err_Det) Field Descriptions
SRIO Registers 5.94 Port Error Detect CSR n (SPn_ERR_DET) Each of the four ports is supported by a register of this type. Figure 150. Port Error Detect CSR n (SPn_ERR_DET) 30-24 ERR_I Reserved MP_S PECIF R-0x00 0x00 LEGEND: R = Read only; -n = value after reset 15-6 Reserved R-0x00...
Page 199: Port Error Rate Enable Csr N (Spn_Rate_En) Field Descriptions
www.ti.com 5.95 Port Error Rate Enable CSR n (SPn_RATE_EN) Each of the four ports is supported by a register of this type. Figure 151. Port Error Rate Enable CSR n (SPn_RATE_EN) 30-24 EN_IM Reserved P_SPE CIFIC R-0x00 0x00 LEGEND: R = Read only; -n = value after reset 15-6 Reserved R-0x00...
Page 200: Port N Attributes Error Capture Csr 0 (Spn_Err_Attr_Capt_Dbg0)
SRIO Registers 5.96 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) Each of the four ports is supported by a register of this type. Figure 152. Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) 31-30 INFO_TYPE Reserv ERROR_TYPE R-0x00 0x00 LEGEND: R = Read only;...
Page 201: Port N Packet/Control Symbol Error Capture Csr 1 (Spn_Err_Capt_Dbg1)
www.ti.com 5.97 Port n Packet/Control Symbol Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) Each of the four ports is supported by a register of this type. Figure 153. Port n Packet/Control Symbol Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 202: Port N Packet/Control Symbol Error Capture Csr 2 (Spn_Err_Capt_Dbg2)
SRIO Registers 5.98 Port n Packet/Control Symbol Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) Each of the four ports is supported by a register of this type. Figure 154. Port n Packet/Control Symbol Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 203: Port N Packet/Control Symbol Error Capture Csr 3 (Spn_Err_Capt_Dbg3)
www.ti.com 5.99 Port n Packet/Control Symbol Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) Each of the four ports is supported by a register of this type. Figure 155. Port n Packet/Control Symbol Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 204: Port N Packet/Control Symbol Error Capture Csr 4 (Spn_Err_Capt_Dbg4)
SRIO Registers 5.100 Port n Packet/Control Symbol Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) Each of the four ports is supported by a register of this type. Figure 156. Port n Packet/Control Symbol Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 205: Port Error Rate Csr N (Spn_Err_Rate) Field Descriptions
www.ti.com 5.101 Port Error Rate CSR n (SPn_ERR_RATE) Each of the four ports is supported by a register of this type. Figure 157. Port Error Rate CSR n (SPn_ERR_RATE) 31-24 ERROR_RATE_BIAS RW-0xFF LEGEND: R = Read only; -n = value after reset 15-8 PEAK_ERROR_RATE RW-0x00...
Page 206: Port Error Rate Threshold Csr N (Spn_Err_Thresh) Field Descriptions
SRIO Registers 5.102 Port Error Rate Threshold CSR n (SPn_ERR_THRESH) Each of the four ports is supported by a register of this type. Figure 158. Port Error Rate Threshold CSR n (SPn_ERR_THRESH) 31-24 ERROR_RATE_FAILED_THRESHOLD RW-0xFF LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 207: Port Ip Discovery Timer In 4X Mode (Sp_Ip_Discovery_Timer) Field Descriptions
www.ti.com 5.103 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) Figure 159. Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) 31-28 DISCOVERY_TIMER RW-0x09 LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 133.
Page 208: Port Ip Mode Csr (Sp_Ip_Mode) Field Descriptions
SRIO Registers 5.104 Port IP Mode CSR (SP_IP_MODE) 31-30 SP_MODE IDLE_ TX_FI PW_DI TGT_I SELF_ ERR_ FO_B YPAS R-0x00 0x00 0x00 0x00 LEGEND: R = Read only; -n = value after reset 15-6 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 134.
Page 209 www.ti.com Table 134. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued) Field Value Description RST_EN Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols are received in a sequence Reset interrupt disable Reset interrupt enable RST_CS Reset received status bit.
Page 210: Serial Port Ip Prescalar (Ip_Prescal) Field Descriptions
SRIO Registers 5.105 Serial Port IP Prescalar (IP_PRESCAL) Figure 161. Serial Port IP Prescalar (IP_PRESCAL) LEGEND: R = Read only; -n = value after reset 15-8 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 135. Serial Port IP Prescalar (IP_PRESCAL) Field Descriptions Field Value Description...
Page 211: Port-Write-In Capture Csr N (Sp_Ip_Pw_In_Captn) Field Descriptions
www.ti.com 5.106 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPTn) Each of the four ports is supported by a register of this type. Figure 162. Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPTn) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only; -n = value after reset Table 136.
Page 212: Port Reset Option Csr N (Spn_Rst_Opt) Field Descriptions
SRIO Registers 5.107 Port Reset Option CSR n (SPn_RST_OPT) Each of the four ports is supported by a register of this type. Figure 163. Port Reset Option CSR n (SPn_RST_OPT) LEGEND: R = Read only; -n = value after reset 15-8 Reserved R-0x00...
Page 213: Port Control Independent Register N (Spn_Ctl_Indep) Field Descriptions
www.ti.com 5.108 Port Control Independent Register n (SPn_CTL_INDEP) Each of the four ports is supported by a register of this type. Figure 164. Port Control Independent Register n (SPn_CTL_INDEP) 28-27 Reserv TX_FL SOFT Reserved _REC R-0x00 0x00 0x00 0x00 LEGEND: R = Read only; -n = value after reset 15-8 MAX_RETRY_THR RW-0x00...
Page 214 SRIO Registers Table 138. Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions (continued) Field Value Description MAX_RETRY_EN Max_retry_error report enable. If enabled, the Port-Write and interrupt are reported as errors. Max retry error report enable Max retry error report disable MAX_RETRY_ER Max_retry_error bit is set when max_retry_cnt is equal to max_retry_threshold.
Page 215: Port Silence Timer N (Spn_Silence_Timer) Field Descriptions
www.ti.com 5.109 Port Silence Timer n (SPn_SILENCE_TIMER) Each of the four ports is supported by a register of this type. Figure 165. Port Silence Timer n (SPn_SILENCE_TIMER) 31-28 SILENCE_TIMER RW-0x0B LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 216: Port Multicast-Event Control Symbol Request Register N (Spn_Mult_Evnt_Cs)
SRIO Registers 5.110 Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) Each of the four ports is supported by a register of this type. Figure 166. Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) LEGEND: R = Read only; -n = value after reset LEGEND: R = Read only;...
Page 217: Port Control Symbol Transmit N (Spn_Cs_Tx) Field Descriptions
www.ti.com 5.111 Port Control Symbol Transmit n (SPn_CS_TX) Each of the four ports is supported by a register of this type. Figure 167. Port Control Symbol Transmit n (SPn_CS_TX) 31-29 STYPE_0 RW-0x00 LEGEND: R = Read only; -n = value after reset 15-13 CS_E RW-0x00...
Page 218: Important Notice
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Texas Instruments TMS320C645X User Manual

Preface

1 Overview

2 SRIO Functional Description

3 Logical/Transport Error Handling and Logging

4 Interrupt Conditions

5 SRIO Registers

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Summary of Contents for Texas Instruments TMS320C645X