Texas Instruments MSP430x1xx User Manual page 213

Figure 11−1. Timer_A Block Diagram
TASSELx
TACLK 00
ACLK 01
SMCLK 10
INCLK 11
CCISx
CCI2A 00
Capture
Mode
01
CCI2B
GND 10
Timer Clock
VCC 11
CCI
A
SCCI Y
EN
EQU0
Timer Clock
IDx
15
16−bit Timer
Divider
1/2/4/8
Clear
TACLR
CMx
logic COV
SCS
0
Sync 1
OUT
Output
Unit2
Timer Clock
OUTMODx
MCx
0
Count
TAR
Mode
RC
15
TACCR2
Compararator 2
EQU2
CAP
0
1
D Set Q
Reset
POR
Timer_A Introduction
Timer Block
EQU0
Set TAIFG
CCR0
CCR1
CCR2
0
Set TACCR2
CCIFG
OUT2 Signal
Timer_A 11-3