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USART Registers: SPI Mode
UxCTL, USART Control Register
7
6
Unused
Unused
rw−0
rw−0
Unused
Bits
Unused
7−6
†
I2C
Bit 5
I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1.
0
1
CHAR
Bit 4
Character length
0
1
LISTEN
Bit 3
Listen enable. The LISTEN bit selects the loopback mode
0
1
SYNC
Bit 2
Synchronous mode enable
0
1
MM
Bit 1
Master mode
0
1
SWRST
Bit 0
Software reset enable
0
1
† Applies to USART0 on MSP430x15x and MSP430x16x devices only.
14-14
USART Peripheral Interface, SPI Mode
5
4
3
I2C †
CHAR
LISTEN
rw−0
rw−0
rw−0
SPI mode
2
I
C mode
7-bit data
8-bit data
Disabled
Enabled. The transmit signal is internally fed back to the receiver
UART mode
SPI mode
USART is slave
USART is master
Disabled. USART reset released for operation
Enabled. USART logic held in reset state
2
1
SYNC
MM
SWRST
rw−0
rw−0
rw−1
0
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