Table of Contents
Advertisement
Chapter 6
NI-VXI Configuration Utility
Note
If you do not want to lose 4 KB of DRAM you can get around this limitation by
setting the Requested Memory option to double the amount that is installed on the
VXI/VME-MXI-2, because the DRAM is aliased throughout the remainder of the
requested memory space. The DRAM should then be accessed in the upper half of the
requested memory space.
A16 and A24/A32 Write Posting
Interlocked Mode
VXI/VME-PCI8026 for Linux
The VXI/VME-MXI-2 can increase performance with its capability to post
write cycles from both the MXIbus and the VXI/VMEbus. Write cycles
should be posted only to devices that cannot return a BERR signal, because
the BERR will not be reported to the originating master.
Select the appropriate option(s) if you want to use either A16 or A24/A32
write posting. By default, both options are disabled.
The A16 write posting option affects only write cycles that map through
the A16 window from the VXI/VMEbus to the MXIbus and vice versa.
A16 write cycles in VXI configuration space are never posted regardless
of the setting of this option.
The A24/A32 write posting option affects write cycles that map through the
A24 window and A32 window from the VXI/VMEbus to the MXIbus and
vice-versa. This option also affects write cycles to the VXI/VME-MXI-2
itself via its requested memory space from both the VXI/VMEbus and the
MXIbus. For more information on the A16, A24, and A32 windows, refer
to VXI-6, VXIbus Mainframe Extender Specification.
Interlocked arbitration mode is an optional mode of operation in which
at any given moment the system can perform as if it were one large
VXI/VMEbus mainframe with only one master of the entire
system—VXI/VMEbus and MXIbus. This mode of operation prevents
deadlocks by interlocking all arbitration in the VXI/VMEbus/MXIbus
system. By default, this option is disabled, which puts the
VXI/VME-MXI-2 in normal operating mode.
In normal operating mode (non-interlocked), multiple masters can operate
simultaneously in the VXI/VMEbus/MXIbus system. A deadlock occurs
when a MXIbus master requests use of a VXI/VMEbus resource in another
VXI/VMEbus mainframe while a VXI/VMEbus master in that mainframe
is in the process of requesting a resource across the MXIbus. When this
situation occurs, the VXI/VMEbus master must give up its bus ownership
to resolve the conflict. The RETRY signal is used to terminate the transfer
6-12
www.ni.com
Advertisement
Table of Contents
