Table of Contents
Advertisement
www.freeservicemanuals.info
EN 120
9.
EM5A NTSC
Implementation
3120
5102
6103
-13V
2101
10R
2n2
3103
1K
GND-STB
U
3105
MAINS
+375V
1K
3102
1K
3101
3107
3106
10M
STARTUP
3117
1K
1K
47R
V-START
6105
15V
2102
+
10µ
2111
3125
3126
6106
15R
10K
15V
3127
5K6
7100
Figure 9-4 Standby supply circuitry
To apply this on the EM5 (diagram A2): replace switch 'S' by
FET TS7102, coil L by L5101/L5100, diode D by D6111, and C
by C2104.
•
Time interval t0-t1: After switching 'on' the TV-set, the
gate of MOSFET TS7102 will be high (max. 15 V due to
zener diode D6105.) This will drive the FET into saturation
(U
= 0 V.) The DC-voltage U
DS
across the primary winding of L5101 (3, 5), resulting in a
linear increasing current through this coil. The voltage
across the co-coupled coil (1, 2) is also positive and will
keep the FET into conductivity via C2101, R3103/3105/
3102 and R3117 for some time. The self-induction of the
coil and the magnitude of the supply voltage (+375 V)
determine the slope of the primary current. The maximum
current is determined by the time the FET stays into
conductance (t0-t1.) This time is directly determined by the
voltage across R3108//R3118 (0.7 Ω.) This voltage is a
measure of the current and if it exceeds 1.4 V, TS7101 will
be driven into conductivity and consequently connects the
gate of TS7102 to earth. The FET will block. The current is:
1.4 V / 0.7 Ω = 2 A. The voltage across the secondary
winding (8, 9) will be negative, diodes D6111 and D6107
will block.
•
Time interval t1-t2: The sudden current interruption in the
primary coil will induce a counter-e.m.f. that wants to
maintain the current. The voltage on the drain of the FET
will increase. The secondary voltage (8, 9) will become
positive and will charge C2104 via D6111. All energy that
was stored in L5101 during t0-t1 will be transferred into the
load. Due to the transformer principle, a voltage will now
be induced in the primary winding (3, 5) and the co-coupled
winding (1, 2.) This voltage will be N* U
ratio.) The voltage across the co-coupled coil will be
negative, keeping the FET blocked.
•
Time t2: At t2, the current through the secondary coil will
be reduced to zero, as C2104 is no longer charged.
Consequently, the voltages will decay and will change
polarity. The gate of the FET will be again made positive, is
driven into conductivity, and the cycle starts again.
Circuit Descriptions and Abbreviation List
HOT
COLD
U
5100/5101
A
2
6111
1
I
SEC
8
U
2104
OUT
2114
10
2m2
10n
3110
ON
OFF
U A
5
2R2
3
t
I
PRIM
U
U D
D
7102
N . Usec
U MAIN
D
G
S
t
3113
3104
22R
47R
I PRIM
6105
15V
7101
t
3108
//3118
I SEC
6108
GND-STB
t
t0
t1
t2
3124
6122
68R
3V9
2109 +
3114
2149
220R
7103/7104
CL 26532041_062.eps
will be transposed
MAINS
(N= winding
SEC
Power On Reset (POR)
+5V2
RL
2743
110602
Via a reset circuit (TS7708) a reset pulse (POR) of 20 ms is
generated for the µP inside the PICNIC and for the ROM. After
'power on,' the 3V3 is built up (derived from the 5V2.) Transistor
TS7708 blocks and pin 6 of the PICNIC will follow the rising
slope of the power supply. As soon as the power supply is
stabilized, capacitor C2744 will charge (via R3748.) When this
voltage reaches 0.6 V (after 20 ms), TS7708 starts to conduct,
and the voltage at pin 6 goes low again. The µP is reset now. If
the PICNIC cannot communicate with the ROM, the 'watchdog'
will generate a reset pulse (on pin 7), which will re-start the
cycle again.
If one of the power supplies is absent (or too low), then a safety
problem can occur in some cases (for example, a too high
temperature of the stabilizer.) To prevent this from happening,
the voltage dividers at the bases of the transistors TS7710 and
TS7707 are calculated such, that they will block when the
situation described above occurs. In this case, the base of
TS7708 is kept 'low' by the conducting TS7709, until the
problem is solved. The µP receives no POR pulse, and cannot
be reset.
5V2 Stabilization and Feedback
The Standby Power Supply always oscillates at maximum
power. The only limiting factor is the maximum primary current,
which has been preset with R3108//3118.
R3113, zener diode D6122, R3124, and R3114 determine
U
. If the voltage across R3114 exceeds the threshold
OUT
voltage of the diode of the optocoupler 7104 (± 1 V) or, in other
words, U
will conduct.
Transistor TS7100 is now driven, and a negative voltage will be
transposed to the emitter of TS7101. When TS7101 conducts,
the gate of the FET is at earth potential, forcing the oscillator
stop. Due to the load, the secondary voltage U
decrease. At a certain voltage, optocoupler TS7104 will block
and the oscillator will start again.
Since there are no capacitors, and there is a high amplification
factor in the feedback circuit, the feedback is ultra-fast. This is
why the ripple on U
(-20 V) used in the feedback circuit, originates from the co-
coupling coil, and is rectified through D6103.
Stabilization is not effected through duty-cycle control but
through burst-mode of TS7100.
Burst-mode is load dependent. If the power supply is less
loaded, the secondary voltage will have the tendency to
increase more rapidly. If the load on the power supply
increases, then the oscillator stops less often, right up to the
moment that the oscillator is operating continuously: maximum
load. If the power supply is now loaded even more, the output
2V5B
3V3_FBX
20 ms
3748
3751
3752
7708
3753
2744
3747
3790
2 ms
3V3_FBX
3736
3746
7709
3737
7710
3V3_FBX
3749
3738
7707
3756
3739
3755
Figure 9-5 Power On Reset
exceeds 5.2 V, the transistor of the optocoupler
OUT
is minimal. The negative supply voltage
OUT
.6 µP RESET
.7 WD RESET
PICNIC
3741
3V3_FBX
3743
2V5D
3742
3V3_E
3750
1V5_E
2V5B
CL 26532041_075.eps
170402
will
OUT
Advertisement
Table of Contents
