Matrox Solios Series Installation And Hardware Reference
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Matrox Solios Series Installation And Hardware Reference

Matrox Solios Series Installation And Hardware Reference

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Matrox Solios
Installation and Hardware Reference
Manual no. 10898-101-0400
March 27, 2008

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  • Page 1 Matrox Solios Installation and Hardware Reference Manual no. 10898-101-0400 March 27, 2008...
  • Page 2 © Copyright Matrox Electronic Systems Ltd., 2004 - 2008. All rights reserved. Limitation of Liabilities: In no event will Matrox or its suppliers be liable for any indirect, special, incidental, economic, cover or consequential damages arising out of the use of or inability to use the product, user documentation or related...

  • Page 3: Table Of Contents

    With all Matrox Solios packages ........24...
  • Page 4 Connecting to Matrox Solios eA/XA....... . 39 Connecting to Matrox Solios GigE ....... . . 41 Chapter 3: Using multiple Matrox Solios boards .
  • Page 5 Matrox Solios eA/XA acquisition section ........71...
  • Page 6 Connectors on Matrox Solios eA/XA ........
  • Page 7 Connectors on Matrox Solios GigE ........

  • Page 9: Chapter 1: Introduction

    Chapter Introduction Chapter 1: This chapter briefly describes the features of the Matrox Solios boards, as well as the software that can be used with the boards.

  • Page 10: Matrox Solios Boards

    If purchased with the optional Processing FPGA, members also have custom image processing capabilities. The PCI-X compliant boards are Matrox Solios XCL and Matrox Solios XA. The PCIe compliant boards are Matrox Solios eCL, Matrox Solios eA, and Matrox Solios GigE. The PCIe compliant boards provide the exact same features as the related PCI-X boards, except for the way the boards connect to the Host bus.
  • Page 11 Matrox Solios boards Matrox Solios eCL/XCL-B Matrox Solios eCL/XCL-B supports acquisition from one Camera Link device in the Base configuration; the device can be a power-over Camera Link (PoCL) video source. Matrox Solios eCL/XCL-B supports Camera Link frequencies of up to 85 MHz.
  • Page 12 When in single-Medium mode, the board supports one Camera Link device in the Medium configuration. Matrox Solios eCL/XCL dual-Base/single-Medium boards are available in two maximum frequencies. By default, the boards support Camera Link frequencies of up to 66 MHz. However, a fast Camera Link version is available and supports Camera Link frequencies of up to 85 MHz.
  • Page 13 Matrox Solios boards Matrox Solios eCL/XCL Acquisition memory dual-Base/single-Medium (64/128/256 MB) (single-Medium mode) 64 DDR Optional (up to 1.6 GB/s)*** DDR SDRAM (64/128/256 MB) Video to Clock PCI-X Second (up to 1.3 GB/s) ChannelLink bridge MDR-26 Data (24) Receiver #2 connector &...
  • Page 14 Matrox Solios eCL/XCL-F Matrox Solios eCL/XCL-F supports acquisition from one Camera Link device in the Base, Medium, or Full configuration (with up to 10 taps). Matrox Solios eCL/XCL-F supports Camera Link frequencies of up to 85 MHz; additionally, Matrox Solios eCL/XCL-F supports the Processing FPGA option.

  • Page 15: Acquisition With Matrox Solios Ea/Xa

    Matrox Solios eA/XA Single can acquire from one analog video source. This acquisition path has an input selector that can switch between receiving input from one of two video sources. Matrox Solios eA/XA Single does not support the optional Processing FPGA.
  • Page 16 16 Chapter 1: Introduction Matrox Solios eA/XA Dual Matrox Solios eA/XA Dual can acquire from up to two independent analog video sources. For added flexibility, each acquisition path has an input selector that can switch between receiving input from one of two video sources.
  • Page 17 Matrox Solios boards Acquisition with Matrox Solios eA/XA Quad Matrox Solios eA/XA Quad can acquire from up to four independent analog video sources. For added flexibility, each acquisition path has an input selector that can switch between receiving input from one of two video sources. This means, for example, that you can connect two 4-tap video sources to the eA/XA Quad board and switch between them.

  • Page 18: Acquisition With Matrox Solios Gige

    18 Chapter 1: Introduction Acquisition with Matrox Solios GigE Matrox Solios GigE is an industrial Gigabit Ethernet (GbE) network interface card (NIC), which is optimized to act as a high-performance GigE Vision frame grabber for It supports acquisition from up to four GigE Vision video GigE Vision video sources.

  • Page 19: Processing Capabilities

    DDR SDRAM and QDRII SRAM memory. On-board memory As a standard feature, Matrox Solios supports up to 256 Mbytes of linearly addressable DDR SDRAM to store acquisition data. This memory is referred to as acquisition memory.
  • Page 20 DB-9 connector from the SOLCLBACCxxPAK accessory kit, less auxiliary signals are available (see the pinout of the auxiliary I/O connector in Appendix B: Technical information). • Matrox Solios eA/XA also has a bi-color LED per timing and control section to monitor PLL operation and sychronization signal input. Matrox Solios eA/XA Quad has a total of four LEDs, Matrox Solios eA/XA Dual has two LEDs, while Matrox Solios eA/XA Single has one LED.

  • Page 21: Data Transfer

    4 active lanes; the eCL-B and eA Single boards can use a x1 PCIe slot. If Matrox Solios XCL and XA are used with a conventional 3.3 or 5V PCI slot, the maximum transfer rate is reduced (132 Mbytes/sec for a 32-bit PCI slot, 266 Mbytes/sec for a 66 MHz 32-bit PCI slot, and 532 Mbytes/sec for a 66 MHz 64-bit PCI slot).

  • Page 22: Software

    22 Chapter 1: Introduction Software To operate Matrox Solios, you can use one or more Matrox Imaging software products that supports the board. These are the Matrox Imaging Library (MIL) and its derivatives (MIL-Lite, ActiveMIL, ActiveMIL-Lite, Matrox Inspector, and Matrox Intellicam). All Matrox software is supported under Windows; consult your software manual for supported Windows environments.

  • Page 23: Essentials To Get Started

    Note that only Matrox Solios eCL, eA, and GigE support a PCIe slot, and it ❖ should be a x4 or x8 PCIe slot. For Matrox Solios eCL-B or eA Single, it can also be a x1 slot. • Processor with an Intel 32-bit architecture (IA32) or equivalent.

  • Page 24: Inspecting The Matrox Solios Package

    With all Matrox Solios packages Standard items You should receive the following item: • The Matrox Solios eCL, XCL, eA, XA, or GigE board, depending on which was purchased. With Matrox Solios eCL/XCL and Matrox Solios eA/XA You should also receive the following items: •...

  • Page 25: Available Separately

    • DVI-TO-8BNC/O, an 8-foot (2.4 m) input cable with a DVI connector on one end and both 8 BNCs and open-ended wires on the other end. This cable is meant to connect to Matrox Solios eA/XA. The open-ended wires allow you to connect to the synchronization and control signals of the module.

  • Page 26: Handling Components

    26 Chapter 1: Introduction Handling components The electronic circuits in your computer and the circuits on Matrox Solios are sensitive to static electricity and surges. Improper handling can seriously damage the circuits. Be sure to drain static electricity from your body by touching a metal fixture (or ground) before you touch any electronic component.
  • Page 27 To do so, you should first complete and submit the online Technical Support Request Form, accessible from the above-mentioned page. Once the information is submitted, a Matrox support agent will contact you shortly thereafter by email or phone, depending...
  • Page 28 28 Chapter 1: Introduction...

  • Page 29: Chapter 2: Hardware Installation

    Chapter Hardware Chapter 2: installation This chapter explains how to install your Matrox Solios board in your computer.

  • Page 30: Installing Your Matrox Solios Board

    1. Remove the cover from your computer; refer to your computer’s documentation for instructions. 2. Check that you have an empty PCIe slot in which to install your Matrox Solios eCL, eA, or GigE; the slot must have at least 4 active lanes, except for eCL-B and eA Single which need one active lane.
  • Page 31 Some computers have a large, black-ridged heat sink that prevents long boards from using some of the PCI board slots. Matrox Solios must not touch the heat sink. Therefore, choose a slot where the board completely avoids it. If you cannot find a suitable slot, contact your computer dealer.
  • Page 32 Important When installing a Matrox Solios eCL, eA, or GigE board in a x16 PCIe slot, special care must be taken to avoid damaging the board. Some x16 PCIe slots have a connector with a retainer. Matrox Solios boards must not come into contact with the latch of this retainer.
  • Page 33 Installing your Matrox Solios board 5. Anchor the board using the screw that you removed in step 3. 6. If required, install the adapter board/bracket of your Matrox Solios board, as described in the section Installing an adapter board/bracket, later in this chapter.

  • Page 34: Installing An Adapter Board/Bracket

    1. Make sure that your Matrox Solios eCL/XCL, eA/XA, or GigE board is fastened to the computer chassis. 2. If you are installing the adapter board of Matrox Solios eA/XA and the slot that you have selected for the board is not a PCI/PCI-X slot, break off the board’s tab if it interferes with other components in the computer.
  • Page 35 Installing an adapter board/bracket Matrox Solios board and the cable in this position, only the connector on one end of the cable will latch properly onto the internal auxiliary I/O connector. The other end will not and excessive force might damage the cable connector.
  • Page 36 36 Chapter 2: Hardware installation 5. If you are installing the adapter board of Matrox Solios eA/XA in a PCI/PCI-X/PCIe slot, align the board’s tab with the slot’s connector, and then press the board firmly but carefully into the slot’s connector. For other types of...

  • Page 37: Connecting Video Sources

    Connecting video sources Connecting to Matrox Solios eCL/XCL-B The Matrox Solios eCL/XCL-B board has the following connectors on its bracket: • One Camera Link-compliant video input connector. Used to receive video input, timing, and synchronization signals and transmit/receive communication signals between the video source and the frame grabber.

  • Page 38: Connecting To Matrox Solios Ecl/Xcl Dual-Base/Single-Medium Or Ecl/Xcl-F Boards

    38 Chapter 2: Hardware installation Connecting to Matrox Solios eCL/XCL dual-Base/single-Medium or eCL/XCL-F boards Matrox Solios eCL/XCL dual-Base/single-Medium and Matrox Solios eCL/XCL-F boards have the following connectors: • Two Camera Link-compliant video input connectors (on the bracket). Used to receive video input, timing, and synchronization signals and transmit/receive communication signals between the video source and the frame grabber.

  • Page 39: Connecting To Matrox Solios Ea/Xa

    3M Interconnect Solutions for Factory Automation, Intercon 1, or other third parties. Note that this cable is not available from Matrox. If using both Camera Link connectors in single-Medium mode, the cables must be of the same type and length.
  • Page 40 Two of these cables are required to connect to more than 4 video sources if using Matrox Solios eA/XA Quad, more than 2 video sources if using Matrox Solios eA/XA...

  • Page 41: Connecting To Matrox Solios Gige

    1. Note that only VID IN 0, TRIG 0, and EXP 0 can be used with Matrox Solios eA/XA Single since there is only one acquisition path (P0). 2. Note that only VID IN 0 and 1, TRIG 0 and 1, and EXP 0 and 1 can be used with Matrox Solios eX/XA Dual since there are only two acquisition paths (P0 and P1).
  • Page 42 Matrox Solios GigE supports acquisition from up to 4 GigE Vision-compliant video sources. You can connect one GigE Vision-compliant video source directly to each Ethernet connector on Matrox Solios GigE. Alternately, you can connect each Ethernet connector on Matrox Solios GigE to any Ethernet network that...
  • Page 43 100 Mbps Fast Ethernet (100BASE-T) and 10 Mbps Ethernet (10BASE-T) networks. It is recommended that you use Matrox Solios GigE with Gigabit Ethernet networks to ensure maximum performance. ❖ For optimal performance, connect each GigE Vision video source directly to...
  • Page 44 44 Chapter 2: Hardware installation...

  • Page 45: Chapter 3: Using Multiple Matrox Solios Boards

    Chapter Using multiple Chapter 3: Matrox Solios boards This chapter explains how to use multiple Matrox Solios boards.

  • Page 46: Multiple Board Installation

    (refer to Chapter 2: Hardware installation). Theoretically, you can have as many as 16 Matrox Solios boards installed in your computer; this number is limited by the number of empty slots in your computer and by the available bandwidth of your PCIe/PCI/PCI-X interface (segment), as discussed in the next section.
  • Page 47 PCIe/PCI/PCI-X transfers to Host memory. If a high performance chipset and a 133 MHz 64-bit PCI-X slot is used with Matrox Solios XCL and XA, you should not have a problem with dropped frames. The list of platforms that are known to be compatible with Matrox Solios are available on the Matrox web site, under the board’s compatibility list.
  • Page 48 48 Chapter 3: Using multiple Matrox Solios boards...

  • Page 49: Chapter 4: Matrox Solios Hardware Reference

    Chapter Matrox Solios Chapter 4: hardware reference This chapter explains the architecture, features, and modes of the Matrox Solios eCL/XCL, Matrox Solios eA/XA, and Matrox Solios GigE hardware.

  • Page 50: Matrox Solios Hardware Reference

    (eCL/eA/GigE) 64-bit Matrox Solios eCL/XCL-B: 32-bit. (XCL/XA) **** Matrox Solios eCL-B: 32-bit. Host PCI/PCI-X/PCIe bus A summary of the features of Matrox Solios, as well as pin assignments for the various connectors, can be found in Appendix B: Technical information.

  • Page 51: Acquisition Path

    MIL-Lite function. For more specialized adjustments, use the Matrox Intellicam program to adjust the DCF file. Using Matrox Intellicam, you can set the active video region, the sampling clock, and all the other parameters related to the timing of the video signal (that is, standard and non-standard video, interlaced or non-interlaced) in your DCF file.

  • Page 52: Matrox Solios Ecl/Xcl Acquisition Section

    85 Mega-samples/sec. Each acquisition path has its own programmable synchronization generator (PSG), formatters, and LUTs, and can have a different acquisition rate. Matrox Solios eCL/XCL supports a comprehensive set of general purpose I/O and serial ports to control cameras...

  • Page 53: Performance

    680 Mbytes/sec The maximum pixel clock frequency is dependent on the length of the cable used. Refer to the Technical features of Matrox Solios eCL/XCL section. Acquisition A Base-type acquisition path supports a maximum of 24 bits of video data when acquiring from Camera Link-compliant video sources or up to 32 bits when acquiring from non-standard time-multiplexed video sources.
  • Page 54 54 Chapter 4: Matrox Solios hardware reference The video sources can be frame, field, or line-scan video sources. Note that the acquisition paths in dual-Base mode are completely independent, and therefore the video sources do not need to be identical when running in dual-Base mode.
  • Page 55 Matrox Solios eCL/XCL acquisition section UART SerTFG LVDS driver PSG #1 & receiver SerTC Second MDR-26 LVDS Cam Ctrl (4) connector drivers Clock ChannelLink LUTs Data (24) Receiver #2 Video & Syncs (4)* PCI-X Bridge Data (24) ChannelLink & Syncs (4)*...
  • Page 56 56 Chapter 4: Matrox Solios hardware reference Clock Second ChannelLink MDR-26 Data (24) Receiver #2 Video connector & Syncs (4)* LUTs PCI-X Data (24) bridge ChannelLink & Syncs (4)* Receiver #1 Clock LVDS First Cam Ctrl (4) drivers MDR-26 connector...
  • Page 57 Matrox Solios eCL/XCL acquisition section Clock ChannelLink Receiver #3 Data (28)* Second Video MDR-26 Clock ChannelLink connector LUTs Receiver #2 PCI-X Data (28)* bridge Data (24) ChannelLink & Syncs (4)* Receiver #1 Clock LVDS First Cam Ctrl (4) drivers MDR-26...

  • Page 58: Supported Video Sources

    Not Camera Link Standard • 10 tap x 8-bit. ❖ Note that Matrox Solios eCL/XCL boards can simultaneously write to a limited number of non-sequential memory regions; this further restricts the tap configurations supported. Matrox Solios eCL/XCL-B can write to two non-sequential memory regions.

  • Page 59: Channellink Receivers

    Matrox Solios eCL/XCL acquisition section write to four. This means that using Matrox Solios eCL/XCL-F, for example, you could only grab from an 8-tap x 8-bit video source if four of the taps carry pixels that are sequential to the other four taps. To establish the number of non-sequential memory regions to which your video source must write, refer to the documentation accompanying your video source.

  • Page 60: Demultiplexers

    Lookup tables Matrox Solios eCL/XCL has on-board lookup tables (LUTs) that can be used to precondition input data at acquisition time, before it is stored in an image buffer. The various versions of Matrox Solios eCL/XCL support different lookup table configurations.

  • Page 61: Communication

    Matrox Solios eCL/XCL acquisition section Dual-Base/single-Medium and single-Full boards Matrox Solios eCL/XCL dual-Base/single-Medium and Matrox Solios eCL/XCL-F boards each have programmable LUTs. In dual-Base mode, the LUTs can be operated in the following configurations per acquisition path • 8 palettes of one, two, three, or four 256-entry 8-bit LUTs.

  • Page 62: Uarts

    Synchronization, timing, and control signals The following tables summarize the synchronization, timing, and control signals supported by Matrox Solios eCL/XCL. Most of these signals are available by defining a camera control or auxiliary (multi-purpose) signal as the required synchronization, timing, or control signal in the DCF.
  • Page 63 Matrox Solios eCL/XCL acquisition section TTL aux. OPTO LVDS cam. ctrl LVDS LVDS aux. in aux. in aux. out CL connect. Type of signal Exposure output 0/1 0/1 0/1 0/1 2 0/3 1 Trigger input Field polarity input Timer-clock input...
  • Page 64 2. On external auxiliary I/O connector 0 (DB-44). 3. On external auxiliary I/O connector 1 (DB-9). 4. Note that a rotary encoder (starting with Matrox Solios XCL Version 100) with quadrature output transmits a two-bit code. The table entries, therefore, denote bit posi- tion.
  • Page 65 3. Clock input is received on the Camera Link connectors, whereas the other signals in this column are received on/transmitted from external auxiliary I/O connector 0 (DB-44). Auxiliary signals and camera control signals Matrox Solios eCL/XCL supports multi-purpose auxiliary input and output signals. Auxiliary signals are configurable signals that can support one or several functions, one of which is user-defined. As mentioned previously, for each...
  • Page 66 66 Chapter 4: Matrox Solios hardware reference Matrox Solios eCL/XCL-B has auxiliary/camera control signals in the following formats: Auxiliary signals # total LVDS camera control output signals. TTL auxiliary input or output signals. Opto-isolated auxiliary input signals. LVDS auxiliary input signals.
  • Page 67 To output an exposure signal, use the MIL-Lite function MdigControl() with M_GRAB_EXPOSURE. Set the clock source of an exposure timer in the DCF. 1. For the standard Camera Link speed Matrox Solios XCL dual-Base/single-Medium boards (66 MHz), four timers have been available starting from version 100. Prior to...
  • Page 68 68 Chapter 4: Matrox Solios hardware reference Next valid frame/field and asynchronous reset modes Matrox Solios eCL/XCL can operate in two modes: next valid frame/field mode and asynchronous reset mode. In next valid frame/field mode, the board waits for the next valid frame or field (as specified by the DCF file) before commencing the grab.
  • Page 69 The quadrature decoder supports a maximum encoder frequency equal to the pixel clock frequency of the video source. 1. For the standard Camera Link speed Matrox Solios XCL dual-Base/single-Medium boards (66 MHz), starting from version 100.
  • Page 70 70 Chapter 4: Matrox Solios hardware reference The PSGs of all Matrox Solios eCL/XCL boards support 5 V tolerant rotary encoders, except fot the PSGs of the standard-speed Matrox Solios XCL dual-Base/single-Medium board , which supports 3.3 V tolerant rotary (66 MHz) encoders.

  • Page 71: Matrox Solios Ea/Xa Acquisition Section

    8 bits or all 10 bits can be stored. Each acquisition path has its own filters, programmable gain, and LUTs. Matrox Solios eA/XA supports video sources with up to 4 taps, depending on the version, and can grab at a maximum rate of 65 Mega-samples/sec per acquisition path.
  • Page 72 ✝ Only acquisition path 0 is available on Matrox Solios eA/XA Single. ✕ Only acquistion paths 0 and 1 are available on Matrox Solios eA/XA Dual. ✝✝ Only two auxiliary outputs are used on Matrox Solios eA/XA Single. Four auxiliary outputs are used on Matrox Solios eA/XA Dual.

  • Page 73: Performance

    2. Note that Matrox Solios eA/XA Single only has acquisition path 0 and can therefore support only 1 tap. Matrox Solios eA/XA Dual only has acquisition paths 0 and 1,...
  • Page 74 74 Chapter 4: Matrox Solios hardware reference Input voltage level and protection The various amplification stages on Matrox Solios eA/XA are able to provide a maximum peak signal of 2.4 V without saturation. Any positive video signal level greater than this threshold will be distorted, so it is not recommended to feed a signal above 3 V with termination (6 V unterminated).
  • Page 75 For each acquisition path, you can adjust the signal’s black and white reference levels so that the full dynamic range of each 10-bit A/D is used. Matrox Solios eA/XA uses the offset-gain topology to adjust the black and white reference levels of the signal.
  • Page 76 A/D converter. Each acquisition path has two filters. The filters used on Matrox Solios are 4th order Butterworth filters. The first has a -3 dB cutoff frequency of 33 MHz. The second filter has a -3 dB cutoff frequency of 7.5 MHz, useful for RS-170 and CCIR video sources.

  • Page 77: Uarts

    UARTs Matrox Solios eA/XA Quad offers four RS-232 compatible serial interfaces, Matrox Solios eA/XA Dual offers two, whereas Matrox Solios eA/XA Single offers one. Each interface is mapped as a COM port so that it can be accessed through the Win32 API. Each interface is comprised of both a transmit port and a receive port, permitting the interface to work in full-duplex mode.

  • Page 78: Synchronization, Timing, And Control Signals

    Single features one. The PSGs are responsible for managing all input and output video timing, synchronization, trigger, exposure, and user-defined signals. The PSGs on Matrox Solios eA/XA allow the board to adapt to many video standards. Each PSG allows for independent acquisition from a video source.
  • Page 79 Matrox Solios eA/XA acquisition section Note that only signals defined for acquisition path 0 (those beginning with P0) and the common LVDS/TTL auxiliary signals apply to the Matrox Solios eA/XA Single board. Only signals defined for acquisition paths 0 and 1 and the common LVDS/TTL signals apply to the Matrox Solios eA/XA Dual board.
  • Page 80 80 Chapter 4: Matrox Solios hardware reference TTL aux. input TTL aux. output Opto aux. TTL/LVDS aux. input TTL/LVDS aux. output input Type of signal Data valid input Timer- clock input User- defined Input User- defined output 1. The maximum # for each signal type cannot always be attained. The actual maximum depends on whether the required auxiliary signals are available or have been defined as another type.
  • Page 81 4. The board can accept an HSYNC or CSYNC input signal, but it can only output an HSYNC signal. Auxiliary signals Matrox Solios eA/XA supports multi-purpose auxiliary input and output signals. Auxiliary signals are configurable signals that can support one or several functions, one of which is user-defined.
  • Page 82 82 Chapter 4: Matrox Solios hardware reference The board supports auxiliary signals in different formats: Auxiliary signals # per path Matrox Solios Matrox Solios Matrox Solios eA/XA Quad #total eA/XA Dual # total eA/XA Single #total Auxiliary input signals that can be defined as either depends on TTL or LVDS.
  • Page 83 Matrox Solios eA/XA acquisition section Clock Each PSG can accept or provide one pixel clock signal (slave or master mode). Important When accessed from the analog video input connectors (DVI), the pixel clock, composite/horizontal synchronization, and vertical synchronization signals of each PSG form a group of signals.
  • Page 84 84 Chapter 4: Matrox Solios hardware reference Next valid frame/field and asynchronous reset modes Each PSG can operate in two modes: next valid frame/field mode and asynchronous reset mode. In next valid frame/field mode, the board waits for the next valid frame or field (as specified by the DCF file) before commencing the grab.
  • Page 85 Matrox Solios eA/XA acquisition section User-defined signals Any auxiliary signal can be configured as a user-defined signal. You can route any input signal that meets specifications to an auxiliary input signal (or auxiliary I/O signals in input mode) configured as a user-defined signal; your application can then interpret this user-defined signal as required.

  • Page 86: Matrox Solios Gige Acquisition Section

    86 Chapter 4: Matrox Solios hardware reference Matrox Solios GigE acquisition section Matrox Solios GigE can capture video from up to four digital video sources compliant with the GigE Vision specification. Matrox Solios GigE supports monochrome and component RGB, YUV, and YCbCr acquisition. Grabbed data can be converted into RGB, YUV, and YCbCr formats, depending on the input format, using the color space converter of the Video to PCI-X bridge.

  • Page 87: Performance

    Matrox Solios GigE supports simultaneous acquisition from up to four independent frame, field, and line-scan video sources that transfer images in GigE Vision format with the following pixel types. Matrox Solios GigE can convert incoming images to the following formats.

  • Page 88: Gige Vision Filter

    The image reconstructor has four image contexts, which in essence provide 4 independent acquisition paths. Auxiliary I/O controller Matrox Solios GigE features an auxiliary I/O controller. The auxiliary I/O Auxiliary signals controller is responsible for managing the auxiliary signals supported by the board.
  • Page 89 For example, any auxiliary output signal, or auxiliary I/O signal in output mode, can be set to exposure output signal 0. Note that for Matrox Solios GigE, the synchronization, timing, and control signals are not dependent on an acquisition path, and by extension, neither are the auxiliary signals.
  • Page 90 90 Chapter 4: Matrox Solios hardware reference OPTO aux. in LVDS TTL aux. I/O TTL aux. out aux. in Type of signal Timer-trigger input Timer-clock input...
  • Page 91 Matrox Solios GigE acquisition section OPTO aux. in LVDS TTL aux. I/O TTL aux. out aux. in Type of signal User-defined In/Out In/Out In/Out In/Out You can set the type of signal to route to an output auxiliary signal, or auxiliary I/O signal in output mode, using the MIL-Lite function MdigControl() with M_AUX_SIGNAL_SOURCE+n, where n is a value between 6 and 17.
  • Page 92 92 Chapter 4: Matrox Solios hardware reference Specifications of the auxiliary signals The board supports the auxiliary signals in different formats: Auxiliary signals Number of signals Opto-isolated auxiliary input signals LVDS auxiliary input signals TTL auxiliary I/O signals TTL auxiliary output signals When an auxiliary input signal is received in TTL format directly, the signal must have a maximum amplitude of 5 V.
  • Page 93 Matrox Solios GigE acquisition section Exposure timers The auxiliary I/O controller has eight exposure timers. Each exposure timer can generate exposure output signals to control the exposure time and other external events related to the video source (such as a strobe). The exposure signals can be output using auxiliary output signals or auxiliary I/O signals in output mode.
  • Page 94 94 Chapter 4: Matrox Solios hardware reference Timer trigger The auxiliary I/O controller supports 10 timer-trigger input signals, which can trigger any of the exposure timers. You can use the timer-trigger input signals to synchronize the generation of an exposure signal with an external event. The timer-trigger input signals can be received using auxiliary input signals or auxiliary I/O signals in input mode;...
  • Page 95 MdigInquire() and MdigControl() with M_USER_BIT_... Combining signals Matrox Solios GigE allows you to combine different signals and output them on one auxiliary signal, using an AND or OR operation. You can combine: • Two exposure signals. This allows you to generate, for example, multiple pulses or more complex pulses on one signal.

  • Page 96: Processing Fpga

    To use the Processing FPGA, you must configure it with an FPGA configuration that defines the appropriate functionality. An FPGA configuration is a code segment that is used to program an FPGA. You can use standard Matrox FPGA configurations or you can create your own using the Matrox FPGA Developer’s Toolkit (FDK) for Matrox Solios.

  • Page 97: Processing Fpga

    The Processing FPGA includes a 32-channel (16 channels per direction), high-speed serial interface to communicate with the acquisition section of the Matrox Solios boards. Each channel has a data rate of 462 Mbits/sec, for a total of 924 Mbytes/sec per direction.

  • Page 98: Dedicated Processing Fpga Memory

    98 Chapter 4: Matrox Solios hardware reference Dedicated Processing FPGA memory When you purchase a Matrox Solios with a Processing FPGA, the board also comes with the following memory, which can only be accessed through the Processing FPGA: • 64/128/256 Mbytes of DDR SDRAM at 1.33 Gbytes/sec (2 x 64 bits x 83.3 MHz).
  • Page 99 Video to PCI-X bridge • Vertical flipping. Captured image data can be flipped vertically. • Color space conversion. For all versions of Matrox Solios except Matrox Solios GigE, the color space converter in the video to PCI-X bridge can convert grabbed image data to YUV and YCbCr formats.

  • Page 100: Memory

    800 Mbytes/sec. Matrox Solios eCL/XCL-F supports up to 256 Mbytes of 110 MHz SDRAM with a bandwidth of 1.76 Gbytes. If the optional Processing FPGA is installed on the board, Matrox Solios supports Optional memory up to 256 Mbytes of additional DDR SDRAM and either four or eight Mbytes...

  • Page 101: Pcie/Pci/Pci-X Interface

    For Matrox Solios eCL-B and eA Single, these conditions include using the board in a x1 PCIe slot. For Matrox Solios XCL and XA, these conditions include using the board in a 133 MHz PCI-X slot. If Matrox Solios XCL and XA...
  • Page 102 Using the PCIe/PCI/PCI-X bus, Matrox Solios can also access Host physically contiguous, non-paged memory. An advantage of this memory is that a bus mastering device (such as Matrox Solios) can access this memory without the help of the Host CPU.

  • Page 103: Appendix A: Glossary

    Appendix A: Glossary Appendix A: This appendix defines some of the specialized terms used in the Matrox Solios documentation.

  • Page 104: Glossary

    • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory. A type of memory used for image capture and processing. SDRAM allows the Matrox Solios to access data at very high speed, which is important for I/O-bound functions. • Digitizer Configuration Format...
  • Page 105 Glossary • Double buffering Alternating the destination of an operation between two buffers. Double buffering allows you to, for example, process one buffer while grabbing into the other buffer. • Dynamic range The range of values present in a buffer. An unsigned 8-bit buffer, for example, has an allowable range of 0 to 255;...
  • Page 106 106 Appendix A: Glossary • Gain level The factor by which an analog input signal is scaled. The gain affects the brightness and contrast of the resulting image. • Grab To acquire an image from a video source. • Horizontal blanking period The portion of a video signal after the end of a line and before the beginning of a new line.
  • Page 107 Glossary • LVDS Low-voltage differential signalling. LVDS offers a general-purpose, high bandwidth interface standard for serial and parallel data interfaces that require increased bandwidth at high speed, with low noise and power consumption. • Progressive scanning Describes a transfer of data in which the lines of the source are written sequentially into the destination buffer.
  • Page 108 108 Appendix A: Glossary • Saturate To replace overflows (or underflows) in an operation with the highest (or lowest) possible value that can be held in the destination buffer of the operation. • UART Universal Asynchronous Receiver/Transmitter. A component that handles asynchronous communication through a serial interface (for example, RS-232 or LVDS).

  • Page 109: Appendix B: Technical Information

    Appendix B: Technical Appendix B: information This appendix contains information that might be useful when installing your Matrox Solios board.

  • Page 110: Board Summary

    Windows. • Computer requirements: - For Matrox Solios eCL, eA and GigE, a x4 or x8 PCIe slot; Matrox Solios eCL-B and eA Single can also be used in x1 PCIe slot. For Matrox Solios XCL and XA, an available conventional PCI slot or PCI-X slot.

  • Page 111: Technical Features Of Matrox Solios Ecl/Xcl

    Technical features of Matrox Solios eCL/XCL Features common to all Matrox Solios eCL/XCL boards • PCIe or PCI/PCI-X short board. Matrox Solios XCL has a universal (3.3 V - 5 V) 64-bit board edge connector; Matrox Solios eCL has a x4 PCIe connector, except for Matrox Solios eCL-B, which has a x1 PCIe connector.
  • Page 112 • Separate LVDS pixel clock, HSYNC, and VSYNC outputs. • Three TTL auxiliary I/O signals (trigger, field polarity, or user-defined input, or exposure or user-defined output). See the Matrox Solios hardware reference chapter for supported configurations. • One LVDS auxiliary output signal (exposure or user-defined output). See the Matrox Solios hardware reference chapter for supported configurations.
  • Page 113 Board summary • Two LVDS auxiliary input signals (trigger, field polarity, timer-clock, quadrature, or user-defined input). See the Matrox Solios hardware reference chapter for supported configurations. • Two opto-isolated auxiliary input signals (trigger, field polarity, or user-defined input). See the Matrox Solios hardware reference chapter for supported configurations.
  • Page 114 Camera Link frequencies: standard Camera Link boards have a maximum frequency of 66 MHz, while fast Camera Link boards support a maximum frequency of 85 MHz. Matrox Solios eCL/XCL-F has a maximum frequency of 85 MHz. • In single-Medium and single-Full modes, the programmable LUTs can be operated in the following configurations - 8 palettes of one, two, three, four, or eight 256-entry 8-bit LUTs.
  • Page 115 1.32 Gbytes/sec of memory bandwidth is available. Note that when the optional Processing FPGA is installed or when the fast Camera Link board is used, these numbers increase to 100 MHz and 1.6 Gbytes/sec, respectively. For Matrox Solios eCL/XCL-F, 64/128/256 Mbytes of 110 MHz DDR SDRAM is available with 1.76 Gbytes of memory bandwidth.

  • Page 116: Technical Features Of Matrox Solios Ea/Xa

    116 Appendix B: Technical information Technical features of Matrox Solios eA/XA • PCIe or PCI/PCI-X long board. Matrox Solios XA has a universal (3.3 V - 5 V) 64-bit PCI/PCI-X board edge connector. Matrox Solios eA Quad and Dual have a x4 PCIe connector, while Matrox Solios eA Single has a x1 PCIe connector.
  • Page 117 • Supports a 64-bit 66/100/133 MHz 3.3 V PCI-X (or a 32/64-bit 33/66 MHz 3.3 V or 5 V conventional PCI) Host interface for Matrox Solios XA, a x4 or greater PCIe Host interface for Matrox Solios eA, and a x1 or greater Host interface...

  • Page 118: Technical Features Of Matrox Solios Gige

    SRAM. It can also come with 64, 128, or 256 Mbytes of DDR SDRAM. 1. The Processing FPGA option is not available for Matrox Solios eCL/XCL-B, eA/XA Single, nor the 66 MHz version of the Matrox Solios eCL/XCL dual-Base/sin- gle-Medium.

  • Page 119: Electrical Specifications

    Electrical specifications Electrical specifications Matrox Solios eCL/XCL-B (starting from version 000) Operating voltage and Typical: 3.3 V, 1 A: 3.3 W current (eCL-B) Typical 12.0 V, 0.333 A: 4.0 W Total (typical): 3.3 W (by the board), 4.0 W (by PoCL video sources), 7.3 W total Operating voltage and Typical: 3.3 V, 0 A: 0 W...
  • Page 120 • high: 5 mA (min) (6.3 mA recommended) to 15 mA (max) (10 mA recommended). Input voltage (with 511 Ohm series resistor only): low of 0.8 V (max); high of 4.06 V (min) (4.72 V recommended). 1. Operating voltages and currents apply starting from version 100 of Matrox Solios XCL.
  • Page 121 Electrical specifications Matrox Solios eCL/XCL-F (starting from version 200) Operating voltage and Typical: 3.3 V, 2.67 A = 8.82 W current (eCL-F) Typical 12.0 V, 0.21 A =2.48 W Total (typical) = 11.3 W Operating voltage and Typical: 3.3 V, 0.0 A = 0.0 W current (XCL-F) Typical: 5.0 V, 2.1 A = 10.5 W...
  • Page 122 122 Appendix B: Technical information Matrox Solios eA (starting from version 100)/Matrox Solios XA (starting from version 200) Operating voltage Matrox Solios XA Single Matrox Solios XA Dual Matrox Solios XA Quad and current (XA) Typical: 5.0 V, 1.46 A = 7.3 W Typical: 5.0 V, 1.552 A = 7.76 W...
  • Page 123 • high: 5 mA (min) (6.3 mA recommended) to 15 mA (max) (10 mA recommended). Input voltage (with 330 Ohm series resistor only): low of 0.8 V (max); high of 3.15 V (min). 1. Operating voltages and currents apply starting from version 100 of Matrox Solios XA.
  • Page 124 124 Appendix B: Technical information Matrox Solios GigE (starting from version 100) Operating voltage and Typical: 3.3 V, 2.2 A = 7.26 W current Typical 12.0 V, 0.79 A = 9.48 W Total (typical): 16.74 W. I/O Specifications Input signals in 111 Ohm differential termination (typical).

  • Page 125: Dimensions And Environmental Specifications

    Dimensions and environmental specifications • Dimensions: Board Dimensions Matrox Solios eCL/XCL eCL-B 16.76 L x 6.89 H x 0.16 W cm (6.6" x 2.714" x 0.062") from bottom edge of goldfinger to top edge of board. XCL-B 16.76 L x 6.44 H x 0.16 W cm (6.6" x 2.536" x 0.062") from bottom edge of goldfinger to top edge of board.

  • Page 126: Connectors On Matrox Solios Ecl/Xcl-B

    Video Input Connector #0 ❖ Note that the Matrox Solios eCL/XCL-B signal names have a ranking that reflects the number of signals of that type, format, and direction for a path. For example, two TTL and two LVDS auxiliary input signals for path 0 would be named P0_TTL_AUX_IN0, P0_TTL_AUX_IN1, P0_LVDS_AUX_IN0+, and P0_LVDS_AUX_IN1+.

  • Page 127: Camera Link Video Input Connector

    Connectors on Matrox Solios eCL/XCL-B Camera Link video input connector The Camera Link video input connector is a 26-pin high-density mini D ribbon (MDR) connector. It is used to receive video input, timing, and synchronization signals and transmit/receive communication signals between the video source and the frame grabber.

  • Page 128: External Auxiliary I/O Connector 0

    In this case, the DB-9 connector has the same pinout as auxiliary I/O connector 1 (DB-9) on the adapter board of other Matrox Solios eCL/XCL boards. Note however, when using the optional DB-9 connector, some DB-15 signals are not available.
  • Page 129 Connectors on Matrox Solios eCL/XCL-B Pinout Pinout Signal Description DB-15 DB-9 P0_LVDS_AUX_IN0+ LVDS auxiliary input 0 (positive). Supported signals: trigger input 0, field input, user-defined input 5, or quadrature input bit 0. P0_LVDS_AUX_IN0- LVDS auxiliary input 0 (negative). See pin 4 for more information.

  • Page 130: Connectors On Matrox Solios Ecl/Xcl Dual-Base/Single-Medium And Ecl/Xcl-F Boards

    Connector #1 Connector #1 ❖ Note that the Matrox Solios eCL/XCL signal names have a ranking that reflects the number of signals of that type, format, and direction for a path. For example, two TTL and two LVDS auxiliary input signals for path 0 would be named P0_TTL_AUX_IN0, P0_TTL_AUX_IN1, P0_LVDS_AUX_IN0+, and P0_LVDS_AUX_IN1+.

  • Page 131: Camera Link Video Input Connectors

    Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards Camera Link video input connectors The two Camera Link video input connectors are 26-pin high-density mini D ribbon (MDR) connectors. They are used to receive video input, timing, and synchronization signals and transmit/receive communication signals between the video source and the frame grabber.
  • Page 132 3M Interconnect Solutions for Factory Automation, Intercon 1, or other third parties. Note that this cable is not available from Matrox. ❖ If using both Camera Link connectors to connect to the same video source (single-Medium mode or single-Full mode), the cables you choose must be of the same type and length.

  • Page 133: External Auxiliary I/O Connector 0

    Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards External auxiliary I/O connector 0 External auxiliary I/O connector 0 is a high-density DB-44 female connector, located on the bracket of the cable adapter board. It is used to transmit timing and synchronization signals, and transmit/receive auxiliary signals.
  • Page 134 134 Appendix B: Technical information Signal Description Not connected. P0_LVDS_CLK_OUT+ Clock output for acq. path 0 (positive). LVDS_AUX_IN1+ LVDS auxiliary input 1 for an unspecified acq. path (positive). Signals only supported for acq. path 0: user-defined input 11. Signals only supported for acq. path 1: trigger input 1, user-defined input 6, timer clock input, or quadrature input bit 1.
  • Page 135 Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards Signal Description P0_LVDS_HSYNC_OUT- HSYNC output for acq. path 0 (negative). See pin 41 for more information. P0_LVDS_CLK_OUT- Clock output for acq. path 0 (negative). See pin 11 for more information. LVDS_AUX_IN1- LVDS auxiliary input 1 for an unspecified acq.

  • Page 136: External Auxiliary I/O Connector 1

    136 Appendix B: Technical information Signal Description Ground. TTL_AUX_IO_0 TTL auxiliary input/output 0 for an unspecified acq. path. Signals only supported for acq. path 0: exposure output 1, user-defined input/output 4. Signals only supported for acq. path 1: user-defined input/output 7. Signals supported for any acq.
  • Page 137 Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards Signal Description P0_TTL_AUX_IO_0 TTL auxiliary input/output 0 for acq. path 0. Supported signals: exposure output 2, trigger input 0, user-defined input/output 2, field input. P0_OPTO_AUX_IN0- Opto-isolated auxiliary input 0 for acq. path 0 (negative).

  • Page 138: Internal Auxiliary I/O Connector

    138 Appendix B: Technical information Internal auxiliary I/O connector The internal auxiliary I/O connector is a 50-pin low-profile IDC connector. It is used to transmit timing and synchronization signals, and transmit/receive auxiliary signals. The connector is located on the edge of the board, making the signals accessible from inside the computer enclosure.
  • Page 139 Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards Signal Description Signal Description P0_LVDS_AUX_IN1+ LVDS auxiliary input 1 for LVDS_AUX_IN0- LVDS auxiliary input 0 for an acq. path 0 (positive). unspecified acq. path (nega- tive). LVDS_AUX_IN0+ LVDS auxiliary input 0 for an Ground.

  • Page 140: Jtag Connector

    140 Appendix B: Technical information JTAG connector If Matrox Solios eCL/XCL has the optional Processing FPGA, the board features a 10-pin male JTAG connector for debugging and probing internal signals of the FPGA. The pin assignment, as used in JTAG mode, is as follows:...

  • Page 141: Connectors On Matrox Solios Ea/Xa

    Connector #0 Connector #1 ❖ Note that the Matrox Solios eA/XA signal names have a ranking that reflects the number of signals of that type, format, and direction for a path. For example, two TTL and two LVDS auxiliary input signals for path 0 would be named P0_TTL_AUX_IN0, P0_TTL_AUX_IN1, P0_LVDS_AUX_IN0+, and P0_LVDS_AUX_IN1+.

  • Page 142: Analog Video Input Connectors

    (DVI-I to DVI-I or DVI-A to DVI-A cable) if the display board encodes the synchronization signals on the video data (sync on green). Otherwise, you must use the Matrox DVI-TO-8BNC/O cable or a custom cable that re-routes the synchronization signals to the appropriate pins.
  • Page 143 0 (UART) to video source. 1. Note that only signals defined for acquisition path 0 (those that begin with P0) and the grounds (GND) apply to the Matrox Solios eA/XA Single board. Only signals defined for acquisition paths 0 and 1 (P0 and P1) and the grounds (GND) apply to the Matrox Soilios eA/XA Dual.
  • Page 144 144 Appendix B: Technical information The pinout for DVI connector 1 is as follows: Signal Description Signal Description P3_LVDS/TTL_VSYNC_IO- VSYNC input/output for acq. P3_LVDS/TTL_CLK_IO- Clock input/output for acq. path 3 (negative). path 3 (negative). P3_LVDS/TTL_VSYNC_IO+ VSYNC input/output for acq. P3_LVDS/TTL_CLK_IO+ Clock input/output for acq.

  • Page 145: External Auxiliary I/O Connector 0

    1. Note that only signals defined for acquisition path 0 (those that begin with P0) and the grounds (GND) apply to the Matrox Solios eA/XA Single board. Only signals defined for acquisition paths 0 and 1 (P0 and P1) and the grounds (GND) apply to the Matrox Soilios eA/XA Dual.
  • Page 146 146 Appendix B: Technical information The pinout for this connector is as follows. The description of each (positive) auxiliary signal states whether the signal is specific to an acquisition path and the type of signals that can be routed onto it. Signal Description LVDS/TTL_AUX_IN7+...
  • Page 147 Connectors on Matrox Solios eA/XA Signal Description LVDS/TTL_AUX_IN2+ Auxiliary input 2 for an unspecified acq. path (positive). Signals only supported for acq. path 0: user-defined input 4. Signals only supported for acq. path 1: user-defined input 2, or field, data valid, CSYNC, or HSYNC input.
  • Page 148 148 Appendix B: Technical information Signal Description P1_LVDS/TTL_AUX_OUT1- Auxiliary output 1 for acq. path 1 (negative). See pin 11 for more information. LVDS/TTL_AUX_IN1- Auxiliary input 1 for an unspecified acq. path (negative). See pin 12 for more information. P0_LVDS/TTL_AUX_OUT1- Auxiliary output 1 for acq. path 0 (negative). See pin 44 for more information.
  • Page 149 1. Note that only signals defined for acquisition path 0 (those that begin with P0), the common auxiliary input signals ( LVDS/TTL_AUX_), and the grounds (GND) apply to the Matrox Solios eA/XA Single board. Only signals defined for acquisition paths 0 and 1 (P0 or P1), the common auxiliary input signals (LLVDS/TTL_AUX_), and the grounds (GND) apply to the Matrox Solios eA/XA Dual board.

  • Page 150: External Auxiliary I/O Connector 1

    150 Appendix B: Technical information External auxiliary I/O connector 1 External auxiliary I/O connector 1 is a standard DB-9 female connector, located on the bracket of the LVDS cable adapter board. It is used to receive opto-isolated auxiliary input signals. It interfaces with the 50-pin internal auxiliary I/O connector on the board, making the auxiliary signals accessible outside the computer enclosure.

  • Page 151: Internal Auxiliary I/O Connector

    Not connected. 1. Note that only signals defined for acquisition path 0 (those that begin with P0) apply to the Matrox Solios eA/XA Single board. Only signals defined for acquisition paths 0 and 1 (P0 or P1) apply to the Matrox Solios eA/XA Dual board.
  • Page 152 152 Appendix B: Technical information All the signals are LVTTL signals unless otherwise specified. Note that the clock and synchronization output signals are the LVTTL version of those output on the DVI connectors. In addition, you cannot simultaneously receive a clock or synchronization input signal on this connector and receive the same signal from the DVI connectors.
  • Page 153 1. Note that only signals defined for acquisition path 0 (those that begin with P0), the common auxiliary input signals (LVTTL_AUX_), and the grounds (GND) and power supply pins apply to the Matrox Solios eA/XA Single board. Only signals defined for acquisition paths 0 and 1 (P0 or P1), the common auxiliary input signals...

  • Page 154: Jtag Connector

    154 Appendix B: Technical information JTAG connector If Matrox Solios eA/XA has the optional Processing FPGA, the board features a 10-pin male JTAG connector for debugging and probing internal signals of the FPGA. The pin assignment, as used in JTAG mode, is as follows:...

  • Page 155: Connectors On Matrox Solios Gige

    Auxiliary I/O connector ❖ Note that the Matrox Solios GigE signal names have a ranking that reflects the number of signals of that type for a path, regardless of the direction and format. For example, two TTL input and two LVDS auxiliary output signals for path 0 would be named P0_AUX_TTL_IN0, P0_AUX_TTL_IN1, P0_AUX_LVDS_OUT2+, and P0_AUX_LVDS_OUT3+.

  • Page 156: Ethernet Connectors

    156 Appendix B: Technical information Ethernet connectors The four Ethernet connectors are 8-pin connectors that terminate 4 twisted-pair wires. They are used to receive video input signals between the video source and the frame grabber, as per GigE Vision protocol, found in the IEEE 802.3-2002 standard.
  • Page 157 Connectors on Matrox Solios GigE Signal Description AUX(TRIG)_TTL_IO_6 TTL auxiliary 6 (input/output) for an unspecified acq. path. Suppor ted signals: exposure outputs 0-7, timer-trigger input 6, timer-clock input 6, user-defined 6 (input/output). AUX(EXP)_TTL_OUT11 TTL auxiliary 11 (output) an unspecified acq. path.
  • Page 158 158 Appendix B: Technical information Signal Description AUX(EXP)_TTL_OUT13 TTL auxiliary 13 (output) for an unspecified acq. path. Suppor ted signals: exposure outputs 0-7, user-defined 13 (output). Ground. Ground. Not connected. Not connected. Not connected. Not connected. AUX(TRIG)_OPTO_IN1+ Opto-isolated auxiliary 1 (input) for an unspecified acq. path (positive). Suppor ted signals: timer-trigger input 1, timer-clock input 1, user-defined 1 (input).

  • Page 159: Internal Auxiliary I/O Connector

    Connectors on Matrox Solios GigE Internal auxiliary I/O connector The internal auxiliary I/O connector is a 30-pin low-profile IDC connector. It is used to transmit timing and synchronization signals, and transmit/receive auxiliary signals. The connector is located on the top edge of the board, making the signals accessible from inside the computer enclosure.

  • Page 160: Jtag Connector

    (www.digikey.com). JTAG connector If Matrox Solios GigE has the optional Processing FPGA, the board features a 10-pin male JTAG connector for debugging and probing internal signals of the FPGA. The pin assignment, as used in JTAG mode, is as follows:...
  • Page 161 2-pin connector (J2). For further information on debugging with the JTAG connector, refer to the Quartus II documentation from the Altera Corporation. For other debugging information, refer to the Matrox FPGA Developer’s Toolkit for Matrox Solios manual.
  • Page 162 162 Appendix B: Technical information...

  • Page 163: Appendix C: Major Revisions Of Matrox Solios Boards

    Appendix C: Major revisions of Appendix C: Matrox Solios boards This appendix lists the major revisions of the Matrox Solios boards that are RoHS-compliant.

  • Page 164: Major Revisions Of Matrox Solios

    164 Appendix C: Major revisions of Matrox Solios boards Major revisions of Matrox Solios RoHS-compliant versions of Matrox Solios eA/XA Part number Version Description SOL6M1A* First shipping version. Moved to secondary source for A/D. This was done to ensure availability.
  • Page 165 Major revisions of Matrox Solios RoHS-compliant versions of Matrox Solios eA/XA Part number Version Description SOL6M4AE* First shipping version. Upgraded the PCI-X to PCIe bridge to a new version. This was a corrective action. For more information, refer to product bulletin MIPB-67.
  • Page 166 166 Appendix C: Major revisions of Matrox Solios boards RoHS-compliant versions of Matrox Solios eCL/XCL Part number Version Description SOL6MCL* First shipping version. Set a default clock speed to improve testability. Changed product packaging. Changed a TTL buffer of a TTL auxiliary output signal to one with a higher voltage tolerance.
  • Page 167 Major revisions of Matrox Solios RoHS-compliant versions of Matrox Solios eCL/XCL Part number Version Description SOL6MFCE* First shipping version. Replaced the LVDS receiver to suppor t 5 V LVDS auxiliary input signals (required to support most rotary encoders). This was done to enhance the feature set.
  • Page 168 168 Appendix C: Major revisions of Matrox Solios boards RoHS-compliant versions of Matrox Solios GigE Part number Version Description SOL6M4GE* First active-product version. SOL1M4GE* First active-product version.

  • Page 169: Appendix D: Acknowledgments

    Appendix D: Acknowledgments Appendix D: This appendix lists the copyright information regarding third-party material used to implement components on the Matrox Solios board.

  • Page 170: Uart Copyright Information

    170 Appendix D: Acknowledgments UART copyright information The following is the copyright notice for the UART design used on the Matrox Solios boards. Copyright © 2002 Daniel Wallner (jesus@opencores.org) All rights reserved. Redistribution and use in source and synthesized forms, with or without...
  • Page 171 99 COM port 19 composite synchronization signals 77 computer requirements 23 connecting video sources A/D converters, Matrox Solios eA/XA 76 Matrox Solios eA/XA 39 AC coupling, Matrox Solios eA/XA 74 Matrox Solios eCL/XCL 37 acquisition features Matrox Solios GigE 41...
  • Page 172 Major revisions of Matrox Solios 164 defined 105 master mode 77 frame Matrox eCL/XCL defined 105 lookup tables 61 Matrox Inspector 22 Matrox Intellicam 23 Matrox Solios eA/XA 15 gain controller, Matrox Solios eA/XA 75 A/D converters 76 global information 110...
  • Page 173 Rotary encoder 69 acquisition rate 87 RS-232 compatible serial interfaces 19 auxiliary signals 88 connectors 155 dimensions 125 sampling rates, Matrox Solios eA/XA 73 exposure timers 93 SDRAM 19 supported video sources 87 defined 104 video timing information 87 signal coupling, Matrox Solios eA/XA 74...
  • Page 174 Matrox Solios eA/XA 116 Matrox Solios eCL/XCL 111 Matrox Solios eCL/XCL-B 111 Matrox Solios eCL/XCL-F 111 technical specifications 110 transfer to/from the Host buffer data 21 triggers Matrox Solios eA/XA 84 Matrox Solios eCL/XCL 68 UART 19 defined 108...

  • Page 175: Regulatory Compliance

    Regulatory Compliance FCC Compliance Statement Warning Changes or modifications to these units not expressly approved by the party responsible for the compliance could void the user's authority to operate this equipment. The use of shielded cables for connections of these devices to other peripherals is required to meet the regulatory requirements.

  • Page 176: Directive On Waste Electrical And Electronic Equipment (Weee)

    Bitte wenden Sie sich an dem Matrox-Website (www.matrox.com/environment/weee) für Recycling Informationen. (Italiano) Informazioni per gli utenti europei – Direttiva sui rifiuti di apparecchiature elettriche ed elettroniche (RAEE) Si prega di riferirsi al sito Web Matrox (www.matrox.com/environment/weee) per le informazioni di riciclaggio.

  • Page 177: China Rohs Hazardous Materials Disclosure Tables

    China RoHS Hazardous Materials Disclosure Tables Material disclosure table for SOL6MCLDBE* Cr(VI) PBDE YPDSB009FS0S2 D-SUB YSF0440X18750 YIF00030C08B0 YDK0340M0 YDK140M0 YIC11486XXXM0 YIL01085CXXM1 YQMN4884M0 YRLR075C01M0 YRSR000A00M0...
  • Page 178 Material disclosure table for SOL6MCL* Cr(VI) PBDE YPDSB009FS0S2 D-SUB YSF0440X18750 YIF00030C08B0 YCCT10WMM0 YDR0001M0 YIC11486XXXM0 YIL01117CXXM4 YIL01580CXXM1 YQMN9926M2 YRLR075C01M0...
  • Page 179 Material disclosure table for SOL6M4GE* Cr(VI) PBDE YIF00040C07B0 YDK140M0 YQMN4884M0 YRSR000A00M0 YPRJ45010FS0S0...
  • Page 180 Material disclosure table for SOL6M4GE30546* Cr(VI) PBDE YIF00040C07B0 YDK140M0 YQMN4884M0 YRSR000A00M0 YIF00030C05B1 YPRJ45010FS0S0...
  • Page 181 Material disclosure table for SOL6M4AE* Cr(VI) PBDE YSF0440X18750 YDK0340M0 YDK140M0 YIC11486XXXM0 YIL01085CXXM1 YLCU820M1 YQMN4884M0 YRLR075C01M0 YRSR000A00M0 YLCU470M0 YLCU680M2 YLC4U70M1 YLC6U80M2 YIF00030C08B0 YPDSB009FS0S2 D-SUB YRSK100B01M0 YRS49R9A01M0...
  • Page 182 Material disclosure table for SOL6M4A* Cr(VI) PBDE YIC11486XXXM0 YLCU470M0 YLCU680M2 YLC4U70M1 YLC6U80M2 YSF0440X18750 YIF00030C08B0 YDK140M0 YDR0001M0 YIL01117CXXM4 YIL01580CXXM1 YLCU820M1 YQMN9926M2 YRLR075C01M0 YPDSB009FS0S2 D-SUB YRSK100B01M0 YRS49R9A01M0...
  • Page 183 Material disclosure table for SOL6M4A30746* Cr(VI) PBDE YIC11486XXXM0 YLCU470M0 YLCU680M2 YLC4U70M1 YLC6U80M2 YSF0440X18750 YIF00030C07B0 YDK140M0 YDR0001M0 YIL01117CXXM4 YIL01580CXXM1 YLCU820M1 YQMN9926M2 YRLR075C01M0 YPDSB009FS0S2 D-SUB YRSK100B01M0 YRS49R9A01M0...
  • Page 184 Material disclosure table for SOL6M2AE* Cr(VI) PBDE YSF0440X18750 YDK0340M0 YDK140M0 YIC11486XXXM0 YIL01085CXXM1 YLCU820M1 YQMN4884M0 YRLR075C01M0 YRSR000A00M0 YLCU470M0 YLCU680M2 YLC4U70M1 YLC6U80M2 YIF00030C08B0 YPDSB009FS0S2 D-SUB YRSK100B01M0 YRS49R9A01M0...
  • Page 185 Material disclosure table for SOL6M2A* Cr(VI) PBDE YIC11486XXXM0 YLCU470M0 YLCU680M2 YLC4U70M1 YLC6U80M2 YSF0440X18750 YIF00030C08B0 YDK140M0 YDR0001M0 YIL01117CXXM4 YIL01580CXXM1 YLCU820M1 YQMN9926M2 YRLR075C01M0 YPDSB009FS0S2 D-SUB YRSK100B01M0 YRS49R9A01M0...
  • Page 186 Material disclosure table for SOL6M1AS* Cr(VI) PBDE YSF0440X18750 YDK0340M0 YDK140M0 YIC11486XXXM0 YIL01085CXXM1 YLCU820M1 YQMN4884M0 YRLR075C01M0 YRSR000A00M0 YLCU470M0 YLCU680M2 YLC4U70M1 YLC6U80M2 YIF00030C08B0 YPDSB009FS0S2 D-SUB YRSK100B01M0 YRS49R9A01M0...
  • Page 187 Material disclosure table for SOL6M1A* Cr(VI) PBDE YIC11486XXXM0 YLCU470M0 YLCU680M2 YLC4U70M1 YLC6U80M2 YSF0440X18750 YIF00030C08B0 YDK140M0 YDR0001M0 YIL01117CXXM4 YIL01580CXXM1 YLCU820M1 YQMN9926M2 YRLR075C01M0 YPDSB009FS0S2 D-SUB YRSK100B01M0 YRS49R9A01M0...
  • Page 188 Material disclosure table for SOL6MFCFE* Cr(VI) PBDE YPDSB009FS0S2 D-SUB YSF0440X18750 YDK0340M0 YDK140M0 YIC11486XXXM0 YIL01085CXXM1 YQMN4884M0 YRLR075C01M0 YRSR000A00M0 YIF00030C05B1...
  • Page 189 Material disclosure table for SOL6MFCF* Cr(VI) PBDE YPDSB009FS0S2 D-SUB YSF0440X18750 YCCT10WMM0 YDR0001M0 YIC11486XXXM0 YIL01117CXXM4 YIL01580CXXM1 YQMN9926M2 YRLR075C01M0 YIF00030C05B1...
  • Page 190 Material disclosure table for SOL6MFCE* Cr(VI) PBDE YPDSB009FS0S2 D-SUB YSF0440X18750 YIF00030C07B0 YDK0340M0 YDK140M0 YIC11486XXXM0 YIL01085CXXM1 YQMN4884M0 YRLR075C01M0 YRSR000A00M0...
  • Page 191 Material disclosure table for SOL6MFC* Cr(VI) PBDE YPDSB009FS0S2 D-SUB YSF0440X18750 YIF00030C07B0 YCCT10WMM0 YDR0001M0 YIC11486XXXM0 YIL01117CXXM4 YIL01580CXXM1 YQMN9926M2 YRLR075C01M0...
  • Page 192 Material disclosure table for SOL6MCLE* Cr(VI) PBDE YPDSB009FS0S2 D-SUB YSF0440X18750 YIF00030C08B0 YDK0340M0 YDK140M0 YIC11486XXXM0 YIL01085CXXM1 YQMN4884M0 YRLR075C01M0 YRSR000A00M0...

  • Page 193: Product Support

    Software Package provided by Matrox is not covered under this limited warranty. 1.3 Matrox's limited warranty covers only those defects which arise as a result of normal use of the Matrox Hardware and does not apply to any damage which arises from: i) improper or inadequate maintenance;...
  • Page 194 (including theft); 1.4 If Matrox receives from the Licensee, during the applicable warranty period, notice of a defect in the Matrox Hardware, which is subsequently confirmed by Matrox, Matrox shall at its sole option, either i) repair the defect using new or refurbished parts and return the repaired Matrox Hardware within a reasonable delay;...
  • Page 195 Matrox Hardware. 1.13 If the Purchaser needs to return Matrox Hardware, it must pack the Matrox Product in its original box and return it to its Matrox dealer where the Matrox Product was purchased, together with the proof of purchase. The Matrox dealer will return the Matrox Product for the Purchaser.

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