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3. Device SPI operations
WIZ610io is controlled by a set of instruction that is sent from a external host ,
commonly referred to as the SPI Master. The SPI Master communicates with
W6100 via the SPI bus, which is composed of four signal lines: Slave Chip Select
(nSCS), Serial Clock (SCLK), MOSI (Master Out Slave In) and MISO (Master In
Slave Out).
The SPI protocol defines four modes for its operation (Mode 0-3). Each mode
differs according to the SCLK polarity and phase - how the polarity and phase
control the flow of data on the SPI bus. The W6100 operates as SPI Slave device
and supports the most common modes - SPI Mode 0 and 3.
The only difference between SPI Mode 0 and 3 is the polarity of the SCLK signal
at the inactive state. With SPI Mode 0 and 3, data is always latched in on the
rising edge of SCLK and always output on the falling edge of SCLK.
3.1 Process of using general SPI Master device
1. Configure Input/Output direction on SPI Master Device pins.
2. Configure nSCS as 'High' on inactive
3. Write target address for transmission on SPDR register (SPI Data Register).
4. Write OP code and data length for transmission on SPDR register.
5. Write desired data for transmission on SPDR register.
6. Configure nSCS as 'Low' (data transfer start)
7. Wait for reception complete
8. If all data transmission ends, configure nSCS as 'High'
WIZ610io User Manual (WIZnet Co.,Ltd.)
0
Address
OP Code (1bit) + data length n (16bit)
data n-1
0 1 2 3 4 5
6
Bit
Byte
< W6100 SPI Frame Format >
1
data1
7
Byte
2
6
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