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Texas Instruments C2620 Technical Reference Manual

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CC26xx SimpleLink™ Wireless MCU

Technical Reference Manual

Literature Number: SWCU117A

February 2015 – Revised March 2015

Table of Contents

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Summary of Contents for Texas Instruments C2620

Page 1 CC26xx SimpleLink™ Wireless MCU Technical Reference Manual Literature Number: SWCU117A February 2015 – Revised March 2015...
Page 2: Table Of Contents
2.7.2 CPU_DWT Registers ..................... 2.7.3 CPU_FPB Registers .................... 2.7.4 CPU_SCS Registers .................... 2.7.5 CPU_TPIU Registers ....................Cortex™-M3 Peripherals .................. Cortex™-M3 Peripherals Introduction Contents SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 3 Debug Features Supported Through WUC TAP ......................Profiler Register ................. Power, Reset, and Clock Management ........................ Introduction ....................6.1.1 System CPU Mode SWCU117A – February 2015 – Revised March 2015 Contents Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 4 ....................9.2.1 FCFG1 Registers ........................Cryptography ..................10.1 AES Cryptoprocessor Overview ..................10.1.1 Functional Description ..............10.1.2 Power Management and Sleep Modes Contents SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 5 1073 ....................13.1 General-Purpose Timers 1074 ......................13.2 Block Diagram 1074 ....................13.3 Functional Description 1075 ..................13.3.1 GPTM Reset Conditions 1076 SWCU117A – February 2015 – Revised March 2015 Contents Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 6 ................. 17.2.1 Alias of Commonly Used Registers 1189 ....................... 17.3 IO Mapping 1191 ........................17.4 Modules 1191 ....................17.4.1 Sensor Controller 1191 Contents SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 7 ......................19.5 Interface to DMA 1333 ..................19.6 Initialization and Configuration 1334 ....................... 19.7 UARTS Registers 1335 ....................19.7.1 UART Registers 1336 SWCU117A – February 2015 – Revised March 2015 Contents Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 8 22.9.2 Termination Sequence 1422 ......................22.10 I2S Registers 1422 ....................22.10.1 I2S Registers 1423 ..........................Radio 1454 ........................23.1 RF Core 1455 Contents SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 9 23.6.5 Immediate Commands 1546 ......................23.7 Radio Registers 1546 ..................23.7.1 RFC_DBELL Registers 1547 ..................23.7.2 RFC_PWR Registers 1565 ..................23.7.3 RFC_RAT Registers 1568 SWCU117A – February 2015 – Revised March 2015 Contents Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 10: Revision History
Changed I2C registers 1391 ....................... • Changed I2S registers 1422 ......................• Changed Radio chapter 1455 ......................• Changed Radio registers 1546 Revision History SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 11: Preface
SWCU117A – February 2015 – Revised March 2015 Read This First Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 12 TI's Terms of Use. TI Embedded Processors Wiki – Texas Instruments Embedded Processors Wiki TI BLE Wiki – Texas Instruments Bluetooth Smart Wiki Established to assist developers using the many Embedded Processors from TI to get started, help each other innovate, and foster the growth of general knowledge about the hardware and software surrounding these devices.
Page 13: Architectural Overview
CC26xx device family ideal for single-chip implementation or network processor implementations of lower power RF nodes..........................Topic Page .................... Target Applications ......................Overview ................... Functional Overview SWCU117A – February 2015 – Revised March 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 14: Target Applications
• Medical • Remote controls • Wireless sensor networks Overview Figure 1-1 shows the different building blocks of the CC26xx device. Architectural Overview SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 15 Overview www.ti.com Figure 1-1. CC26xx Block Diagram SWCU117A – February 2015 – Revised March 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 16 [RTC]), with interrupt and 20KB of RAM with retention in all power modes positions the CC26xx microcontroller perfectly for battery applications. Architectural Overview SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 17: Functional Overview
Compact JTAG interface reduces the number of pins required for debugging • Ultra-low power consumption with integrated sleep modes • Up to 48-MHz operation SWCU117A – February 2015 – Revised March 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 18: On-Chip Memory
Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller. Architectural Overview SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 19: Radio
DMA capability. • CCM, CTR, CBC-MAC, ECB modes of operation • 118 Mbps throughput • Secure key storage memory • Low latency SWCU117A – February 2015 – Revised March 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 20: General-Purpose Timers
Channels in the μDMA are dedicated for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory, as the peripheral is ready to transfer more data. Architectural Overview SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 21: System Control And Clock
The CC26xx device supports both asynchronous and synchronous serial communications including: • UART • • • SSI (SPI) The following sections provide more detail on each of the communications functions. SWCU117A – February 2015 – Revised March 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 22 – Supports simultaneous master and slave operation • Four I C modes: – Master transmit – Master receive – Slave transmit – Slave receive Architectural Overview SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 23 – Transmit single request asserted when there is space in the FIFO; burst request is asserted when FIFO contains four entries SWCU117A – February 2015 – Revised March 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 24: Programmable Ios
The sensor controller will take care of baseline tracking, hysteresis, filtering, and other related functions. Architectural Overview SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 25: Random Number Generator
1.3.13.1 Supply System There are several voltage levels in use on the CC26xx family. Figure 1-2 shows an overview of the supply system. SWCU117A – February 2015 – Revised March 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 26 VDDR pins. See the reference designs and Section 1.3.13.2, DC-DC Converter, for further details. Architectural Overview SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 27 It is possible to check that the device has booted properly into external regulator mode by reading the [AON_SYSCTL:PWRCTL:EXT_REG_MODE] register field. SWCU117A – February 2015 – Revised March 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 28: The Cortex-M3 Processor
....................Block Diagram ......................Overview ................... Programming Model .................. Coretex-M3 Core Registers ..................Instruction Set Summary ................Cortex-M3 Processor Registers The Cortex-M3 Processor SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 29: The Cortex-M3 Processor Introduction
The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. SWCU117A – February 2015 – Revised March 2015 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 30: Overview
To enable simple and cost-effective profiling of the system trace events, a serial wire viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through one pin. The Cortex-M3 Processor SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 31: Trace Port Interface Unit
Section 2.5, Coretex-M3 Core Registers. SWCU117A – February 2015 – Revised March 2015 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 32: Processor Mode And Privilege Levels For Software Execution
16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. For more information, see the Cortex™-M3 Instruction Set Technical User's Manual. The Cortex-M3 Processor SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 33: Coretex-M3 Core Registers
PC (R15) Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL Control register Banked version of SP SWCU117A – February 2015 – Revised March 2015 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 34: Core Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31:0 DATA Register data — The Cortex-M3 Processor SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 35 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31:0 DATA Register data — SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 36 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31:0 DATA Register data — SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 37 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31:0 DATA Register data — SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 38 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31:0 DATA Register data — SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 39 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LINK Bits Field Name Description Type Reset 31:0 LINK This field is the return address. 0xFFFF FFFF SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 40 Reads of the EPSR bits directly using the MSR instruction return 0, and the processor ignores writes to these bits. The processor ignores writes to the IPSR bits. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 41 The value of this bit is meaningful only when accessing PSR or APSR. APSR Overflow Flag Value Description SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 42 IPSR ISR Number 0x00 This field contains the exception type number of the current ISR. Value Description 0x00 Thread mode 0x01 Reserved 0x02 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 43 Reserved 0x7F For more information, see Section 4.1.2, Exception Types. The value of this field is meaningful only when accessing PSR or IPSR. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 44 PRIMASK Priority Mask Value Description Prevents the activation of all exceptions with configurable priority. No effect. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 45 Prevents the activation of all exceptions except for NMI. No effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 46 All exceptions with priority levels 5–7 are masked. All exceptions with priority levels 6 and 7 are masked. All exceptions with priority level 7 are masked. RESERVED Reserved SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 47: Instruction Set Summary
Table 2-25 is copied from the Cortex™-M3 Instruction Set Technical User's Manual. Changes made in the manual must be made in Table 2-25. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 48 Rt, [Rn, #offset] – halfword LDRT Rt, [Rn, #offset] Load register with word – LSL, LSLS Rd, Rm, <Rs|#n> Logical shift left N, Z, C SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 49 Rt, Rt, [Rn {, #offset}] Store register exclusive – STREXB Rd, Rt, [Rn] Store register exclusive byte – Store register exclusive STREXH Rd, Rt, [Rn] – halfword SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 50: Cortex-M3 Processor Registers
UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword – – Wait for event – – Wait for interrupt – Cortex-M3 Processor Registers SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 51: Cpu_Itm Registers
Trace Enable Section 2.7.1.33 E40h Trace Privilege Section 2.7.1.34 E80h Trace Control Section 2.7.1.35 FB0h Lock Access Section 2.7.1.36 FB4h Lock Status Section 2.7.1.37 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 52 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 53 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 54 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 55 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 56 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 57 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 58 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 59 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 60 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 61 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 62 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 63 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 64 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 65 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 66 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 67 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 68 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 69 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 70 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 71 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 72 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 73 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 74 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 75 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 76 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 77 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 78 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 79 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 80 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 81 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 82 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 83 ITM port is used concurrently by interrupts or other threads. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 84 Bit mask to enable tracing on ITM stimulus port 12. STIMENA11 Bit mask to enable tracing on ITM stimulus port 11. STIMENA10 Bit mask to enable tracing on ITM stimulus port 10. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 85 Bit mask to enable tracing on ITM stimulus port 2. STIMENA1 Bit mask to enable tracing on ITM stimulus port 1. STIMENA0 Bit mask to enable tracing on ITM stimulus port 0. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 86 23. Bit [3] enables stimulus ports 24, 25, ..., and 31. 0: User access allowed to stimulus ports 1: Privileged access only to stimulus ports SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 87 Enables the DWT stimulus (hardware event packet emission to the TPIU from the DWT) SYNCENA Enables synchronization packet transmission for a synchronous TPIU. CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization speed. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 88 ITM is idle. ITMENA Enables ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 89 LOCK_ACCESS A privileged write of 0xC5ACCE55 enables more write access to Control Registers TER, TPR and TCR. An invalid write removes write access. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 90 Write access to component is blocked. All writes are ignored, reads are permitted. PRESENT Indicates that a lock mechanism exists for this component. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 91 Cortex-M3 Processor Registers www.ti.com SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 92: Cpu_Dwt Registers
Mask 2 Section 2.7.2.16 FUNCTION2 Function 2 Section 2.7.2.17 COMP3 Comparator 3 Section 2.7.2.18 MASK3 Mask 3 Section 2.7.2.19 FUNCTION3 Function 3 Section 2.7.2.20 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 93 (every 256 cycles of multi-cycle instructions). 0: CPI counter events disabled. 1: CPI counter events enabled. EXCTRCENA Enables Interrupt event tracing. 0: Interrupt event trace disabled. 1: Interrupt event trace enabled. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 94 Enable CYCCNT, allowing it to increment and generate synchronization and count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 95 (this counter will not advance in power modes where free- running clock to CPU stops). It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 96 If CTRL.CPIEVTENA is set, an event is emitted when the counter overflows. This counter initializes to 0 when it is enabled using CTRL.CPIEVTENA. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 97 An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 98 CPU's free-running clock. In some power modes the free-running clock to CPU is gated to minimize power consumption. This means that the sleep counter will be invalid in these power modes. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 99 An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 100 FOLDCNT This counts the total number folded instructions. This counter initializes to 0 when it is enabled using CTRL.FOLDEVTENA. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 101 Table 2-72. PCSR Register Field Descriptions Field Type Reset Description 31-0 EIASAMPLE Execution instruction address sample, or 0xFFFFFFFF if the core is halted. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 102 Reference value to compare against PC or the data address as given by FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler Counter (CYCCNT). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 103 So, if COMP0 is 3, this matches a word access of 0, because 3 would be within the word. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 104 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 105 Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 106 Reference value to compare against PC or the data address as given by FUNCTION1. Comparator 1 can also compare data values. So this register can contain reference values for data matching. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 107 So, if COMP1 is 3, this matches a word access of 0, because 3 would be within the word. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 108 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 109 Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 110 Table 2-79. COMP2 Register Field Descriptions Field Type Reset Description 31-0 COMP Reference value to compare against PC or the data address as given by FUNCTION2. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 111 So, if COMP2 is 3, this matches a word access of 0, because 3 would be within the word. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 112 Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 113 Table 2-82. COMP3 Register Field Descriptions Field Type Reset Description 31-0 COMP Reference value to compare against PC or the data address as given by FUNCTION3. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 114 So, if COMP3 is 3, this matches a word access of 0, because 3 would be within the word. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 115 Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 116 Cortex-M3 Processor Registers www.ti.com SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 117: Cpu_Fpb Registers
Comparator 3 Section 2.7.3.6 COMP4 Comparator 4 Section 2.7.3.7 COMP5 Comparator 5 Section 2.7.3.8 COMP6 Comparator 6 Section 2.7.3.9 COMP7 Comparator 7 Section 2.7.3.10 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 118 '1'. This bit always reads 0. ENABLE Flash patch unit enable bit 0x0: Flash patch unit disabled 0x1: Flash patch unit enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 119 This field always reads 3'b001. Writing to this field is ignored. 28-5 REMAP Remap base address field. RESERVED This field always reads 0. Writing to this field is ignored. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 120 Compare and remap enable comparator 0. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 0 disabled 0x1: Compare and remap for comparator 0 enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 121 Compare and remap enable comparator 1. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 1 disabled 0x1: Compare and remap for comparator 1 enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 122 Compare and remap enable comparator 2. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 2 disabled 0x1: Compare and remap for comparator 2 enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 123 Compare and remap enable comparator 3. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 3 disabled 0x1: Compare and remap for comparator 3 enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 124 Compare and remap enable comparator 4. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 4 disabled 0x1: Compare and remap for comparator 4 enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 125 Compare and remap enable comparator 5. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 5 disabled 0x1: Compare and remap for comparator 5 enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 126 Compare and remap enable comparator 6. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 6 disabled 0x1: Compare and remap for comparator 6 enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 127 Compare and remap enable comparator 7. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 7 disabled 0x1: Compare and remap for comparator 7 enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 128 Cortex-M3 Processor Registers www.ti.com SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 129: Cpu_Scs Registers
Section 2.7.4.41 D40h ID_PFR0 Processor Feature 0 Section 2.7.4.42 D44h ID_PFR1 Processor Feature 1 Section 2.7.4.43 D48h ID_DFR0 Debug Feature 0 Section 2.7.4.44 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 130 DCRDR Debug Core Register Data Section 2.7.4.58 DFCh DEMCR Debug Exception and Monitor Control Section 2.7.4.59 F00h STIR Software Trigger Interrupt Section 2.7.4.60 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 131 Total number of interrupt lines in groups of 32. 0: 0...32 1: 33...64 2: 65...96 3: 97...128 4: 129...160 5: 161...192 6: 193...224 7: 225...256 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 132 DISMCYCINT Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 133 STRVR.RELOAD and then begins counting down. On reaching 0, it sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads STRVR.RELOAD again, and begins counting. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 134 23-0 RELOAD Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 135 Writing to it with any value clears the register to 0. Clearing this register also clears STCSR.COUNTFLAG. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 136 An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. The value read is valid only when core clock is at 48MHz. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 137 Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 138 Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 139 Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 140 Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 141 Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 142 Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 143 Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 144 Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 145 Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 146 Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 147 Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 148 Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 149 Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 150 Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 151 Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 152 Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 153 Reading 0 from this bit implies that interrupt line 21 is not active. Reading 1 from this bit implies that the interrupt line 21 is active (See EVENT:CPUIRQSEL21.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 154 Reading 0 from this bit implies that interrupt line 3 is not active. Reading 1 from this bit implies that the interrupt line 3 is active (See EVENT:CPUIRQSEL3.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 155 Reading 0 from this bit implies that interrupt line 0 is not active. Reading 1 from this bit implies that the interrupt line 0 is active (See EVENT:CPUIRQSEL0.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 156 Reading 0 from this bit implies that interrupt line 32 is not active. Reading 1 from this bit implies that the interrupt line 32 is active (See EVENT:CPUIRQSEL32.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 157 Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). 15-8 PRI_1 Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). PRI_0 Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 158 Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). 15-8 PRI_5 Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). PRI_4 Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 159 Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). 15-8 PRI_9 Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). PRI_8 Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 160 Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). 15-8 PRI_13 Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). PRI_12 Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 161 Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). 15-8 PRI_17 Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). PRI_16 Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 162 Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). 15-8 PRI_21 Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). PRI_20 Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 163 Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). 15-8 PRI_25 Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). PRI_24 Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 164 Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). 15-8 PRI_29 Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). PRI_28 Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 165 15-8 PRI_33 Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). PRI_32 Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 166 VARIANT Implementation defined variant number. 19-16 CONSTANT Reads as 0xF 15-4 PARTNO C23h Number of processor within family. REVISION Implementation defined revision number. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 167 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. VECTACTIVE Active ISR number field. Reset clears this field. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 168 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 169 1 only when the core is halted. The bit self-clears. Writing this bit to 1 while core is not halted may result in unpredictable behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 170 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 171 User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception, which is associated with the Main stack pointer. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 172 LDR with PC as a destination. - BX with any register. The value written to the PC is intercepted and is referred to as the EXC_RETURN value. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 173 23-16 PRI_6 Priority of system handler 6. UsageFault 15-8 PRI_5 Priority of system handler 5: BusFault PRI_4 Priority of system handler 4: MemManage SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 174 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 175 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. PRI_12 Priority of system handler 12. Debug Monitor SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 176 1h = Exception is pending. SYSTICKACT SysTick active flag. 0x0: Not active 0x1: Active 0h = Exception is not active 1h = Exception is active SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 177 0h = Exception is not active 1h = Exception is active MEMFAULTACT MemManage exception active 0h = Exception is not active 1h = Exception is active SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 178 This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 179 XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 180 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 181 HALTED Halt request flag. The processor is halted on the next instruction. 0x0: No halt request 0x1: Halt requested by NVIC, including step SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 182 Flags CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with CFSR.MMARVALIDindicate the cause of the fault. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 183 Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the fault. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 184 Type Reset Description 31-0 IMPDEF Implementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 185 32-bit basic instructions cannot.) 0x3: Thumb-2 encoding with all Thumb-2 basic instructions STATE0 State0 (T-bit == 0) 0x0: No ARM encoding 0x1: N/A SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 186 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 187 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 188 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 189 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 190 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 191 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 192 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 193 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 194 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 195 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 196 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 197 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 198 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 199 Software should not rely on the value of a reserved. When writing to this register, 0x5 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 200 C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will be unknown to software when C_DEBUGEN = 0. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 201 DebugReturnAddress 0x10: XPSR/flags, execution state information, and exception number 0x11: MSP (Main SP) 0x12: PSP (Process SP) 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 202 This enables flags and bits to acknowledge state and indicate if commands have been accepted to, replied to, or accepted and replied to. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 203 It is only reset by a power-on reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 204 VC_CORERESET Reset Vector Catch. Halt running system if Core reset occurs. Ignored when DHCSR.C_DEBUGEN is cleared. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 205 Interrupt ID field. Writing a value to this bit-field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 206 Cortex-M3 Processor Registers www.ti.com SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 207: Cpu_Tpiu Registers
Claim Tag Set Section 2.7.5.9 FA4h CLAIMTAG Current Claim Tag Section 2.7.5.10 FA4h CLAIMCLR Claim Tag Clear Section 2.7.5.11 FC8h DEVID Device ID Section 2.7.5.12 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 208 3-bit port size support 0x0: Not supported 0x1: Supported 2-bit port size support 0x0: Not supported 0x1: Supported 1-bit port size support 0x0: Not supported 0x1: Supported SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 209 1-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 210 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12-0 PRESCALER Divisor for input trace clock is (PRESCALER + 1). SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 211 PROTOCOL Trace output protocol 0h = TracePort mode 1h = SerialWire Output (Manchester). This is the reset value. 2h = SerialWire Output (NRZ) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 212 FTNONSTOP 0: Formatter can be stopped 1: Formatter cannot be stopped RESERVED This field always reads as zero SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 213 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 214 The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 215 0: This claim tag bit is not implemented 1: This claim tag bit is not implemented The behavior when writing to this register is described in CLAIMSET. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 216 0: No effect 1: Set this bit in the claim tag The behavior when reading from this location is described in CLAIMMASK. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 217 Claim Tag value. Reading CLAIMMASK determines how many bits from this register must be used. The behavior when writing to this register is described in CLAIMCLR. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 218 0: No effect 1: Clear this bit in the claim tag. The behavior when reading from this location is described in CLAIMTAG. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 219 Type Reset Description 31-0 DEVID CA0h This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no ETM present. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 220: Cortex™-M3 Peripherals
SWCU117A – February 2015 – Revised March 2015 Cortex™-M3 Peripherals This chapter describes the Cortex™-M3 peripherals..........................Topic Page ..............Cortex™-M3 Peripherals Introduction ..................Functional Description Cortex™-M3 Peripherals SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 221: Cortex™-M3 Peripherals Introduction
A high-speed alarm timer using the system clock • A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and SWCU117A – February 2015 – Revised March 2015 Cortex™-M3 Peripherals Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 222: Nvic
ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. Cortex™-M3 Peripherals SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 223: System Control Block (Scb)
The FPB implements hardware breakpoints and patches code and data from Code space to System space. A full FPB unit contains: SWCU117A – February 2015 – Revised March 2015 Cortex™-M3 Peripherals Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 224: Trace Port Interface Unit (Tpiu)
The DWT to generate PC samples at defined intervals, and to generate interrupt event information.It can also provide periodic requests for protocol synchronization to the ITM and the TPIU. Cortex™-M3 Peripherals SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 225 0xe000 0000 CPU_ROM_TABLE Cortex-M's ROM Table 0xe00f f000 CPU_SCS Cortex-M's System Control Space 0xe000 e000 CPU_TIPROP Texas Instruments' Proprietary Registers for Cortex-M 0xe00f e000 CPU_TPIU Cortex-M's Trace Port Interface Unit 0xe004 0000 FCFG1 Factory Configuration Area 1 0x5000 1000 FCFG2...
Page 226 Micro Direct Memory Access Controller 0 0x4002 0000 vims Versatile Instruction Memory System Control 0x4003 4000 Watchdog Timer 0x4008 0000 Cortex™-M3 Peripherals SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 227: Interrupts And Events
Exception Model ....................Fault Handling ..................... Event Fabric ..................... AON Event Fabric ..................... MCU Event Fabric ................. Interrupts and Events Registers SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 228: Exception Model
Hard faults have a fixed priority of –1, meaning they have higher priority than any exception with configurable priority. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 229 Synchronous – – – Reserved 0 is the default priority for all the programmable priorities. Section 4.1.4. See CM3_SCS:SHPR 1. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 230 AUX ADC new sample 0x0000 00C0 available or ADC DMA done, ADC underflow and overflow 0x0000 00C4 True random number generator Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 231: Exception Handlers
0x0000 0200 to 0x3FFF FE00. When configuring the [CM3_SCS:VTOR] register, the offset must be aligned on a 512-byte boundary. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 232: Exception Priorities
If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 233: Exception Entry And Return
When the late-arriving exception returns from the exception handler, the normal tail-chaining rules apply. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 234 EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 235: Fault Handling
Trying to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 236: Fault Escalation And Hard Faults
The processor enters a lockup state if a hard fault occurs when executing the hard fault handlers. In a CC26xx device, a lockup state resets the system. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 237: Event Fabric
SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 238: Event Fabric Overview
The AON event fabric resides in the AON power domain where the wake-up controller, the debug subsystem, the AUX domain, and the real-time clock (RTC) reside. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 239: Common Input Event List
ID. By default, these IDs are set to 63 (NULL, no event), where the lines always stay logic low. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 240: Mcu Event Fabric
For more information on the remaining subscribers, refer to the specific peripheral chapters for the appropriate consumer (peripheral) for that specific subscriber. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 241: Common Input Event List
AUX domain wake-up control [AON_EVENT:AUXWUSEL.*] AUX software event 1, triggered by [AUX_EVCTL:SWEVSET.SWEV1], 0x1D AUX_SWEV1 also available as AUX_EVENT2 AON wake-up event. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 242 GPT1B compare event. Configured by [GPT1:TBMR.TCACT]. 0x41 GPT2A_CMP GPT2A compare event. Configured by [GPT2:TAMR.TCACT]. 0x42 GPT2B_CMP GPT2B compare event. Configured by [GPT2:TBMR.TCACT]. 242 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 243 Software event 1, triggered by [SWEV.SWEV1] 0x66 SWEV2 Software event 2, triggered by [SWEV.SWEV2] 0x67 SWEV3 Software event 3, triggered by [SWEV.SWEV3] SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 244: Event Subscribers
The following three subscribers are described as they are related to the system CPU and CPU interrupts: • System CPU • Nonmaskable Interrupt (NMI) to System CPU • Freeze Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 245: Interrupts And Events Registers
[EVENT_FRZSUB0] register. Table 4-9. Freeze Subscriber Event Selection Event No. Event Enumeration NONE 0x78 CPU_HALTED 0x79 ALWAYS_ACTIVE Interrupts and Events Registers SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 246: Aon_Event Registers
Section 4.6.1.2 EVTOMCUSEL Event Selector For MCU Event Fabric Section 4.6.1.3 RTCSEL RTC Capture Event Selector For AON_RTC Section 4.6.1.4 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 247 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 248 2Eh = AUX Software triggered event #2. Triggered by [AUX_EVCTL.SWEVSET.SWEV2] 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 249 25h = RTC channel 2 event 26h = RTC channel 0 - delayed event 27h = RTC channel 1 - delayed event SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 250 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 251 2Eh = AUX Software triggered event #2. Triggered by [AUX_EVCTL.SWEVSET.SWEV2] 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 252 25h = RTC channel 2 event 26h = RTC channel 0 - delayed event 27h = RTC channel 1 - delayed event Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 253 **AUX ** Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX 3Fh = No event, always low SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 254 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 255 2Eh = AUX Software triggered event #2. Triggered by [AUX_EVCTL.SWEVSET.SWEV2] 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 256 25h = RTC channel 2 event 26h = RTC channel 0 - delayed event 27h = RTC channel 1 - delayed event Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 257 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 258 2Eh = AUX Software triggered event #2. Triggered by [AUX_EVCTL.SWEVSET.SWEV2] 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 259 **AUX ** Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX 3Fh = No event, always low SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 260 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 261 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 262 26h = RTC channel 0 - delayed event 27h = RTC channel 1 - delayed event 28h = RTC channel 2 - delayed event Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 263 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 264 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 265 **AUX ** Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX 3Fh = No event, always low SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 266 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 267 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 268 **AUX ** Comparator B (inverted) as opposed to AUX_COMPB which is synchronized in AUX 3Fh = No event, always low Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 269 Interrupts and Events Registers www.ti.com SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 270: Event Registers
RFCSEL8 Output Selection for RFC Event 8 Section 4.6.2.43 124h RFCSEL9 Output Selection for RFC Event 9 Section 4.6.2.44 270 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 271 Section 4.6.2.89 600h GPT3ACAPTSEL Output Selection for GPT3 0 Section 4.6.2.90 604h GPT3BCAPTSEL Output Selection for GPT3 1 Section 4.6.2.91 SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 272 Section 4.6.2.94 A00h FRZSEL0 Output Selection for FRZ Subscriber 0 Section 4.6.2.95 F00h SWEV Set or Clear Software Events Section 4.6.2.96 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 273 Read only selection value 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 274 Read only selection value 9h = Interrupt event from I2C Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 275 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 276 Read only selection value 38h = SPIS Combined event, the flags are found here SPIS:GPFLAGS Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 277 Read only selection value 7h = Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 278 Read only selection value 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 279 1Ch = AUX software event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL AUX domain wakeup control AON_EVENT:AUXWUSEL SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 280 Read only selection value 22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 281 Read only selection value 23h = SSI0 combined interrupt, interrupt flags are found here SSI1:MIS SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 282 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 283 Read only selection value 1Ah = Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 284 Read only selection value 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 285 Read only selection value 8h = Interrupt event from I2S SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 286 1Dh = AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL AUX domain wakeup control AON_EVENT:AUXWUSEL Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 287 Read only selection value 18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 288 Read only selection value 10h = GPT0A interrupt event, controlled by GPT0:TAMR Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 289 Read only selection value 11h = GPT0B interrupt event, controlled by GPT0:TBMR SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 290 Read only selection value 12h = GPT1A interrupt event, controlled by GPT1:TAMR Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 291 Read only selection value 13h = GPT1B interrupt event, controlled by GPT1:TBMR SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 292 Read only selection value Ch = GPT2A interrupt event, controlled by GPT2:TAMR Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 293 Read only selection value Dh = GPT2B interrupt event, controlled by GPT2:TBMR SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 294 Read only selection value Eh = GPT3A interrupt event, controlled by GPT3:TAMR Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 295 Read only selection value Fh = GPT3B interrupt event, controlled by GPT3:TBMR SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 296 Read only selection value 5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 297 Read only selection value 27h = Combined DMA done corresponding flags are here UDMA0:REQDONE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 298 Read only selection value 26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 299 Read only selection value 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 300 Read only selection value 64h = Software event 0, triggered by SWEV.SWEV0 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 301 Read only selection value Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 302 Read only selection value 1h = Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 303 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 304 Read only selection value 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 305 Read only selection value 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 306 Read only selection value 68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 307 Read only selection value 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 308 Read only selection value 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 309 Read only selection value 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 310 Read only selection value 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 311 Read only selection value 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 312 Read only selection value 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 313 Read only selection value 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 314 Read only selection value 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 315 Read only selection value 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 316 AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 317 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 318 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 319 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 320 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 321 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 322 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 323 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 324 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 325 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 326 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 327 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 328 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 329 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 330 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 331 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 332 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 333 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 334 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 335 Read only selection value 31h = UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 336 Read only selection value 30h = UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 337 Read only selection value 33h = UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 338 Read only selection value 32h = UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 339 Read only selection value 29h = SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 340 Read only selection value 28h = SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 341 Read only selection value 2Bh = SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 342 Read only selection value 2Ah = SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 343 Read only selection value 3Ah = SPIS RX FIFO DMA single request, controlled by SPIS:CFG.TR_DMA_REQ_TYPE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 344 Read only selection value 39h = SPIS RX FIFO DMA burst request, controlled by SPIS:CFG.TR_DMA_REQ_TYPE Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 345 Read only selection value 3Ch = SPIS TX FIFO DMA single request, controlled by SPIS:CFG.TX_DMA_REQ_TYPE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 346 Read only selection value 3Bh = SPIS TX FIFO DMA burst request, controlled by SPIS:CFG.TX_DMA_REQ_TYPE Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 347 Read only selection value 75h = DMA single request event from AUX, configured by AUX_EVCTL:DMACTL SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 348 Read only selection value 76h = DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 349 Read only selection value 74h = AUX observation loopback SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 350 Read only selection value 74h = AUX observation loopback Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 351 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 352 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 353 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 354 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 355 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 356 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 357 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 358 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 359 Read only selection value 3h = Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 360 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 361 SSI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 362 57h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 363 75h = DMA single request event from AUX, configured by AUX_EVCTL:DMACTL 76h = DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL 77h = RTC periodic event controlled by SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 364 Table 4-91. UDMACH14BSEL Register Field Descriptions (continued) Field Type Reset Description AON_RTC:CTL.RTC_UPD_EN 78h = CPU halted 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 365 Read only selection value 7h = Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 366 Read only selection value 2Dh = SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 367 Read only selection value 2Ch = SSI1 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 368 Read only selection value 2Fh = SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 369 Read only selection value 2Eh = SSI1 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 370 Read only selection value 64h = Software event 0, triggered by SWEV.SWEV0 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 371 Read only selection value 64h = Software event 0, triggered by SWEV.SWEV0 SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 372 Read only selection value 65h = Software event 1, triggered by SWEV.SWEV1 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 373 Read only selection value 65h = Software event 1, triggered by SWEV.SWEV1 SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 374 Read only selection value 66h = Software event 2, triggered by SWEV.SWEV2 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 375 Read only selection value 66h = Software event 2, triggered by SWEV.SWEV2 SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 376 Read only selection value 67h = Software event 3, triggered by SWEV.SWEV3 Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 377 Read only selection value 67h = Software event 3, triggered by SWEV.SWEV3 SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 378 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 379 AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 6Eh = AUX timer 1 event, corresponds to SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 380 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 381 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 382 AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 6Eh = AUX timer 1 event, corresponds to Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 383 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*] 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 384 12h = GPT1A interrupt event, controlled by GPT1:TAMR 13h = GPT1B interrupt event, controlled by GPT1:TBMR 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 385 Read only selection value 63h = Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 386 61h = RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 62h = RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 79h = Always asserted Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 387 Read/write selection value 0h = Always inactive 78h = CPU halted 79h = Always asserted SWCU117A – February 2015 – Revised March 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 388 SWEV0 Writing "1" to this bit when the value is "0" triggers the Software 0 event. Interrupts and Events SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 389: Jtag Interface
Serial Wire Viewer (SWV) ....................Halt In Boot (HIB) ..................Debug and Shutdown ............ Debug Features Supported Through WUC TAP ....................Profiler Register SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 390: Top Level Debug System
MCU voltage domain 1149.1 eFuse TAP PRCM PBIST1.0 TAP PBIST2.0 TAP JTAG power domain Test TAP 1149.1 ICEPick cJTAG 2/4pin ICEMelter I/O MUX JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 391 The two main paths allow for setting or retrieving information from either a data register (DR) or the instruction register (IR) of the device. The data register depends on the value loaded into the instruction register. SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 392: Cjtag
Reuse of TDI and TDO pins TCKWID Programmable TCK width Power down logic capability for Power control Power down logic cJTAG module JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 393 OScan4 nTDI nTDI OScan5 nTDI nTDI OScan6 nTDI OScan7 nTDI TMS is present for the first packet of the shift. SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 394: Jtag Commands
No DTS delay is added Add one TCKC signal period Add two TCKC signal periods Add a variable number of TCKC signal periods Reserved 394 JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 395 SGC bit of a nontargeted controller is cleared SGC bit of the targeted controller is set SGC bit of a nontargeted controller is not affected 00101–00110 Reserved SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 396: Programming Sequences
3. Scan DR (9 bits of 1, end in Pause DR)—Load CP1 with 9. 4. Goto Scan (Through Update DR to Pause DR)—Complete CP1 by going through update. JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 397: Icepick
TAPs for end user. The open TAPs can be locked by writing to the corresponding field in the customer configuration area. SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 398 TAP is connected closest to the device TDO. • Any selected TAPs within the test bank are linked before any TAPs within the debug bank (DAP for example). JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 399: Icepick™ Registers
000000, 111111 BYPASS Always-open ROUTER Connected IDCODE Always-open ICEPICKCODE Always-open CONNECT Always-open 1000 USERCODE Always-open 000001, 000011, 000110, 001001–111110 Reserved Reserved SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 400 The contents of this register are replicated to a device configuration area which is memory mapped. Refer to FCFG1:ICEPICK_DEVICE_ID in Section 9.2.1.50 for details of this register. 400 JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 401 Icepick Type An identifier of the Icepick Type This field is set to 0x1CC which corresponds to Type C. Capabilities Reserved SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 402: Router Scan Chain
Figure 5-11. ROUTER DR Scan Chain Write Enable / Block Select Register Number Register Value Write Failure Access JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 403: Tap Routing Registers
This section describes the TAP routing registers that can be accessed using router scan. 5.3.4.1 ICEPick™ Control Block The ICEPick Control Block implements the Table 5-13. Reads of unused registers return all 0s. SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 404 Once activated, the ICEPick TAP is no longer visible between the device Disappear-forever TDI and TDO. Only a power-on reset will make the TAP visible again. 001-010, 100-111 Reserved Reserved JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 405 Secondary Debug TAP 0 Register 0x1-0xF Reserved 5.3.4.3.1 Secondary Debug TAP Register Table 5-21 shows the secondary debug TAP register [SDTR]. SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 406 Reserved Reserved When 0, the TAP cannot be accessed due to security. TapAccessible When 1, the TAP can be accessed. 406 JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 407 If a TAP does not exist, the rest of the controls and status bits in this register are considered to be non-operational. SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 408: Icemelter
To exit HIB, the external emulator must connect to the device and first HALT, then RESUME the CPU through DAP. After resuming, the program execution continues from the application code. JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 409: Debug And Shutdown
This register resides in the TEST TAP. Refer to Table 5-24 for more details Figure 5-12. Profiler Register Chip Status Access Reset Unknown SWCU117A – February 2015 – Revised March 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 410 0x6 The RF synthesizer is active. 0xE The RF core is receiving a packet. 0xA The RF core is transmitting a packet. Others: Reserved 11:0 Reserved JTAG Interface SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 411: Power, Reset, And Clock Management
This chapter details the flexible power management and clock control (PRCM) of the CC26xx device..........................Topic Page ..................... Introduction ....................PRCM Registers SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 412: Introduction
All power domains are powered off and voltage domains are supplied by the micro LDO. Shutdown mode Only I/Os maintain their operation. All voltage regulators, voltage, and power domains are off. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 413: System Cpu Mode
For example, register [PRCM:PDCTL0.SERIAL_ON] controls the SERIAL power domain. Figure 6-3 for more details about voltage and power domains. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 414 VDDR_RF pin. The Global LDO must be decoupled by a µF-sized capacitor on the VDDR net. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 415: Digital Power Partitioning
*_PD. Each power domain contains digital modules. Figure 6-3 shows details of the power partitioning of the CC26xx device. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 416 I/O state holder AUX Wakeup Analog interface Timers Event Peripherals SC SRAM Event fabric JTAG_PD ICEPick JTAG router IEEE1149.7 (cJTAG) Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 417: Clock Management
24 MHz ACLK_ADC oscillator 32 kHz LF RC ACLK_REF oscillator 32 kHz External ACLK_TDC I/O controller 32 kHz SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 418 48 MHz from RC oscillator 24 MHz from RC oscillator 24 MHz from XTAL oscillator Selectable in [DDI_0_OSC:CTL0.ACLK_TDC_SRC_SE Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 419 DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL RCOSC 48 MHz / 1536 XTAL 48 MHz / 768 ACLK_REF RCOSC 32 kHz XTAL 32.768 kHz SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 420 SCLK_HF, regardless of the settings in [PRCM:INFCLKDIVR/S/DS]. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 421 2 if PRCM:INFCLKDIVR/S/ DS = 1 I/O controller INFRASTRUCTURE clock Wakeup interrupt controller Watchdog timer SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 422: Power Modes
Table 6-5 provides an overview of the power modes defined in TI-RTOS. 422 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 423 – VIMS_PD powered • VIMS clock running – All other power domains off – All digital module clocks disabled SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 424 Enable the DC-DC converter for [AON_SYSCTL:PWRCTL.DCDC_ACTIVE] No (Default: Global LDO) lower power Set the HF clocks to correct source [DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL] 424 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 425 Set the system CPU SLEEPDEEP [CPU_SCS:SCR.SLEEPDEEP] Stop the system CPU to start the WFI or WFE power-down sequence SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 426: Reset
The [PRCM:WARMRESET] register has readable bits that indicate if the MCU_VD was reset due to a system CPU LOCKUP event or a watchdog time-out. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 427: Prcm Registers
6.1.6.6 Reset of AUX_PD Reset of AUX_PD can be done by writing to the [AON_WUC:AUXCTL.RESET_REQ] register. PRCM Registers SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 428: Prcm Registers
Section 6.2.1.39 134h PDCTL0SERIAL SERIAL Power Domain Control Section 6.2.1.40 138h PDCTL0PERIPH PERIPH Power Domain Control Section 6.2.1.41 428 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 429 Selected RFC Mode Section 6.2.1.55 224h RAMRETEN Memory Retention Control Section 6.2.1.56 250h RAMHWOPT CONFIG SIZE For SRAM Section 6.2.1.57 SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 430 0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 431 0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 432 0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 433 SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with CLKLOADCTL.LOAD) 5. RFC do no request access to BUS 6. System CPU in deepsleep SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 434 SSICLKGDS - UARTCLKGR - UARTCLKGS - UARTCLKGDS - I2SCLKGR - I2SCLKGS - I2SCLKGDS - I2SBCLKSEL - I2SCLKCTL - I2SMCLKDIV - I2SBCLKDIV - I2SWCLKDIV - RAMHWOPT Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 435 0: Disable clock 1: Enable clock if RFC power domain is on For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 436 00: Disable clock 01: Disable clock when SYSBUS clock is disabled 11: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 437 CLKLOADCTL.LOAD needs to be written CRYPTO_CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 438 CLKLOADCTL.LOAD needs to be written CRYPTO_CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 439 CLKLOADCTL.LOAD needs to be written CRYPTO_CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 440 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 441 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 442 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 443 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 444 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 445 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 446 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 447 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 448 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 449 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 450 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 451 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 452 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SSI0 2h = Enable clock for SSI1 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 453 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SSI0 2h = Enable clock for SSI1 SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 454 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SSI0 2h = Enable clock for SSI1 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 455 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 456 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 457 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 458 0h = Internal. Only to be used through TI provided API. 1h = Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 459 BCLK source selector 0: Use external BCLK 1: Use internally generated clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 460 5h = Divide by 32 6h = Divide by 64 7h = Divide by 128 8h = Divide by 256 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 461 0: MCLK, BCLK and **WCLK** will be static low 1: Enables the generation of MCLK, BCLK and WCLK For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 462 MCUCLK period longer than the high phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 463 MCUCLK period longer than the low phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 464 (unsigned, [1-255]) BCLK periods. WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 465 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 466 0: No registered event 1: A WDT event has occured since last SW clear of the register. A read of this register clears both WDT_STAT and LOCKUP_STAT. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 467 RFC_ON 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 1: RFC power domain powered on SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 468 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDCTL0.RFC_ON Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 469 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDCTL0.SERIAL_ON SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 470 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDCTL0.PERIPH_ON Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 471 (guaranteed) RFC_ON RFC Power domain 0: Domain may be powered down 1: Domain powered up (guaranteed) SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 472 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDSTAT0.RFC_ON Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 473 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDSTAT0.SERIAL_ON SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 474 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDSTAT0.PERIPH_ON Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 475 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 476 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDCTL1.CPU_ON Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 477 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDCTL1.RFC_ON SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 478 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDCTL1.VIMS_MODE Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 479 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 480 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDSTAT1.BUS_ON Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 481 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDSTAT1.RFC_ON SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 482 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDSTAT1.CPU_ON Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 483 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDSTAT1.VIMS_MODE SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 484 4h = Select Mode 4 5h = Select Mode 5 6h = Select Mode 6 7h = Select Mode 7 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 485 OFF mode first and then CACHE or SPILT mode. 10: Illegal mode 11: No restrictions SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 486 1h = 10K : Configured to 10k RAM 2h = 16K : Configured to 16k RAM 3h = 20K : Configured to 20k RAM Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 487 PRCM Registers www.ti.com SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 488: Aon_Sysctl Registers
Register Name Section PWRCTL Power Management Section 6.2.2.1 RESETCTL Reset Management Section 6.2.2.2 SLEEPCTL Sleep Mode Section 6.2.2.3 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 489 GLDO for recharge of VDDR 1: Use DCDC for recharge of VDDR Note: This bitfield should be set to the same as DCDC_ACTIVE SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 490 Internal. Only to be used through TI provided API. BOOT_DET_0 Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 491 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 492 Application software may want to reconfigure the state for all IO's before setting this bitfield upon waking up from a SHUTDOWN. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 493: Aon_Wuc Registers
Recharge Controller Status Section 17.8.4.11 OSCCFG Oscillator Configuration Section 17.8.4.12 JTAGCFG JTAG Configuration Section 17.8.4.13 JTAGUSERCODE JTAG USERCODE Section 17.8.4.14 SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 494 MCU is no longer requesting powerdown and system is back in active mode. 0h = No clock in Powerdown 1h = Use SCLK_LF in Powerdown 2h = 2 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 495 Selects the clock source for AUX: NB: Switching the clock source is guaranteed to be glitchless 1h = HF Clock (SCLK_HF) 2h = 2 4h = LF Clock (SCLK_LF) SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 496 7h = Retention on for SRAM:BANK0, SRAM:BANK1 and SRAM:BANK2 Fh = Retention on for all banks (SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2 and SRAM:BANK3) Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 497 Retention is disabled 1: Retention is enabled NB: If retention is disabled, the AUX_RAM will be powered off when it would otherwise be put in retention mode SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 498 PWRSTAT.AUX_PD_ON 0: AUX is allowed to Power Off, Power Down or Disconnect. 1: AUX Power OFF, Power Down or Disconnect requests will be overruled Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 499 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 500 Powerdown mode, but instead it will turn off all internal powersupplies, effectively putting the device into Shutdown mode. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 501 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 502 (requested from MCU or JTAG as indicated in MCU_RESET_SRC) This bit can only be cleared by writing a 1 to it Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 503 PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Mantissa of the Period. PERIOD=(PER_M*16+15)*2^PER_E SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 504 PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Exponent of the Period. PERIOD=(PER_M*16+15)*2^PER_E Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 505 We can therefore use the value as an indication of the leakage current during recharge. This bitfield is cleared to 0 when writing this register. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 506 Note: Oscillator amplitude calibration is turned of when both PER_M and this bitfield are set to 0 Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 507 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 508 Description 31-0 USER_CODE B99A02Fh 32-bit JTAG USERCODE register feeding main JTAG TAP NB: This field can be locked Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 509: Ddi_0_Osc Registers
RCOSCHF Control Section 6.2.4.13 STAT0 Status 0 Section 6.2.4.14 STAT1 Status 1 Section 6.2.4.15 STAT2 Status 2 Section 6.2.4.16 SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 510 STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be disabled to prevent flash corruption. Switching should not be enabled when running from flash. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 511 1h = Medium frequency clock derived from high frequency XOSC. SCLK_HF_SRC_SEL Source select for sclk_hf 0h = High frequency RCOSC clk 1h = High frequency XOSC clk SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 512 XOSC_HF_FAST_START R/W Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 513 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 514 Internal. Only to be used through TI provided API. IBIASCAP_HPTOLP_OL_ R/W Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 515 Internal. Only to be used through TI provided API. HPMRAMP1_TH Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 516 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 517 Internal. Only to be used through TI provided API. 15-0 XOSC_HF_COLUMN_Q1 Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 518 13-0 XOSC_HF_IBIASTHERM Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 519 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 520 ADC_IREF_CTRL Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 521 Internal. Only to be used through TI provided API. LP_BUF_ITRIM Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 522 3h = 6P0MEG : Internal. Only to be used through TI provided API. RCOSCLF_CTUNE_TRIM R/W Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 523 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 524 24 or 48 MHz chrystal is used (enabled in doulbler bypass for the 48MHz chrystal). Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 525 ADC_DATA adc_data PENDINGSCLKHFSWITC R Indicates when sclk_hf is ready to be swtiched HING SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 526 FORCE_RCOSC_HF force_rcosc_hf SCLK_HF_EN SCLK_HF_EN SCLK_MF_EN SCLK_MF_EN ACLK_ADC_EN ACLK_ADC_EN ACLK_TDC_EN ACLK_TDC_EN ACLK_REF_EN ACLK_REF_EN CLK_CHP_EN CLK_CHP_EN CLK_DCDC_EN CLK_DCDC_EN SCLK_HF_GOOD SCLK_HF_GOOD Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 527 Field Type Reset Description SCLK_MF_GOOD SCLK_MF_GOOD SCLK_LF_GOOD SCLK_LF_GOOD ACLK_ADC_GOOD ACLK_ADC_GOOD ACLK_TDC_GOOD ACLK_TDC_GOOD ACLK_REF_GOOD ACLK_REF_GOOD CLK_CHP_GOOD CLK_CHP_GOOD CLK_DCDC_GOOD CLK_DCDC_GOOD SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 528 +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer. Power, Reset, and Clock Management SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 529: Versatile Instruction Memory System (Vims)
The RAM block can be used as a cache for the Flash block or as general purpose RAM. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 530 VIMS Software (SW) Remarks ....................VIMS Registers ............................................EEFUSE ......................FLASH ....................VIMS Registers ....................ROM Functions ......................SRAM Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 531: Vims Configurations
In GPRAM mode, the RAM block functions as a general-purpose RAM. The Flash block has no cache support, and all accesses to the flash are routed directly to the Flash block. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 532 SYSCODE address space. System bus accesses to the Flash block and CPU accesses to the flash USERCODE address space are routed directly to the Flash block. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 533 USERCODE and SYSCODE address space icode/dcode icode/dcode CACHE FLASH USERCODE and SYSCODE address space sysbus sysbus BROM address space SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 534: Vims Flash Line Buffering
NOTE: If the whole MCU domain is powered off, the VIMS domain will not support retention. Table 7-1 specifies the valid retention combination for VIMS memory: Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 535 The correct procedure will be to put VIMS into off mode and then disabled mode (see Figure 7-8, GPRAM Retention, for more details). SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 536 DISABLED If switch to enabled is needed, the following sequence is required: INIT INIT ENABLED SPLIT Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 537: Vims Registers
Table 7-2. VIMS Registers Offset Acronym Register Name Section STAT Status Section 7.3.1 Control Section 7.3.2 SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 538: Stat Register (Offset = 0H) [Reset = X]
1h = CACHE : VIMS Cache mode 2h = VIMS Split Cache mode 3h = VIMS Off mode Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 539: Ctl Register (Offset = 4H) [Reset = X]
1h = CACHE : VIMS Cache mode 2h = VIMS Split Cache mode 3h = VIMS Off mode SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 540: Rom
Fixed: The number of this type is fixed Chip Erase function will erase all sectors not locked by TI. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 541: Flash Memory Programming
SRAM) while the flash operation is in progress. 7.6.4 FLASH Read Timings 7.6.5 Power Mode Operations VIMS Registers SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 542: Flashmem Registers
Table 7-6. FLASHMEM Registers Offset Acronym Register Name Section Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 543: Flash Registers
FMC VREADCT Trim Section 7.7.2.42 2084h FVHVCT1 FMC VHVCT1 Trim Section 7.7.2.43 2088h FVHVCT2 FMC VHVCT2 Trim Section 7.7.2.44 SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 544 FSM_PRG_PUL FMC FSM Maximum Programming Pulses Section 7.7.2.90 226Ch FSM_ERA_PUL FMC FSM Maximum Erase Pulses Section 7.7.2.91 544 Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 545 FMC Flash Bank 7 Starting Address Section 7.7.2.122 2430h FCFG_B0_SSIZE0 FMC Flash Bank 0 Sector Size 0 Section 7.7.2.123 SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 546 0 : Not busy 1 : Busy POWER_MODE Power state of the flash sub-system. 0 : Active 1 : Low power Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 547 Internal. Only to be used through TI provided API. DIS_IDLE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 548 Internal. Only to be used through TI provided API. SYSCODE_START Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 549 Internal. Only to be used through TI provided API. SECTORS Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 550 Internal. Only to be used through TI provided API. FWLOCK Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 551 Internal. Only to be used through TI provided API. FWFLAG Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 552 Internal. Only to be used through TI provided API. 15-0 DUMPWORD Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 553 Internal. Only to be used through TI provided API. 10-0 Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 554 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 555 Table 7-17. DATALOWER Register Field Descriptions Field Type Reset Description 31-0 DATA Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 556 Internal. Only to be used through TI provided API. GATING Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 557 Internal. Only to be used through TI provided API. RESETDONE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 558 Internal. Only to be used through TI provided API. 23-0 ACCUMULATOR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 559 Internal. Only to be used through TI provided API. INPUTENABLE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 560 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 561 Table 7-23. EFUSEKEY Register Field Descriptions Field Type Reset Description 31-0 CODE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 562 Internal. Only to be used through TI provided API. EFUSEDAY Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 563 Internal. Only to be used through TI provided API. SYS_WS_READ_STATE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 564 Internal. Only to be used through TI provided API. DATA Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 565 Internal. Only to be used through TI provided API. MARGIN Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 566 Internal. Only to be used through TI provided API. WRITECLOCK Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 567 Internal. Only to be used through TI provided API. CODE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 568 Internal. Only to be used through TI provided API. FROM0 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 569 Internal. Only to be used through TI provided API. FROM0 Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 570 Table 7-32. SELFTESTCYC Register Field Descriptions Field Type Reset Description 31-0 CYCLES Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 571 Table 7-33. SELFTESTSIGN Register Field Descriptions Field Type Reset Description 31-0 SIGNATURE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 572 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 573 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 574 Internal. Only to be used through TI provided API. 23-0 EDACEN Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 575 Internal. Only to be used through TI provided API. 23-0 ERR_PRF_FLG Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 576 Internal. Only to be used through TI provided API. PROTL1DIS Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 577 Internal. Only to be used through TI provided API. 15-0 Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 578 Internal. Only to be used through TI provided API. BUSY Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 579 Internal. Only to be used through TI provided API. VREADS Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 580 Internal. Only to be used through TI provided API. BANKPWR0 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 581 Internal. Only to be used through TI provided API. BANKRDY Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 582 Internal. Only to be used through TI provided API. PUMPPWR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 583 Internal. Only to be used through TI provided API. 15-0 PAGP Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 584 Internal. Only to be used through TI provided API. BANK Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 585 Internal. Only to be used through TI provided API. SLOCK Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 586 Internal. Only to be used through TI provided API. 15-0 ENCOM 55AAh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 587 Internal. Only to be used through TI provided API. VREADCT Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 588 Internal. Only to be used through TI provided API. VHVCT_PV Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 589 Internal. Only to be used through TI provided API. 15-0 RESERVED Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 590 Internal. Only to be used through TI provided API. VHVCT_READ Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 591 Internal. Only to be used through TI provided API. VIN_CT Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 592 Internal. Only to be used through TI provided API. 11-0 RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 593 Internal. Only to be used through TI provided API. VWLCT_P Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 594 Internal. Only to be used through TI provided API. EFUSE_EN Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 595 Internal. Only to be used through TI provided API. SHIFT_DONE R/W1C Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 596 Table 7-58. FEFUSEDATA Register Field Descriptions Field Type Reset Description 31-0 FEFUSEDATA Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 597 Internal. Only to be used through TI provided API. SEQ_PUMP Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 598 Internal. Only to be used through TI provided API. RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 599 Internal. Only to be used through TI provided API. V5PWRDNZ Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 600 Internal. Only to be used through TI provided API. MODE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 601 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 602 Table 7-64. FADDR Register Field Descriptions Field Type Reset Description 31-0 FADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 603 Internal. Only to be used through TI provided API. RESERVED Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 604 Table 7-66. FWPWRITE0 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE0 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 605 Table 7-67. FWPWRITE1 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE1 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 606 Table 7-68. FWPWRITE2 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE2 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 607 Table 7-69. FWPWRITE3 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE3 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 608 Table 7-70. FWPWRITE4 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE4 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 609 Table 7-71. FWPWRITE5 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE5 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 610 Table 7-72. FWPWRITE6 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE6 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 611 Table 7-73. FWPWRITE7 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE7 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 612 Internal. Only to be used through TI provided API. ECCBYTES31_24 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 613 Internal. Only to be used through TI provided API. SAFELV Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 614 Internal. Only to be used through TI provided API. CLKSEL Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 615 Internal. Only to be used through TI provided API. RESERVED Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 616 Internal. Only to be used through TI provided API. INV_DAT Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 617 Internal. Only to be used through TI provided API. FSMCMD Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 618 Internal. Only to be used through TI provided API. ERA_OSU Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 619 Internal. Only to be used through TI provided API. 11-0 RESERVED Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 620 Internal. Only to be used through TI provided API. ERA_VSU Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 621 Internal. Only to be used through TI provided API. 11-0 RESERVED Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 622 Internal. Only to be used through TI provided API. EXE_VALD Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 623 Internal. Only to be used through TI provided API. RD_H Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 624 Internal. Only to be used through TI provided API. RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 625 Internal. Only to be used through TI provided API. 15-0 ERA_OH Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 626 Internal. Only to be used through TI provided API. 11-0 SAV_P_PUL Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 627 Internal. Only to be used through TI provided API. ERA_VH Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 628 Internal. Only to be used through TI provided API. 15-0 PROG_PUL_WIDTH Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 629 Table 7-91. FSM_ERA_PW Register Field Descriptions Field Type Reset Description 31-0 FSM_ERA_PW Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 630 Internal. Only to be used through TI provided API. 11-0 SAV_ERA_PUL Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 631 Table 7-93. FSM_TIMER Register Field Descriptions Field Type Reset Description 31-0 FSM_TIMER Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 632 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 633 Internal. Only to be used through TI provided API. 22-0 PGM_ADDR Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 634 Internal. Only to be used through TI provided API. 22-0 ERA_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 635 Internal. Only to be used through TI provided API. 11-0 MAX_PRG_PUL Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 636 Internal. Only to be used through TI provided API. 11-0 MAX_ERA_PUL BB8h Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 637 Internal. Only to be used through TI provided API. 15-0 RESERVED Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 638 Internal. Only to be used through TI provided API. 11-0 PUL_CNTR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 639 Internal. Only to be used through TI provided API. EC_STEP_HEIGHT Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 640 Internal. Only to be used through TI provided API. OVERRIDE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 641 Internal. Only to be used through TI provided API. BLK_OTP Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 642 Internal. Only to be used through TI provided API. WR_ENA Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 643 Table 7-105. FSM_ACC_PP Register Field Descriptions Field Type Reset Description 31-0 FSM_ACC_PP Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 644 Internal. Only to be used through TI provided API. 15-0 ACC_EP Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 645 Internal. Only to be used through TI provided API. 27-0 CUR_ADDR Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 646 Internal. Only to be used through TI provided API. SEC_OUT Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 647 Internal. Only to be used through TI provided API. 11-0 CONFIG_CRC Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 648 Internal. Only to be used through TI provided API. FSM_ERR_BANK Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 649 Internal. Only to be used through TI provided API. 11-0 FSM_PGM_MAXPUL Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 650 Internal. Only to be used through TI provided API. FSMEXECUTE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 651 Table 7-113. FSM_SECTOR1 Register Field Descriptions Field Type Reset Description 31-0 FSM_SECTOR1 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 652 Table 7-114. FSM_SECTOR2 Register Field Descriptions Field Type Reset Description 31-0 FSM_SECTOR2 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 653 Table 7-115. FSM_BSLE0 Register Field Descriptions Field Type Reset Description 31-0 FSM_BSLE0 Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 654 Table 7-116. FSM_BSLE1 Register Field Descriptions Field Type Reset Description 31-0 FSM_BSL1 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 655 Table 7-117. FSM_BSLP0 Register Field Descriptions Field Type Reset Description 31-0 FSM_BSLP0 Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 656 Table 7-118. FSM_BSLP1 Register Field Descriptions Field Type Reset Description 31-0 FSM_BSL1 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 657 Internal. Only to be used through TI provided API. MAIN_NUM_BANK Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 658 Internal. Only to be used through TI provided API. CPU_TYPE1 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 659 Internal. Only to be used through TI provided API. B0_TYPE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 660 Internal. Only to be used through TI provided API. 23-0 B0_START_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 661 Internal. Only to be used through TI provided API. 23-0 B1_START_ADDR Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 662 Internal. Only to be used through TI provided API. 23-0 B2_START_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 663 Internal. Only to be used through TI provided API. 23-0 B3_START_ADDR Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 664 Internal. Only to be used through TI provided API. 23-0 B4_START_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 665 Internal. Only to be used through TI provided API. 23-0 B5_START_ADDR Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 666 Internal. Only to be used through TI provided API. 23-0 B6_START_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 667 Internal. Only to be used through TI provided API. 23-0 B7_START_ADDR Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 668 Internal. Only to be used through TI provided API. B0_SECT_SIZE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 669: Rom Functions
GPIO backdoor. The bootloader may not be called from application code. SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 670: Sram
Data can also be transferred to and from the SRAM using the micro-direct memory access controller (μDMA). The Cortex M0 in the RF Core also has access to the system RAM. Versatile Instruction Memory System (VIMS) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 671: Bootloader
SWCU117A – February 2015 – Revised March 2015 Bootloader This section describes the CC26xx bootloader..........................Topic Page ................... Bootloader Functionality ..................Bootloader Interfaces SWCU117A – February 2015 – Revised March 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 672: Bootloader Functionality
The bootloader communicates with an external device over a 2–pin UART or a 4–pin SSI interface. The communication protocol and transport layers are described in the following sections. Bootloader SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 673: Packet Handling
SWCU117A – February 2015 – Revised March 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 674: Transport Layer
UART connection. Table 8-3 specifies which serial interface signals will be configured to specific DIOs. These pins are fixed and cannot be reconfigured. Bootloader SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 675 The device communicating with the bootloader drives the SSI0 RX, SSI0 Clk, and SSI0 Fss pins, while the CC26xx drives the SSI0 TX pin. SWCU117A – February 2015 – Revised March 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 676: Serial Bus Commands
CCFG parameters will be programmed with values from the corresponding parameters in FCFG1 after the erase: BOOTLOADER_ENABLE and all DAP and TAP parameters. 676 Bootloader SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 677 The format of the packet including the command is as follows: unsigned char ucCommand[3]; ucCommand[0] = <size=3>; ucCommand[1] = <checksum>; ucCommand[2] = COMMAND_PING; SWCU117A – February 2015 – Revised March 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 678 The bootloader responds with an ACK signal to the host device after the actual erase operation is performed. On CC26xx, the flash starts at address 0x1800 0000 and it has 32 sectors of 4KB each. Bootloader SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 679 COMMAND_RET_INVALID_CMD 0x42 incorrect packet size) COMMAND_RET_INVALID_ADR 0x43 Status for invalid input address COMMAND_RET_FLASH_FAIL 0x44 Status for failing flash erase or program operation SWCU117A – February 2015 – Revised March 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 680 The bootloader then waits for an ACK signal from the host as a confirmation that the packet was received. The format of the command is as follows: unsigned char ucCommand[3]; ucCommand[0] = <size=3>; ucCommand[1] = <checksum>; ucCommand[2] = COMMAND_GET_CHIP_ID; Bootloader SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 681 Read Repeat Count [31:24]; ucCommand[12]= Read Repeat Count [23:16]; ucCommand[13]= Read Repeat Count [15: 8]; ucCommand[14]= Read Repeat Count [7: 0]; SWCU117A – February 2015 – Revised March 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 682 CCFG Field ID, which identifies the CCFG parameter to be written, and the second 32-bit value is the Field Value to be programmed. The command handler masks out Field Value bits not corresponding to the CCFG parameter size. Bootloader SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 683 Any other value than 0xC5 will force a Bit[31:8] – Don’t care 6: ID_PBIST1_TAP_LCK locked TAP after a following boot Bit[7:0] – 0xC5 = TAP unlocked sequence. SWCU117A – February 2015 – Revised March 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 684 Any value other than 0xC5 will force the Bit[31:8] – Don’t care 14: ID_BL_ENABLE bootloader to ignore any received Bit[7:0] – Bootloader enable command. Bootloader SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 685: Device Configuration
CCFG should be set by the application and contains configuration parameters for the ROM bootcode, device hardware, and device firmware..........................Topic Page ................ Customer Configuration (CCFG) ................Factory Configuration (FCFG) SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 686: Customer Configuration (Ccfg)
[CCFG_TAP_DAP_0:TEST_TAP_ENABLE] register is not enabled in FCFG, the value in the corresponding CCFG field is ignored and the functionality is disabled. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 687: Ccfg Registers
FF4h CCFG_PROT_63_32 Protect Sectors 32-63 Section 9.1.1.19 FF8h CCFG_PROT_95_64 Protect Sectors 64-95 Section 9.1.1.20 FFCh CCFG_PROT_127_96 Protect Sectors 96-127 Section 9.1.1.21 SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 688 SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET XOSC_MAX_START Unsigned value of maximum XOSC startup time (worst case) in units of 100us. Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 689 (handled automatically if using TI RTOS!). DIS_XOSC_OVR Disable XOSC override functionality. 0: Enable XOSC override functionality. 1: Disable XOSC override functionality. See: MODE_CONF_1.DELTA_IBIAS_INIT MODE_CONF_1.DELTA_IBIAS_OFFSET MODE_CONF_1.XOSC_MAX_START SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 690 Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 691 DriverLib functions SysCtrlSetRechargeBeforePowerDown() and SysCtrlAdjustRechargeAfterPowerDown() which should be called before and after powerdown / standby respectively (handled automatically if using TI RTOS!). SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 692 Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 693 Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 694 Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 695 Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 696 FFFFFFFFh Bits[31:0] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 697 FFFFFFFFh Bits[63:32] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 698 FFFFFFFFh Bits[31:0] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 699 FFFFFFFFh Bits[63:32] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 700 Enables the boot loader failure analysis. 0xC5: Failure analysis enabled. Any other value: Failure analysis disabled. NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if failure analysis is enabled. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 701 Bank erase is also referred to as mass erase. 0: Disable the boot loader bank erase function. 1: Enable the boot loader bank erase function. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 702 Failure Analysis) option with the unlock code. All other values: Disable the functionality of unlocking the TI FA option with the unlock code. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 703 1 by boot FW while in safezone. Any other value: AON_WUC:JTAGCFG.TEST_TAP will be set to 0 by boot FW while in safezone. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 704 1 by boot FW while in safezone. Any other value: AON_WUC:JTAGCFG.WUC_TAP will be set to 0 by boot FW while in safezone. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 705 A non-zero value forces the boot sequence to call the boot loader. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 706 0: Sector protected WRT_PROT_SEC_15 0: Sector protected WRT_PROT_SEC_14 0: Sector protected WRT_PROT_SEC_13 0: Sector protected WRT_PROT_SEC_12 0: Sector protected WRT_PROT_SEC_11 0: Sector protected Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 707 0: Sector protected WRT_PROT_SEC_4 0: Sector protected WRT_PROT_SEC_3 0: Sector protected WRT_PROT_SEC_2 0: Sector protected WRT_PROT_SEC_1 0: Sector protected WRT_PROT_SEC_0 0: Sector protected SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 708 0: Sector protected WRT_PROT_SEC_47 0: Sector protected WRT_PROT_SEC_46 0: Sector protected WRT_PROT_SEC_45 0: Sector protected WRT_PROT_SEC_44 0: Sector protected WRT_PROT_SEC_43 0: Sector protected Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 709 0: Sector protected WRT_PROT_SEC_36 0: Sector protected WRT_PROT_SEC_35 0: Sector protected WRT_PROT_SEC_34 0: Sector protected WRT_PROT_SEC_33 0: Sector protected WRT_PROT_SEC_32 0: Sector protected SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 710 0: Sector protected WRT_PROT_SEC_78 0: Sector protected WRT_PROT_SEC_77 0: Sector protected WRT_PROT_SEC_76 0: Sector protected WRT_PROT_SEC_75 0: Sector protected WRT_PROT_SEC_74 0: Sector protected Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 711 0: Sector protected WRT_PROT_SEC_68 0: Sector protected WRT_PROT_SEC_67 0: Sector protected WRT_PROT_SEC_66 0: Sector protected WRT_PROT_SEC_65 0: Sector protected WRT_PROT_SEC_64 0: Sector protected SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 712 0: Sector protected WRT_PROT_SEC_110 0: Sector protected WRT_PROT_SEC_109 0: Sector protected WRT_PROT_SEC_108 0: Sector protected WRT_PROT_SEC_107 0: Sector protected WRT_PROT_SEC_106 0: Sector protected Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 713: Factory Configuration (Fcfg)
Some of the more useful fields in FCFG are MAC_15_4_* fields, which give the preprogrammed IEEE address of the chipset and the MAC_BLE_* fields that give the Bluetooth Smart address of the chipset. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 714: Fcfg1 Registers
LDO Trim Section 9.2.1.41 2E8h MAC_BLE_0 MAC BLE Address 0 Section 9.2.1.42 2ECh MAC_BLE_1 MAC BLE Address 1 Section 9.2.1.43 714 Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 715 Power Down Current Control 95C Section 9.2.1.77 3B4h PWD_CURR_110C Power Down Current Control 110C Section 9.2.1.78 3B8h PWD_CURR_125C Power Down Current Control 125C Section 9.2.1.79 SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 716 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 717 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 718 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 719 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 720 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 721 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 722 RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 723 RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 724 RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 725 RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 726 RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 727 RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 728 Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 729 Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 730 Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 731 Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 732 Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 733 Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 734 Table 9-42. SHDW_DIE_ID_0 Register Field Descriptions Field Type Reset Description 31-0 ID_31_0 Shadow of EFUSE:DIE_ID_0, ie efuse row number 3 Reset depends on eFuse value. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 735 Table 9-43. SHDW_DIE_ID_1 Register Field Descriptions Field Type Reset Description 31-0 ID_63_32 Shadow of EFUSE:DIE_ID_1, ie efuse row number 4 Reset depends on eFuse value. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 736 Table 9-44. SHDW_DIE_ID_2 Register Field Descriptions Field Type Reset Description 31-0 ID_95_64 Shadow of EFUSE:DIE_ID_2, ie efuse row number 5 Reset depends on eFuse value. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 737 Table 9-45. SHDW_DIE_ID_3 Register Field Descriptions Field Type Reset Description 31-0 ID_127_96 Shadow of EFUSE:DIE_ID_3, ie efuse row number 6 Reset depends on eFuse value. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 738 11 Reset depends on eFuse value. RCOSCHF_CTRIM Shadow of EFUSE:OSC_BIAS_LDO_TRIM.RCOSCHF_CTRIM, ie in efuse row number 11 Reset depends on eFuse value. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 739 12 Reset depends on eFuse value. TRIMTEMP Shadow of EFUSE:ANA_TRIM.TRIMTEMP, ie in efuse row number Reset depends on eFuse value. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 740 Type Reset Description 31-0 LOT_NUMBER Number of the manufacturing lot that produced this unit. Reset holds log information from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 741 Reset holds log information from production test. 15-0 YCOORDINATE Y coordinate of this unit on the wafer. Reset holds log information from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 742 Erase verify setup time in cycles. Value will be written to FLASH:FSM_PE_VSU.ERA_VSU by the flash device driver when an erase/program operation is initiated. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 743 Address->EXECUTEZ setup time in cycles. Value will be written to FLASH:FSM_CMP_VSU.ADD_EXZ by the flash device driver when an erase/program operation is initiated.. 11-0 CVSU Compaction verify setup time in cycles. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 744 FLASH:FSM_PE_VH.PGM_VH when an erase/program operation is initiated. PVH2 Program verify row switch time in half-microseconds. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 745 FLASH:FSM_VSTAT.VSTAT_CNT when an erase/program operation is initiated. 11-0 SM_FREQUENCY Max FCLK frequency allowed for program, erase, and verify reads. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 746 The actual FMC register value should be one less than this since the FMC starts counting from zero. Value will be written to FLASH:FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT when an erase/program operation is initiated. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 747 15-0 MAX_PP Max program pulse limit per program operation. Value will be written to FLASH:FSM_PRG_PUL.MAX_PRG_PUL when an erase/program operation is initiated. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 748 FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_PRG_PW.PROG_PUL_WIDTH when a erase/program operation is initiated. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 749 FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_ERA_PW.FSM_ERA_PW when a erase/program operation is initiated. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 750 VHV_E Value will be written to FLASH:FVHVCT1.VHVCT_E by the flash device driver when an erase/program operation is initiated Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 751 Reset holds trim value from production test. VINH Inhibit voltage applied to unselected columns during programming. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 752 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Reset holds trim value from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 753 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Reset differs depending on partnumber. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 754 FW by setting FLASH:CFG.CONFIGURED. Reset differs depending on partnumber. WAIT_SYSCODE Value will be written to FLASH:WAIT_SYSCODE.WAIT_SYSCODE by boot FW code while in safezone. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 755 Value will be written to ADI_3_REFSYS:DCDCCTL4.DEADTIME_TRIM by boot FW while in safezone. DCDC_LOW_EN_SEL Value will be written to ADI_3_REFSYS:DCDCCTL4.LOW_EN_SEL by boot FW while in safezone. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 756 Table 9-63. ANA2_TRIM Register Field Descriptions (continued) Field Type Reset Description DCDC_HIGH_EN_SEL Value will be written to ADI_3_REFSYS:DCDCCTL4.HIGH_EN_SEL by boot FW while in safezone. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 757 VTRIM_DELTA Value will be written to ADI_2_REFSYS:SOCLDOCTL2.VTRIM_DELTA by boot FW while in safezone. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 758 Type Reset Description 31-0 ADDR_0_31 The first 32-bits of the 64-bit MAC BLE address Reset holds trim value from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 759 Type Reset Description 31-0 ADDR_32_63 The last 32-bits of the 64-bit MAC BLE address Reset holds trim value from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 760 Type Reset Description 31-0 ADDR_0_31 The first 32-bits of the 64-bit MAC 15.4 address Reset holds trim value from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 761 Type Reset Description 31-0 ADDR_32_63 The last 32-bits of the 64-bit MAC 15.4 address Reset holds trim value from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 762 If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is initiated. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 763 FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 764 TEMPVSLOPE Signed byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 765 Change in CTRIM trim 15-8 CTRIMFRACT_QUAD Temp compensation quadratic CTRIMFRACT CTRIMFRACT_SLOPE Number of CTRIMFRACT codes per 20 degrees C from default temperature SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 766 Reset holds log information from production test. 15-0 The revision of the ATE Trim&Calc document used in MP1 in production Reset holds log information from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 767 Field used to distinguish between different silicon revisions of the device. 27-12 WAFER_ID B99Ah Field used to identify silicon die. 11-0 MANUFACTURER_ID Manufacturer code. 0x02F: Texas Instruments SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 768 This revision number must be incremented by 1 before any devices are to be produced if the FCFG1 layout has changed since the previous production of devices. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 769 The revision of the test program used in the production process when FCFG1 was programmed. Reset holds log information from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 770 GPIO_CNT This value is written to IOC:CFG.GPIO_CNT by boot FW while in safezone. Reset differs depending on partnumber. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 771 Trim value for ADI_0_RF:IFALDO2.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Reset holds trim value from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 772 Trim value for DDI_0_OSC:ANABYPASSVAL1.XOSC_HF_COLUMN_Q12. RCOSCLF_CTUNE_TRIM R Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_CTUNE_TRIM. Reset holds trim value from production test. RCOSCLF_RTUNE_TRIM R Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_RTUNE_TRIM. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 773 Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Reset holds trim value from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 774 Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Reset holds trim value from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 775 SOC_ADC gain in absolute reference mode at temperature 1 (30C). EMP1 Calculated in production test.. Reset holds log information from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 776 SOC_ADC gain in relative reference mode at temperature 1 (30C). EMP1 Calculated in production test.. Reset holds trim value from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 777 SOC_ADC gain in external reference mode at temperature 1 (30C). EMP1 Calculated in production test.. Reset holds trim value from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 778 SOC_ADC offset in absolute reference mode at temperature 1 T_TEMP1 (30C). Signed 8-bit number. Calculated in production test.. Reset holds trim value from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 779 SOC_ADC_REF_VOLTA Value to write in ADI_4_AUX:ADCREF1.VTRIM at temperature 1 GE_TRIM_TEMP1 (30C). Reset holds trim value from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 780 IBIAS and CAP trim open loop count. CAP_REM is remainder of the CAP that is left to reach the final cap value. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 781 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 782 Do not need to program this. CAP_TRIM = CAP_INIT - CAP_STEP*IBIASCAP_HPTOLP_OL_CNT - CAP_REM; IBIAS_TRIM = IBIAS_INIT - 1*IBIASCAP_HPTOLP_OL_CNT; Here, cap_init is decimal conversion of cap_init_col and cap_init_row. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 783 13-0 XOSC_HF_IBIASTHERM 3FFh Value of xosc_hf_ibiastherm when oscdig is bypassed. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 784 Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 785 TRIMBOD_H Trim value for 2.0V VDDS BOD target found in production test. Reset holds trim value from production test. SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 786 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Reset holds trim value from production test. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 787 CAP (measured in production test) 15-0 FLUX_CAP_0P4_TRIM FFFFh Reserved storage of measurement value on 0.4um pitch FLUX CAP (measured in production test) SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 788 Trim value for ESET_VOLTAGE DDI_0_OSC:ADCDOUBLERNANOAMPCTL.DBLR_LOOP_FILTER_ RESET_VOLTAGE. 19-10 HPM_IBIAS_WAIT_CNT 100h Trim value for DDI_0_OSC:RADCEXTCFG.HPM_IBIAS_WAIT_CNT. LPM_IBIAS_WAIT_CNT Trim value for DDI_0_OSC:RADCEXTCFG.LPM_IBIAS_WAIT_CNT. IDAC_STEP Trim value for DDI_0_OSC:RADCEXTCFG.IDAC_STEP. Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 789 Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum powerdown current, in units of 0.5uA SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 790 Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum powerdown current, in units of 0.5uA Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 791 Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum powerdown current, in units of 0.5uA SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 792 Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum powerdown current, in units of 0.5uA Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 793 Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum powerdown current, in units of 0.5uA SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 794 Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum powerdown current, in units of 0.5uA Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 795 Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum powerdown current, in units of 0.5uA SWCU117A – February 2015 – Revised March 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 796 Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum powerdown current, in units of 0.5uA Device Configuration SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 797: Cryptography
DMA capability. This chapter provides the description and information for configuring the AES engine..........................Topic Page ................. 10.1 AES Cryptoprocessor Overview ..................10.2 Cryptography Registers SWCU117A – February 2015 – Revised March 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 798: Aes Cryptoprocessor Overview
When a block is preloaded, the previous block must finish before additional data can be loaded. Therefore, once the pipeline is full, sequential data blocks can be passed every 32 clock cycles. Cryptography SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 799: Power Management And Sleep Modes
AHB master interface. By default, a little endian-oriented AHB-host system is assumed. When the AHB system is big endian-oriented, the AHB_MST1_BIGEND must be set to 1. SWCU117A – February 2015 – Revised March 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 800: Module Description
0x4002 402C DMACH1LEN 0x0000 0000 Channel 1 DMA Section 10.2.1.8 length 0x4002 4078 DMABUSCFG 0x0000 6000 Master run-time Section 10.2.1.9 parameters 800 Cryptography SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 801 Interrupt-clear Section 10.2.1.37 register 0x4002 478C IRQSET 0x0000 0000 Interrupt-set register Section 10.2.1.38 0x4002 4790 IRQSTAT 0x0000 0000 Interrupt-status Section 10.2.1.39 register SWCU117A – February 2015 – Revised March 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 802 AHB port errors. A port error aborts operations on all serviced channels and prevents further transfers using that port, until the error is cleared by writing to the [DMASWRESET] register. Cryptography SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 803 RAM based on its register settings (including generation of the key store RAM addresses). The AES module supports only DMA write operations to the key store. SWCU117A – February 2015 – Revised March 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 804 AAD data DMA transfer (AES-CCM), which is typically set up as separate input data transfer. Cryptography SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 805 A fundamental component of the AES algorithm is the S-Box. The S-Box provides a unique 8-bit output for each 8-bit input. SWCU117A – February 2015 – Revised March 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 806 AESKEY3__0 - AESKEY3__3 register locations must be written before starting the CBC-MAC operation, which is required to clear these two key registers. Cryptography SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 807 It is advised to write a new length per packet. If the length registers decrement to zero, no new data is processed until a new context or length value is written. SWCU117A – February 2015 – Revised March 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 808 CCM decrypt data n-bit ciphertext block n-bit plaintext block CBC-MAC data n-bit plaintext block no output data SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 809 The Key Size register defines the size of the keys that are written with DMA. The Key Size register should be configured before writing to the [KEYWRITEAREA] register. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 810: Performance
For longer data streams, the data processing time approaches the theoretical maximum throughput. For operations that use the slave interface as alternative for the DMA, the performance depends on the performance of the host CPU. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 811: Programming Guidelines
Clear the interrupt after handling it. • Master control module algorithm selection register must be cleared to zero to switch off the DMA/AHB SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 812 Result data must be read using the same interface as the input data: either using the slave interface or DMA. • The result tag for operations with authentication can be read using the slave interface or DMA. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 813 AESDATAIN0[31:0]: e2bec16b AESDATAIN1[31:0]: 969f402e AESDATAIN2[31:0]: 117e3de9 AESDATAIN3[31:0]: 2a179373 Output data using slave interface or DMA: AESDATAOUT0[31:0]: bdd1eef3 AESDATAOUT1[31:0]: 3ca0d2b5 AESDATAOUT2[31:0]: 7e5a4b06 AESDATAOUT3[31:0]: f881b13d SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 814 The length field may also be zero, for continued processing. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 815 If the result IV must be read by the host, the save_context bit must be set to 1 after processing the programmed number of bytes. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 816 AESCTL[30]==’1’ // wait for SAVED_CONTEXT_RDY bit [30] read AESIV_0 read AESIV_3 // this read clears the SAVED_CONTEXT_RDY flag endif // end of algorithm SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 817 AESCTL[30]==’1’ // wait for the SAVED_CONTEXT_RDY bit [30] read AESTAGOUT__0 - AESTAGOUT__3 // this read clears the SAVED_CONTEXT_RDY flag // end of algorithm SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 818 AESAUTHLEN // write the length of the AAD data block // (may be non-block size aligned) // configure DMAC to fetch the AAD data SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 819 10.1.6.4.2 External Port Errors The AHB master interface and the DMAC inside the crypto core can detect AHB port errors received through the AHB_ERR signal. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 820: Conventions And Compliances
Federal Information Processing Standard Gigabyte Gbit Giga bit Gbps Giga bits per second HMAC Hashed MAC Hardware Integer Counter Mode IETF Internet Engineering Task Force SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 821 , while tag is used for authenticated encryption operations (AES-CCM). Crypto context Collection of parameters that define the crypto operation: mode, key, IV, and so forth. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 822: Cryptography Registers
11 and least significant bit 3. 10.1.7.2 Compliances AES encryption in ECB and CBC modes complies with FIPS-197. 10.2 Cryptography Registers SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 823: Crypto Registers
Interrupt Clear Section 10.2.1.37 78Ch IRQSET Interrupt Set Section 10.2.1.38 790h IRQSTAT Interrupt Status Section 10.2.1.39 7FCh HWVER CTRL Module Version Section 10.2.1.40 SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 824 Round Robin scheme. 0h = Priority low 1h = Priority high DMA Channel 0 Control 0h = Channel disabled 1h = Channel enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 825 Field Type Reset Description 31-0 ADDR Channel external address value. Holds the last updated external address after being sent to the master interface. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 826 Note: Writing a non-zero value to this register field starts the transfer if the channel is enabled by setting DMACH0CTL.EN. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 827 This register field indicates if DMA channel 1 is active or not. 0: Not active 1: Active CH0_ACTIVE This register field indicates if DMA channel 0 is active or not. 0: Not active 1: Active SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 828 Software reset enable 0: Disable 1: Enable (self-cleared to zero). Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE and DMASTAT.CH1_ACTIVE. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 829 DMA operation. The ongoing block transfer will be completed, but no new transfers will be requested. 0h = Channel disabled 1h = Channel enabled SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 830 Field Type Reset Description 31-0 ADDR Channel external address value. Holds the last updated external address after being sent to the master interface. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 831 Note: Writing a non-zero value to this register field starts the transfer if the channel is enabled by setting DMACH1CTL.EN. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 832 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 833 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 834 Minor version number 19-16 HW_PATCH_LVL Patch level. 15-8 VER_NUM_COMPL Bit-by-bit complement of the VER_NUM field bits. VER_NUM Version number of the DMA Controller (209) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 835 RAM areas are sequential. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 836 RAM areas are sequential. 0h = This RAM area is not selected to be written 1h = This RAM area is selected to be written SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 837 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 838 0h = This RAM area is not written with valid key information 1h = This RAM area is written with valid key information SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 839 For software compatibility KEYWRITTENAREA will be reset when writing to this register. 1h = 128_BIT : 128 bits 2h = 192_BIT : Not supported 3h = 256_BIT : Not supported SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 840 4h = RAM Area 4 5h = RAM Area 5 6h = RAM Area 6 7h = RAM Area 7 8h = No RAM SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 841 = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register array. The interpretation of this field depends on the crypto operation mode. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 842 = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register arrary. The interpretation of this field depends on the crypto operation mode. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 843 Table 10-28. AESIV_0 to AESIV_3 Register Field Descriptions Field Type Reset Description 31-0 The interpretation of this field depends on the crypto operation mode. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 844 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 845 NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 846 Description 31-0 LEN_LSW Used to write the Length values to the Crypto peripheral. This register contains bits [31:0] of the combined data length. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 847 Crypto peripheral. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 848 Once processing with this context is started, this length decrements to zero. Writing this register triggers the engine to start using this context for CCM. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 849 Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 850 GCM, CCM and CBC- MAC. For CTR mode, the remaining data in an unaligned data block is ignored. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 851 Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 852 GCM, CCM and CBC- MAC. For CTR mode, the remaining data in an unaligned data block is ignored. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 853 Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 854 GCM, CCM and CBC- MAC. For CTR mode, the remaining data in an unaligned data block is ignored. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 855 Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 856 GCM, CCM and CBC- MAC. For CTR mode, the remaining data in an unaligned data block is ignored. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 857 Table 10-41. AESTAGOUT_0 to AESTAGOUT_3 Register Field Descriptions Field Type Reset Description 31-0 This register contains the authentication TAG for the combined and authentication-only modes. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 858 If set to 1, selects the Key Store to be loaded via DMA. The maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16, 24 and 32 bytes are allowed) SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 859 Select AHB transfer protection control for DMA transfers using the key store area as destination. 0 : transfers use 'USER' type access. 1 : transfers use 'PRIVILEGED' type access. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 860 Writing 0 has no effect. The bit is self cleared after executing the reset. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 861 Interrupt enable. This bit must be set to 1 to enable interrupts from the Crypto peripheral. 0 : All interrupts are disabled enabled. 1 : All interrupts are enabled. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 862 DMA_IN_DONE This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. RESULT_AVAIL This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 863 DMA_IN_DONE If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. RESULT_AVAIL If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 864 If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. Writing 0 has no effect. RESULT_AVAIL If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. Writing 0 has no effect. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 865 This bit returns the status of DMA data in done interrupt. RESULT_AVAIL This bit is set high when the Crypto peripheral has a result available. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 866 Crypto peripheral register is indeed read. VER_NUM The version number for the Crypto peripheral, this field contains the value 120 (decimal) or 0x78. SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 867: O Control
....................... 11.7 GPIO ....................11.8 I/O Pin Mapping ..................11.9 Peripheral PORTIDs ......................11.10 I/O Pin ..................11.11 I/O Control Registers SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 868: Introduction
AON PERIPH AON Peripherals toe_nt AON/AUX MUX tiet tdit TMS Pin tdot Latch CTRL toe_nt bmon_level DEBUG AON BATMON I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 869: I/O Mapping And Configuration
PA enable RFC_GPO2 0x31 RF Core Data Out 2 TX start RFC_GPO3 0x32 RF Core Data Out 3 Synth calibration running SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 870: Map 32-Khz System Clock (Lf Clock) To Dio/Pin
AUX domain. There are more constraints and reliability issues to consider before powering off a domain; for more details refer to . I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 871: Unused I/O Pins
4. Toggle the DIO1 output by issuing an XOR operation on the [GPIO:DOUT3_0:DIO1] bit with 0x100. 5. Call the following driver library functions: IOCPinTypeGpioOutput(0x1); GPIOPinToggle(0x1); SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 872: I/O Pin Mapping
2 mA / 4 mA 2 mA / 4 mA 2 mA / 4 mA 2 mA / 4 mA CC13xx does not have DIO0. I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 873: Peripheral Portids
11-2, which gives a rough overview of the analog pin stage. Pullup and pulldown resistances are given in the data sheet. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 874: Pin Configuration
Enables or disables the I/O input driver. • Output Driver (Depends on specific peripheral mapped to pin) Enables or disables the I/O output driver. I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 875: I/O Control Registers
I/O Control Registers www.ti.com 11.11 I/O Control Registers SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 876: Aon_Ioc Registers
Section 11.11.1.2 IOSTRMAX IO Drive Strength Maximum Section 11.11.1.3 IOCLATCH IO Latch Control Section 11.11.1.4 CLK32KCTL SCLK_LF External Output Control Section 11.11.1.5 I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 877 31-3 RESERVED Internal. Only to be used through TI provided API. GRAY_CODE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 878 31-3 RESERVED Internal. Only to be used through TI provided API. GRAY_CODE Internal. Only to be used through TI provided API. I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 879 31-3 RESERVED Internal. Only to be used through TI provided API. GRAY_CODE Internal. Only to be used through TI provided API. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 880 1h = Latches are transparent, meaning the value of the IO is directly controlled by the GPIO or peripheral value I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 881 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. IOC:IOCFG0.PORT_ID) set to AON_CLK32K. 1: Output enable not active SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 882 I/O Control Registers www.ti.com I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 883: Ioc Registers
Configuration of DIO28 Section 11.11.2.29 IOCFG29 Configuration of DIO29 Section 11.11.2.30 IOCFG30 Configuration of DIO30 Section 11.11.2.31 IOCFG31 Configuration of DIO31 Section 11.11.2.32 SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 884 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 885 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 886 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 887 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 888 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 889 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 890 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 891 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 892 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 893 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 894 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 895 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 896 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 897 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 898 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 899 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 900 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 901 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 902 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 903 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 904 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 905 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 906 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 907 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 908 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 909 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 910 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 911 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 912 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 913 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 914 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 915 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 916 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 917 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 918 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 919 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 920 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 921 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 922 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 923 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 924 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 925 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 926 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 927 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 928 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 929 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 930 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 931 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 932 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 933 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 934 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 935 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 936 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 937 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 938 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 939 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 940 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 941 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 942 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 943 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 944 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 945 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 946 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 947 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 948 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 949 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 950 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 951 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 952 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 953 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 954 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 955 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 956 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 957 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 958 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 959 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 960 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 961 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 962 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 963 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 964 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 965 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 966 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 967 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 968 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 969 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 970 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 971 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 972 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 973 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 974 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 975 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 976 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 977 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 978 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 979 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 980 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 981 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 982 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 983 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 984 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 985 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 986 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 987 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 988 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 989 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 990 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 991 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 992 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 993 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 994 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 995 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 996 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 997 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 998 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 999 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117A – February 2015 – Revised March 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 1000 0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection 1000 I/O Control SWCU117A – February 2015 – Revised March 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...

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