Silicon Laboratories Si1010 User Manual page 24

EBID_MOSI,EBID_MISO,EBID_SCK,EBID_NSEL
IC2
3
VCC
WP
1
EBID_NSEL
CS
5 2
EBID_MOSI EBID_MISO
SI SO
EBID_SCK 6
SCK
C23
7
HOLD
GND
100nF
25AA080C
GND
GND
**** Optional part is NOT MOUNTED.
GPIO2
UPG2214TB6SM
CC1
4 3
VC2 OUT2
ANT
LM2
CC2
56pF
5 2
RF_IN GND
8.2nH
56pF
6 1 GND
VC1 OUT1
GND GND
CM3 CM2
IC4
4.3pF 4.3pF GPIO1
GND GND
Si4432 RevB1 switch matching
915MHz
19.11.2009
C4 C3 C2 C1
RDC
2.2uF
100nF 100pF 33pF
0R
GND GND GND GND
15
16
17
18
19
20
LC
21
120nH
LM L0 C0
12nH
12nH
33pF
LH
CM
CH
3pF
5.6pF 5.6nH
GND GND
RH
CR2 50R
6.8pF
GND
LR
11nH
CR1
3.3pF
GND GND
Figure 14. Si1000 Daughtercard Schematic
VDD_MCU
30MHz
Q3
Q1 32.768kHz
42
SDN XTAL4
P2.6
41
VDD_RF P2.6
40 P2.7/C2D
P2.7/C2D
TX
39 NRST/C2CK
NRST/C2CK
RXP
38
RXN VDD_MCU
37
VR_IF GND4
P0.0
36
NC2 P0.0/VREF
GND
C21 C28
100pF 100nF
SJ1
GND GND
1 2
GND GND GND
SJ4
SJ11
1
1 2 P0.2
100nF
N.F.
C26
C27
100nF
N.F.
SJ12 GND
1 2 P0.3
1k 1k SDN
GPIO0
C16
C17 C11
GPIO2
1uF
100pF 100nF
GPIO1
GND GND GND
32.768 kHz
C20
Q4
N.F.
GND
TEST PINS
NIRQ
P0.0
P0.0
P0.1
P0.1
P0.2
P0.2
P0.3
P0.3
P0.4
P0.4
P0.5
P0.5
P0.6
P0.6
P0.7
P0.7
P1.5
J1 P1.5
1 2 P1.6
P1.6
3 4 P1.7
P1.7
5 6 P2.0(P0.7)
P2.0
7 8 P2.1(P1.4)
P2.1
9 10 P2.2(P1.5)
P2.2
P2.3(P1.6)
P2.3
10 PIN, straith male
P2.4
P2.4
P2.5
P2.5
GND P2.6
P2.6
P2.7/C2D
P2.7/C2D
NRST/C2CK
NRST/C2CK
GND
GND2
GND
VDD2
VDD
2
CS1
P2.2(P1.5) 1 2 P0.7
(P1.2)
P2.0(P0.7) 3 4
(P1.0) (P1.4)
P2.3(P1.6) 5 6 L3
(P1.3)
R8 10k 7 8 P0.0
P0.4 9 10 P0.1
0R
10k
SJ9 P0.5 11 12
SDN
1 2 13 14 P0.2
P0.6 15 16 P2.1(P1.4)
(P1.1)
17 18 L4
19 20
21 22 P0.3
0R
C24
P1.5
(DCEN) 23 24
(VBAT) 25 26 EBID_MOSI
1uF
P2.4 27 28 EBID_MISO
R7 10k
GND
29 30 EBID_SCK
P2.5 31 32 EBID_NSEL
SJ6
1 2 33 34 P1.6
GND
P2.6 P1.7
35 36
SJ5
1 2 37 38 P2.7/C2D
(GND/DC) 39 40 NRST/C2CK
CON40-0
GND
C25
1uF
GND