Supermicro SuperServer 1029GP-TR User Manual page 34

SuperServer 1029GP-TR User's Manual
P1/P2- P1/P2-
Modes
DIMMF1 DIMME1
AD DRAM1 DRAM1
MM DRAM2 DRAM2
AD + MM DRAM3 DRAM3
AD DCPMM DRAM1
MM DCPMM DRAM1
AD + MM DCPMM DRAM3
AD: App Direct, MM: Memory Mode
Asymmetric Population within One CPU Socket
P1/P2 P1/P2
Modes
DIMMF1 DIMME1
AD DRAM1 DRAM1
AD* DRAM1 DRAM1
*Second socket has no DCPMM
DDR4 Type
DRAM1 RDIMM
DRAM2 RDIMM
DRAM3 RDIMM
Note: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct Mode.
Validation Matrix (DDR4 DIMMs Validated with DCPMM)
DIMM Type
RDIMM
LRDIMM
LRDIMM 3DS
•
For MM, general NM/FM ratio is between 1:4 and 1:16. Excessive capacity for FM can
be used for AD. (NM = Near Memory; FM = Far Memory)
•
For each individual population, rearrangements between channels are allowed as long
as the resulting population is compliant with the PDG rules for the 82xx/62xx/52xx/42xx
platform.
•
For each individual population, please use the same DDR4 DIMM in all slots.
•
For each individual population, sockets are normally symmetric with exceptions for 1
DCPMM per socket and 1 DCPMM per node case. Currently, DCPMM modules oper-
ate at 2666 MHz.
•
No mixing of DCPMM and NVMDIMMs within the same platform is allowed.
•
This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM
and MM + AD modes.
Symmetric Population within One CPU Socket
P1/P2- P1/P2-
DIMMD1 DIMMD2
DRAM1 DCPMM
DRAM2 DCPMM
DRAM3 DCPMM
DRAM1
DRAM1
DRAM3
P1/P2 P1/P2
DIMMD1 DIMMD2
DRAM1 -
DRAM1 -
Legend (for the tables above)
3DS RDIMM LRDIMM 3DS LRDIMM
- -
3DS RDIMM LRDIMM -
Ranks Per DIMM
& Data Width
(Stack)
1Rx4
2Rx8
2Rx4
4Rx4
8Rx4 (4H)
P1/P2- P1/P2- P1/P2-
DIMMA2 DIMMA1 DIMMB1
DCPMM DRAM1 DRAM1
DCPMM DRAM2 DRAM2
DCPMM DRAM3 DRAM3
DRAM1 DRAM1
DRAM1 DRAM1
DRAM3 DRAM3
P1/P2 P1/P2 P1/P2
DIMMA2 DIMMA1 DIMMB1
DCPMM DRAM1 DRAM1
DCPMM DRAM1 DRAM1
Capacity
Any Capacity
Refer to Validation Matrix below.
DIMM Capacity (GB)
DRAM Density
4Gb 8Gb
8GB 16GB
8GB 16GB
16GB 32GB
N/A 64GB
N/A 128GB
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P1/P2- Channel
DIMMC1 Config.
DRAM1 2-1-1
DRAM2 2-1-1
DRAM3 2-1-1
DCPMM 1-1-1
DCPMM 1-1-1
DCPMM 1-1-1
P1/P2 Channel
DIMMC1 Config.
DRAM1 2-1-1
DRAM1 2-1-1