Analog Inputs - Digilent Cmod S7 Reference Manual

22.8.2018
(https://reference.digilentinc.com/_detail/reference/programmable-logic/cmod-s7/cmod-s7-dip.png?id=reference%3Aprogrammable-logic%3Acmod-
s7%3Areference-manual)
Figure 7.1 DIP Pin Diagram
VU (pin 24) can be used to power the Cmod S7 when it is not connected to a USB Host. When the device is connected to a USB host,
VU is driven by the 5V rail of the USB connector and can be used to power devices external to the Cmod S7. See the Power Supplies
section for more information.
7.1 DIP Digital I/O
The pins directly connected to the FPGA can be used as general purpose inputs or outputs. Each of these pins is connected to the
FPGA via a 240 Ohm series resistor. The series resistors prevent short circuits that can occur if a user accidentally drives a signal that is
supposed to be used as an input. The downside to this added protection is that these resistors limit the maximum switching speed of
these signals to 25 MHz (). These pins support input voltages of up to 3.5V.
For more information on the electrical characteristics of these pins, please see Xilinx's
(https://www.xilinx.com/support/documentation/data_sheets/ds189-spartan-7-data-sheet.pdf)

7.2 Analog Inputs

Pins 32 and 33 of the DIP headers are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs
range from 0V-1V, so resistor-divider circuits are used on the Cmod S7 to scale down the input voltage from 3.3V. This circuit is shown
in Figure 7.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to GND () on pin
25) that is applied to these pins. The analog inputs can tolerate input voltages of up to 5.5V, though any voltage above 3.3V will be read
as 3.3V by the XADC module.
https://reference.digilentinc.com/reference/programmable-logic/cmod-s7/reference-manual
Cmod S7 Reference Manual [Reference.Digilentinc]
Spartan-7 Datasheet
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