Sony HAP-Z1ES Service Manual page 90

HAP-Z1ES
FPGA DSP BOARD IC601 ADSP-21488KSWZ-3A1 (AUDIO DSP)
Pin No. Pin Name
1 VDD_INT
2 CLK_CFG1
3 BOOT_CFG0
4 VDD_EXT
5 VDD_INT
6 BOOT_CFG1
7 GND
8, 9 NC
10 CLK_CFG0
11 VDD_INT
12 CLKIN
13 XTAL
14 VDD_EXT
15, 16 VDD_INT
nRESETOUT/
17
nRESETIN
18 VDD_INT
19 DPI_P01
20 DPI_P02
21 DPI_P03
22 VDD_INT
23 DPI_P05
24 DPI_P04
25 DPI_P06
26 VDD_EXT
27, 28 DPI_P08, DPI_P07
29 VDD_INT
DPI_P09 to DPI_P13,
30 to 36
DAI_P03, DAI_P14
37 to 39 VDD_INT
40 DAI_P13
41 DAI_P07
42 DAI_P19
43, 44 DAI_P01, DAI_P02
45 VDD_INT
46 VDD_EXT
47 VDD_INT
48 DAI_P06
49 DAI_P05
50 DAI_P09
51 DAI_P10
52 VDD_INT
53 VDD_EXT
54 DAI_P20
55 VDD_INT
DAI_P08, DAI_P04,
56 to 63 DAI_P14, DAI_P18 to
DAI_P15, DAI_P12
64 VDD_INT
65 DAI_P11
66, 67 VDD_INT
68 GND
69 THD_M
70 THD_P
71 VDD_THD
72 to 76 VDD_INT
77 FLAG0
90
I/O
- Power supply terminal (+1.1V) (for core)
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
I
Fixed at "H" in this unit
I Boot mode selection signal input terminal
- Power supply terminal (+3.3V) (for I/O)
- Power supply terminal (+1.1V) (for core)
I Boot mode selection signal input terminal
- Ground terminal
- Not used
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
I
Fixed at "L" in this unit
- Power supply terminal (+1.1V) (for core)
I System clock input terminal (10 MHz)
O System clock output terminal (10 MHz)
- Power supply terminal (+3.3V) (for I/O)
- Power supply terminal (+1.1V) (for core)
I/O Reset signal input/output terminal
- Power supply terminal (+1.1V) (for core)
I Serial data input from the FPGA
O Serial data output to the FPGA
I Serial data transfer clock signal input from the FPGA
- Power supply terminal (+1.1V) (for core)
I/O Not used
I Chip select signal input from the FPGA
I/O Not used
- Power supply terminal (+3.3V) (for I/O)
I/O Not used
- Power supply terminal (+1.1V) (for core)
I/O Not used
- Power supply terminal (+1.1V) (for core)
I Bit clock signal input from the FPGA
I L/R sampling clock signal input from the FPGA
I Audio data input from the FPGA
I/O Not used
- Power supply terminal (+1.1V) (for core)
- Power supply terminal (+3.3V) (for I/O)
- Power supply terminal (+1.1V) (for core)
I Bit clock signal input from the FPGA
I L/R sampling clock signal input from the FPGA
O Audio data output to the FPGA
I/O Not used
- Power supply terminal (+1.1V) (for core)
- Power supply terminal (+3.3V) (for I/O)
I/O Not used
- Power supply terminal (+1.1V) (for core)
I/O Not used
- Power supply terminal (+1.1V) (for core)
I Interrupt request signal input from the FLAG0 (pin 77)
- Power supply terminal (+1.1V) (for core)
- Ground terminal
O Thermal diode cathode output terminal
I Thermal diode anode input terminal
- Power supply terminal (for thermal diode)
- Power supply terminal (+1.1V) (for core)
O Interrupt request signal output to the DAI_P11 (pin 65)
Description
Fixed at "L" in this unit
Fixed at "L" in this unit
Not used
Not used
Not used
Not used