Sony HAP-Z1ES Service Manual page 75

• IC Pin Function Description
MAIN BOARD IC101 MCIMX6D5EYM10AC (MPU)
Pin No. Pin Name
A2 PCIE_REXT
A3 PCIE_TXM
A4 GND3
A5 FA_ANA
A6 USB_OTG_DP
A7 XTALI
A8 GND4
A9 MLB_SN
A10 MLB_DP
A11 MLB_CN
A12 SATA_TXP
A13 GND1
A14 SATA_RXM
A15 SD3_DAT2
A16 NANDF_ALE
A17 NANDF_CS2
A18 NANDF_D0
A19 NANDF_D4
A20 SD4_DAT3
A21 SD1_DAT0
SD2_DAT0,
A22, A23
SD2_DAT2
A24 RGMII_TD3
A25 GND2
B1 PCIE_RXM
B2 PCIE_RXP
B3 PCIE_TXP
B4 GND22
B5 VDD_FA
B6 USB_OTG_DN
B7 XTALO
B8 USB_OTG_CHD_B
B9 MLB_SP
B10 MLB_DN
B11 MLB_CP
B12 SATA_TXM
B13 SD3_CMD
B14 SATA_RXP
B15 SD3_DAT3
B16 NANDF_RB0
B17 SD4_CMD
B18 NANDF_D5
SD4_DAT1,
B19, B20
SD4_DAT6
B21 SD1_CMD
B22 SD2_DAT3
RGMII_RD1,
B23, B24
RGMII_RD2
B25 RGMII_RXC
C1 GND23
C2 JTAG_TRSTB
C3 JTAG_TMS
C4 GND25
C5 CLK2_N
C6 GND26
C7 CLK1_N
C8 GPANAIO
I/O
- Terminal for the Impedance calibration
O Transmit data (negative) output to the FPGA
- Ground terminal
- Not used
I/O Two-way USB data (positive) with the USB connector
I System clock input terminal (24 MHz)
- Ground terminal
- Not used
- Not used
- Not used
O Transmit data (positive) output to the hard disk drive
- Ground terminal
I Receive data (negative) input from the hard disk drive
I/O Two-way data bus terminal
O Reset signal output to the system controller
- Not used
I/O Two-way data bus terminal
- Not used
I/O Two-way data bus with the fl ash memory
I/O Two-way data bus terminal
- Not used
O RGMII transmit data output to the ethernet transceiver
- Ground terminal
I Receive data (negative) input from the FPGA
I Receive data (positive) input from the FPGA
O Transmit data (positive) output to the FPGA
- Ground terminal
- Not used
I/O Two-way USB data (negative) with the USB connector
O System clock output terminal (24 MHz)
- Not used
- Not used
- Not used
- Not used
O Transmit data (negative) output to the hard disk drive
- Not used
I Receive data (positive) input from the hard disk drive
- Not used
O Interrupt signal output to the remote commander code learning processor
O Command signal output to the fl ash memory
- Not used
I/O Two-way data bus with the fl ash memory
- Not used
- Not used
I RGMII receive data input from the ethernet transceiver
I RGMII receive clock signal input from the ethernet transceiver
- Ground terminal
- Not used
- Not used
- Ground terminal
- Not used
- Ground terminal
O Clock signal (negative) output to the FPGA
- Not used
Description
Not used
"H": reset
Not used
Not used
HAP-Z1ES
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