Sony HAP-Z1ES Service Manual page 81

Pin No. Pin Name
GPIO_2, GPIO_9,
T1 to T5 GPIO_6, GPIO_1,
GPIO_0
T6 KEY_COL4
T7 KEY_ROW3
T8 GND84
T9 VDDARM23_IN7
T10 VSSSOC_CAP2
T11, T12 GND79, GND80
VSSSOC_CAP3,
T13, T14
VSSSOC_CAP4
T15 GND81
T16 VDDSOC_IN9
T17 GND82
T18 NVCC_DRAM2
T19 GND83
DISP0_DAT21,
T20, T21
DISP0_DAT16
DISP0_DAT15,
T22 to DISP0_DAT11,
T25 DISP0_DAT12,
DISP0_DAT9
U1 LVDS0_TX0_P
U2 LVDS0_TX0_N
U3 LVDS0_TX1_P
U4 LVDS0_TX1_N
U5 KEY_COL3
U6 KEY_ROW1
U7 KEY_COL1
U8 GND89
U9 VDDARM23_IN8
U10 VSSSOC_CAP5
U11, U12 GND85, GND86
VSSSOC_CAP6,
U13, U14
VSSSOC_CAP7
U15 GND87
U16 VDDSOC_IN10
U17 GND88
U18 NVCC_DRAM3
U19 GND90
U20 ENET_TXD0
U21 ENET_CRS_DV
DISP0_DAT20,
U22 to
DISP0_DAT19,
U24
DISP0_DAT17
U25 DISP0_DAT14
V1 LVDS0_TX2_P
V2 LVDS0_TX2_N
V3 LVDS0_CLK_P
V4 LVDS0_CLK_N
KEY_ROW4,
V5, V6
KEY_ROW0
V7 NVCC_LVDS2P5
V8 GND91
NVCC_DRAM13,
V9 to
NVCC_DRAM4 to
V18
NVCC_DRAM12
V19 GND92
V20 ENET_MDC
V21 ENET_TX_EN
V22 ENET_REF_CLK
V23 ENET_MDIO
I/O
- Not used
- Not used
O Liquid crystal display dimmer control signal output terminal
- Ground terminal
- Power supply terminal for the cores regulator
O Internal regulator output terminal (+1.1V)
- Ground terminal
O Internal regulator output terminal (+1.1V)
- Ground terminal
- Power supply terminal for the SOC and PU regulators (+1.42V)
- Ground terminal
- Power supply terminal for the DDR interface (+1.5V)
- Ground terminal
O RGB signal (red) output to the liquid crystal display
O RGB signal (green) output to the liquid crystal display
- Not used
- Not used
- Not used
- Not used
O Liquid crystal display dimmer control signal output terminal
- Not used
- Not used
- Ground terminal
- Power supply terminal for the cores regulator
O Internal regulator output terminal (+1.1V)
- Ground terminal
O Internal regulator output terminal (+1.1V)
- Ground terminal
- Power supply terminal for the SOC and PU regulators (+1.42V)
- Ground terminal
- Power supply terminal for the DDR interface (+1.5V)
- Ground terminal
O Power on/off control signal output terminal for the liquid crystal display
O Reset signal output to the ethernet transceiver
O RGB signal (red) output to the liquid crystal display
O RGB signal (green) output to the liquid crystal display
- Not used
- Not used
- Not used
- Not used
- Not used
- Power supply terminal for the LVDS display interface (+2.5V)
- Ground terminal
- Power supply terminal for the DDR interface (+1.5V)
- Ground terminal
O Management data clock signal output to the ethernet transceiver
- Not used
I 25 MHz clock signal input from the ethernet transceiver
I/O Two-way management data bus with the ethernet transceiver
Description
Not used
Not used
"L": reset
HAP-Z1ES
"H": power on
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