Sony HAP-Z1ES Service Manual page 77

Pin No. Pin Name
E21 RGMII_TD2
E22 EIM_EB2
E23 EIM_D22
E24, E25 EIM_D26, EIM_D27
F1 CSI_D3P
F2 CSI_D3M
F3 CSI_CLK0P
F4 CSI_CLK0M
F5 to F8 GND33 to GND36
F9 VDDUSB_CAP1
F10 USB_H1_DN
F11 PMIC_STBY_REQ
F12 BOOT_MODE1
F13 SD3_DAT7
F14 SD3_DAT1
F15 NANDF_CS0
F16 NANDF_D2
F17 SD4_DAT2
F18 SD1_DAT3
F19 SD2_CMD
F20 RGMII_TD1
F21, F22 EIM_D17, EIM_D24
F23 EIM_EB3
F24, F25 EIM_A22, EIM_A24
G1 DSI_D0P
G2 DSI_D0M
G3 GND39
G4 DSI_REXT
G5 JTAG_TDI
G6 JTAG_TDO
G7 PCIE_VPH
G8 PCIE_VPTX
G9 VDD_SNVS_CAP
G10 GND37
G11 VDD_SNVS_IN
G12 SATA_VPH
G13 SATA_VP
G14 NVCC_SD3
G15 NVCC_NANDF
G16, NVCC_SD1,
G17 NVCC_SD2
G18 NVCC_RGMII
G19 GND38
G20 EIM_D20
G21,
EIM_D19, EIM_D25
G22
G23 EIM_D28
G24,
EIM_A17, EIM_A19
G25
H1 DSI_D1P
H2 DSI_D1M
H3 DSI_CLK0M
H4 DSI_CLK0P
H5 JTAG_TCK
H6 JTAG_MOD
H7 PCIE_VP
H8 GND43
H9 VDDHIGH_IN1
H10 VDDHIGH_CAP1
H11 VDDARM23_CAP1
I/O
O RGMII transmit data output to the ethernet transceiver
I Boot mode setting terminal
O VBUS power on/off control signal output terminal for the USB connector
- Not used
- Not used
- Not used
- Not used
- Not used
- Ground terminal
O Internal regulator output terminal
I/O Two-way USB data (negative) with the WLAN/BT COMBO card
O Not used
I Boot mode setting terminal
- Not used
- Not used
O Power on/off control signal output terminal for the learning circuit power
- Not used
I/O Two-way data bus with the fl ash memory
- Not used
- Not used
O RGMII transmit data output to the ethernet transceiver
- Not used
I Boot mode setting terminal
I Boot mode setting terminal
- Not used
- Not used
- Ground terminal
- Not used
- Not used
- Not used
- Power supply terminal for the PCIe interface (+2.5V)
- Power supply terminal for the PCIe interface (+1.1V)
O Internal regulator output terminal
- Ground terminal
- Power supply terminal for the SNVS Regulator (+3.3V)
- Power supply terminal for the SATA interface (+2.5V)
- Power supply terminal for the SATA interface (+1.1V)
O Internal regulator output terminal
O Internal regulator output terminal
O Internal regulator output terminal
- Power supply terminal for the ENET interface (+1.8V)
- Ground terminal
O Confi guration signal output to the FPGA
- Not used
I Diag mode enable signal input terminal
I Boot mode setting terminal
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used
- Power supply terminal for the PCIe interface (+1.1V)
- Ground terminal
- Power supply terminal for the +2.5V regulator (+3.3V)
O Internal regulator output terminal (+2.5V)
O Internal regulator output terminal
Description
Fixed at "L"
Fixed at "H"
Fixed at "L"
Fixed at "L"
Fixed at "L"
Not used
HAP-Z1ES
"H": power on
"H": power on
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