Datex-Ohmeda Aestiva 7900 SmartVent Technical Reference Manual page 32

2 Theory of Operation
DATA acquisition
2-16
A system reset will occur between 62.5 msec and 250 msec if no legal toggle
addresses occur by that time. Multiple level 7 interrupts will occur prior to a
reset. The output of this watchdog is connected to IRQ7 on the 68340
processor.
Error response sequence
Errors detected by either watchdog are handled in the following sequence:
• At the first detection of any error, a watchdog responds by issuing an IRQ7
interrupt.
• If the exception handler software for IRQ7 cannot correct the error, then the
next detection of an error causes a soft system reset.
• If the error still cannot be corrected, then an audio alarm sounds
(independent of processor interaction) and a cyclic soft reset continues until
the error is corrected or the system is powered down.
The data acquisition system for the Aestiva 7900 Ventilator consists of two
major building blocks. The first is an analog to digital converter (ADC) system
and the second is a digital to analog converter (DAC) system.
This portion of the Aestiva 7900 Ventilator allows the microprocessor to
interface with valves and pressure transducers. The data acquisition system is
also used for internal monitoring of safety relevant signals.
The ADC system is designed to meet the following specifications:
Resolution
Input Voltage Range
Number of Channels
Total Conversion Time
Integral Nonlinearity
Differential Nonlinearity
Full-Scale Error
Unipolar Offset Error
The DAC system is designed to meet the following specifications:
Resolution
Number of Channels
Settling time to 0.01%
Output Voltage Range
Integral Nonlinearity
Differential Nonlinearity
Full-Scale Error
Zero-Scale Error
12 Bits
0 - 4.095 Volts (1mV/LSB)
24
8 to 8.63 µsec max
± 1 LSB max
± 1 LSB max (guaranteed monotonic)
± 6 LSB max
± 3 LSB max
12 Bits
1
30 µsec max
0 - 4.095 Volts (1mV/LSB)
± 1 LSB max
± 1 LSB max (guaranteed monotonic)
± 9 LSB max
+ 4 LSB max
05/04 1006-0453-000