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How to Use the TDA911X and Improve Performances
TDA911x Deflection Processors at a Glance
The TDA911x is a family of deflection processors for multisync monitors, incorporating horizontal
and vertical processing, geometry correction, dynamic corrections (focus and/or brightness etc.),
DC/DC conversion and various safety and auxiliary functions. They are entirely controlled through
an I²C interface.
The TDA9112 was designed as an upgrade of the TDA9109/9111, using the same 32-pin shrink
DIP package. The pin-out remains nearly the same in order to simplify new layouts; however some
minor changes were necessary, mainly to pack more functions inside. Those already familiar with
TDA9109/9111 will recognize all the functions and operation styles they are accustomed to use.
For low- and medium-range applications where certain sophisticated features are not required,
several different economical versions of the TDA9112 are available: TDA9113, TDA9115 and
TDA9116.
Table 1
compatible, with minor exceptions
Recently, the most complete version of the TDA9112 has been upgraded into the higher
performance TDA9112A. Improvements concern mainly geometry and focus corrections, but also
jitter behavior, B+ function, safety and I²C control. The design guidelines provide that the
TDA9112A should operate at once when fitted in the place of an existing TDA9112 (even if the
ideal I²C register settings may differ slightly).
Section 2: Special Features of the TDA9112A
TDA9112A. For a detailed description of each, please refer to the relevant chapters.
1. Hard-wired H Moire function of the TDA9115/9116 replaces the Focus/Brightness functions.
16 Septembre 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
summarizes their respective features. All versions are pin- and software-
1
Revision 1.1
.
summarizes the improvements incorporated in
AN1290
Application Note
1/62
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Summary of Contents for ST TDA911 Series
- Page 1 AN1290 Application Note ® How to Use the TDA911X and Improve Performances TDA911x Deflection Processors at a Glance The TDA911x is a family of deflection processors for multisync monitors, incorporating horizontal and vertical processing, geometry correction, dynamic corrections (focus and/or brightness etc.), DC/DC conversion and various safety and auxiliary functions.
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Page 2: Table Of Contents
AN1290 Table of Contents Chapter 1 Main Characteristics of the TDA9112 Deflection Processor Family ..5 Chapter 2 Special Features of the TDA9112A ........7 Chapter 3 TDA9112 Family Pin Review . - Page 3 AN1290 5.1.14 Breathing Functions in the TDA9112A ....................33 Application Hints ........................ 33 5.2.1 Coupling to Booster ...........................33 5.2.2 Ripple Rejection ..........................34 5.2.3 Vertical Vibration ..........................35 5.2.4 Leakage on Cs ...........................36 Chapter 6 Geometry and Focus Control Section ....... .37 Theory of Operation ......................
- Page 4 AN1290 TDA9112 Family as I²C Bus Device ................... 55 Receiving Data ........................55 Sending Data ........................56 Register Organization ......................56 Management of Status Register and Sync Priority ............58 Chapter 10 I²C Bus Control Register Map ........60 4/62 STMicroelectronics Confidential...
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Page 5: Main Characteristics Of The Tda9112 Deflection Processor Family
AN1290 Main Characteristics of the TDA9112 Deflection Processor Family Main Characteristics of the TDA9112 Deflection Processor Family Control Control of all functions and status reading through I²C interface (status reading is not available with the TDA9115). I²C settings take effect during the Vertical Oscillator Retrace for an improved screen aspect. These parameters can be sent at any moment. - Page 6 Accepts positive and negative H and V sync signals Accepts Composite sync signals with the automatic management of serration pulses Sync on Green is not extracted (this function is available in ST Video preamps) Vertical Moire compensation controlled by I²C programming Horizontal Moire compensation (I²C programming), may be optimized for combined or separate...
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Page 7: Special Features Of The Tda9112A
AN1290 Special Features of the TDA9112A Special Features of the TDA9112A The TDA9112A provides features and performances at least equal to those of the TDA9112, with one exception: the DC/DC converter configuration using an internal oscillator has not been continued because very few customers used it. Software compatibility is maintained. The new or improved functions are listed below and details may be found in the relevant chapters. - Page 8 Special Features of the TDA9112A AN1290 Dynamic Correction (Focus/Brightness) The new composite H/V output can provide any signal polarity (concavity up or down; same polarity for H and V). The signal at horizontal frequency, previously parabolic, may be set to any power index from 2 to 4.
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Page 9: Tda9112 Family Pin Review
AN1290 TDA911x Family Pin Review TDA911x Family Pin Review The main features of the TDA9112, TDA9113, TDA9115 and TDA9116 are described in Table The additional features for the TDA9112A are given in Section 2: Special Features of the TDA9112A. Table 2: TDA911x Pin Descriptions (Sheet 1 of 2) Pin No. - Page 10 TDA911x Family Pin Review AN1290 Table 2: TDA911x Pin Descriptions (Sheet 2 of 2) Pin No. Pin Description When the DC/DC converter is used in the External sawtooth configuration, Pin 16 should receive a sawtooth (less than 2V peak), either representative of the current in the switch (current mode) or provided by an R/C oscillator (open loop).
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Page 11: Chapter 4 Horizontal Section
AN1290 Horizontal Section Horizontal Section Theory of Operation 4.1.1 Horizontal Section Structure The TDA9112 horizontal section is similar to the TDA9109/9111. It includes a sawtooth oscillator, a sync detector, two phase-locked loops (PLLs) and an output stage. Moreover, X-ray protection and PLL1 lock/unlock detection are provided. -
Page 12: Digital Sync Detection
Horizontal Section AN1290 4.1.2 Digital Sync Detection The H/HV sync pulse is detected on pin 1 by a comparator with hysteresis, compatible with the standard TTL. It is intended for digital sync only (separate or composite). The IC synchronizes on the pulse front edge. -
Page 13: Pll1
AN1290 Horizontal Section until the 1.6V threshold is reached; then a new charge phase starts. As a result, the voltage on pin 6 will be a sawtooth with a (6.4-1.6)V amplitude and a period of: æ æ ö ö with∆V ∆T h C 0 x ∆V ---------------- -... -
Page 14: Frequency Precision
Horizontal Section AN1290 When HSync pulses are received, the voltage on pin 9 will increase until the local oscillator matches the incoming frequency. Since the range for pin 9 voltage is between 1.3V and 6.2V, the relative capture frequency range (ratio of maximum to minimum frequency) is: ------- - 4.77 4.1.7... -
Page 15: Pll1 Inhibition
AN1290 Horizontal Section Figure 2: H Oscillator Waveform 6.4V φ PLL2 Threshold 1.6V 12µs Sync pulse Forced OFF Forced ON Range for PLL2 back 4.1.8 PLL1 Inhibition The PLL1 operation remains undisturbed if one (and only one) sync pulse front edge arrives in each horizontal period, in phase with the V point on each sawtooth. -
Page 16: Frequency Change Speed Limitation
Horizontal Section AN1290 When PLL1 endures this severe disturbance, it requires some time to recover the proper phase. As this could entail a visible distortion on top of the screen, the TDA9112 has been provided with a PLL1 inhibition feature: the two current sources of PLL1 will be turned OFF during the Vsync pulse and 2 complete lines later. -
Page 17: Soft-Start
AN1290 Horizontal Section Hex code 00 corresponds to a 65% duty factor. This is the default value at start-up, in order to minimize the stress on the scanning transistor. 4.1.11 Soft-start The TDA9112 is equipped with a self-contained soft-start. When switching ON, HOut will remain inhibited until the supply voltage ramps up to more than 8.5V. -
Page 18: H Moire Cancellation
Horizontal Section AN1290 approximately 4V when it is unlocked. The last elements are an internal comparator referenced to 6.25V (with hysteresis) and a CMOS inverter; you will find on its output pin 3 a HIGH state when PLL1 is unlocked. The same data can also be read in the IC through the I²C bus. Nevertheless, a Read request is necessary in this case. -
Page 19: Application Hints
AN1290 Horizontal Section pitch, the wider the stripes (however, if the dot array is not uniform, the basically vertical stripes will be strongly distorted). Please notice that if the succession of dots is shifted horizontally by half a pixel, the dark and bright stripes will be exchanged. -
Page 20: Output Stage
Horizontal Section AN1290 synchronized to horizontal components in frequency and phase, like those in SMPS, B+ DC/DC converters, PWM DACs, etc. — The ground track should enter the IC area through pin 27, then go to the various ground pins (7, 21, which are not connected internally) and to the H- and V-related components and to no other place. -
Page 21: Enlarging The Frequency Range
AN1290 Horizontal Section Any ripple, non synchronous to horizontal, on the transformer supply capacitor will influence the H-scanning transistor storage time and cause supplementary jitter. If a MOS transistor is used as driver, its Gate-Source capacitance must be charged or discharged at each transition. -
Page 22: X-Ray Protection
Horizontal Section AN1290 4.2.4 X-Ray Protection The X-ray protection is latched; once triggered by a voltage higher than 8V, it stops the IC operation until it is reset by switching the monitor OFF and ON again, or through I²C programming (Sad16h/d7). -
Page 23: Chapter 5 Vertical Section
AN1290 Vertical Section Vertical Section Theory of Operation 5.1.1 Structure of V Section The vertical section of the TDA9112 remains basically the same as in the TDA9111. It includes a sync detector, a V ramp generator with Free-running and Synchronized modes, an AGC system to maintain the amplitude of the V ramp constant, and S- and C-correction generators. -
Page 24: Frequency Range And Precision
Vertical Section AN1290 For the calculation of vertical frequency, we can neglect this discharge time and find: --------------- - = 100 Hz (typical) Cx V with I = 45 µA (typical). Nevertheless, there is a ±20% spread on this current, so that the same spread must be expected on the free-running frequency (not taking into account the capacitor spread). -
Page 25: Sync Detection
AN1290 Vertical Section 5.1.4 Sync Detection This part is best explained after the oscillator section since the sawtooth is used for polarity recognition as shown in Figure Figure 7: Sync Detection Positive or Negative sync 6µs 6µs Edge detector 13µs Sampling pulse Internal sync pulse Oscillator capacitor (not at scale) -
Page 26: Agc Loop Stability
Vertical Section AN1290 5.1.5 AGC Loop Stability Like all sampled feedback systems, the AGC loop has a particular instability mode, which require special attention: At a first sampling time, the vertical sawtooth peak voltage is compared to the pre-set 5V value. A corrective current proportional to the difference is added to the charge current of the oscillator capacitor with the appropriate sign to decrease the voltage difference at the next sampling time. - Page 27 AN1290 Vertical Section Let us consider C correction as an example (Figure 8 Figure 9). Instead of a ramp with a constant slope (obtained by charging C with constant current), we want to obtain a continuously increasing slope. For that purpose, we can add a current with constant positive slope to I - I’...
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Page 28: Output Stage And Vertical Shift
Vertical Section AN1290 In the TDA9112A only, the S and C corrections are very different (see description below). Figure 9: C Correction Circuit 3.5V I²C 5.1.7 Output Stage and Vertical Shift The vertical sawtooth undergoes certain modifications before reaching the vertical output on pin 23: To begin with, a high-impedance voltage follower transmits the signal without disturbing the oscillator. -
Page 29: Vertical Signal Management In The Tda9112A
AN1290 Vertical Section Figure 10: Vertical Waveform Waveform on pin 22 Waveform for following stages 5.1.8 Vertical Signal Management in the TDA9112A The block diagram of the vertical signal has been greatly modified in the TDA9112A in order to obtain the following improvements: “Tracking”... -
Page 30: On/Off Function
Vertical Section AN1290 In the next stage, the ramp and the S and C corrections are added, then a variable gain is applied together with EHT compensation, which has its own sensitivity setting. A second offset voltage and the Moire compensation are added, and a buffer transmits the signal to the output on pin 23. Figure 11: Variable Gain and EHT Compensation (Vramp) VMoire... -
Page 31: Moire
AN1290 Vertical Section 5.1.11 V Moire Depending on the definition mode, vertical amplitude etc., the vertical line step may be very close to the tube vertical pitch. This will create an array of interference fringes, just as for the Horizontal section, and a succession of more or less horizontal stripes, successively brighter and darker. - Page 32 Vertical Section AN1290 driven lower than 1V. In this area, decreasing the voltage by 1V will cause a 2.5% decrease of the vertical sawtooth amplitude, which normally should be more than enough for compensation. A resistive network should be introduced between ABL point and pin 18, with a twofold purpose: set the bias voltage in the active area between 1 and 8V, apply to pin 18 the ABL voltage variations with convenient attenuation.
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Page 33: Breathing Functions In The Tda9112A
AN1290 Vertical Section 5.1.14 Breathing Functions in the TDA9112A In the TDA9112A, the “gain” of each breathing compensation channel (H and V) may be adjusted through I²C parameters HEHTG and VEHTG (Registers 1B and 1C). The optimization of breathing compensation is made much easier, since the MCU is able to program the “gain” for each frequency or frequency range. -
Page 34: Ripple Rejection
Vertical Section AN1290 A first design constraint is centering: no current should flow in R when the voltage on pin 23 corresponds to the middle of sawtooth and when Vertical position setting is in middle position (i.e. V = Vmid = 3.5V on pin 23). This easily provides the condition: ⋅... -
Page 35: Vertical Vibration
AN1290 Vertical Section Take care to connect R directly to R , without any other intermediate connections (like supplies or filtering capacitors). Figure 14: Coupling to VBooster + Supply R40a R40b Scanning Processor 7, 21, 27 Yoke - Supply 5.2.3 Vertical Vibration In completed chassis, some designers have noticed a vertical vibration of the display, usually for precise (but not stable) settings of Horizontal position. -
Page 36: Leakage On Cs
Vertical Section AN1290 Since the discharge time has some spread, and since the parasitic frequency may be any of the horizontal frequencies in the range, there is no hope to choose such capacitor, to avoid coincidence between the parasitic pulses and the critical point. The only way is: to give minimal area to the receiving loop “capacitor/IC”, to maintain minimal area and maximum distance for the loop which emits parasitic voltages. -
Page 37: Chapter 6 Geometry And Focus Control Section
AN1290 Geometry and Focus Control Section Geometry and Focus Control Section Theory of Operation The input signal for this entire section (Figure 16) is the vertical sawtooth voltage, i.e. the difference between the V (buffered) voltage and the internal 3.5V voltage reference, multiplied by an amplitude factor and added to a shift factor. - Page 38 Geometry and Focus Control Section AN1290 The designer is responsible in deciding how much the total voltage will affect the B+ or the diode modulator voltage. Nevertheless, the various corrections will always remain in the same ratio to each other. For information, the design goal is that total HSize variation corresponding to the total variation of DC component be ±...
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Page 39: Tracking With Horizontal Size
AN1290 Geometry and Focus Control Section 6.1.2 Tracking with Horizontal Size Since pincushion distortion increases with the distance from the centre, it is a natural requirement that E/W correction increase with HSize. For that purpose, the amplitude of all corrections should decrease when the DC component (HSize) increases. -
Page 40: Dynamic Corrections
Geometry and Focus Control Section AN1290 All corrections (Pincushion, Corner (symmetric and asymmetric), Keystone, Parallelogram, Side pin balance) are also computed as functions of V - 3.5V. This means that for a given point on the screen, constant corrections will correspond when changing vertical amplitude and position. Consequently, the outlook of the display vertical border will remain unchanged when modifying these adjustments. -
Page 41: Vertical Dynamic Focus/Brightness
AN1290 Geometry and Focus Control Section During the discharge period, the level of the H Focus signal is maintained to the value corresponding to the beginning of the next scanning period. This allows a maximum amount of time for the damping of the transients which appear during flyback. At first glance, the HFocus parabola should be symmetric in comparison with the middle of the displays. -
Page 42: Application Hints
Geometry and Focus Control Section AN1290 Application Hints 6.2.1 E/W Output Stage An output inverting amplifier has been designed to ensure the interface with an E/W diode modulator (see Figure 17). Figure 17: E/W Amplifier Vs=12V 470k To sub-HSize DAC To diode modulator 220p... - Page 43 Þ Take care to provide a pull-down resistor to always keep the output transistor conductive on pin 24! (Not needed with the TDA9112A) Þ You will find on the ST Evaluation Board a similar application; except that the signal from pin 24 to the input passes through an attenuator (R constitutes a resistive divider with R ).
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Page 44: Chapter 7 Dc/Dc Converter Section
DC/DC Converter Section AN1290 DC/DC Converter Section Structure of the DC/DC Converter and B+ Loop 7.1.1 Structure of the Converter Section The DC/DC converter section has a basic structure very similar to the well-known UC 3842 family, i.e. current-mode PWM converters. (You can refer to the corresponding datasheet). It includes: An oscillator to switch the power MOS transistor ON. -
Page 45: B+ Output Polarity
AN1290 DC/DC Converter Section The step-down, continuous conduction converter does not have the advantages of a step-up configuration, but it is easily adapted to a large frequency range, since the ratio of the regulated to unregulated voltage is just equal to the duty factor. Nevertheless, the slow frequency response of the step-down voltage mode makes it ill-adapted to direct modulation by the E/W signal. -
Page 46: Selecting The Trigger Timing
DC/DC Converter Section AN1290 7.1.5 Selecting the Trigger Timing In Internal sawtooth configuration, since the HFocus sawtooth is used for comparison purpose, conduction of the power MOS transistor is triggered at the same time as the sawtooth, i.e. inside the flyback pulse (See Section 6.1.7: Horizontal Dynamic Focus/Brightness for more details). -
Page 47: Structure Of The Regulation Loop (Step-Down, Current Mode)
AN1290 DC/DC Converter Section Figure 18: Regulation Loop in Step-up H Scanning Transistor Zfb: HOut TMOS Vref 10nF Reset 7.1.7 Structure of the Regulation Loop (Step-down, Current Mode) Operating in a similar way as in a step-up configuration, this architecture maximizes the time devoted to energy storage ( Figure 19 ). -
Page 48: Structure Of The Regulation Loop (Step-Down, Voltage Mode)
DC/DC Converter Section AN1290 The capacitor value should be low enough not to switch the MOS transistor ON during a power switch-ON. A Zener diode protects the gate at this time. On the other side, the surge current will be sunk by one of the buffer transistors. -
Page 49: Structure Of The Dc/Dc Converter (Open Loop)
AN1290 DC/DC Converter Section Figure 20: Regulation Loop in Step-down, Voltage Mode (MOS type N) (TDA9112 only) H scanning transistor TMOS Zfb: Reset Vref 10nF H Focus Capacitor 7.1.9 Structure of the DC/DC Converter (Open Loop) A scanning stage needs a B+ roughly proportional to the frequency (Figure 21 ) . -
Page 50: Application Hints
DC/DC Converter Section AN1290 Figure 21: DC/DC converter in Step-down, Open loop, MOS type p Zfb: Pull-up TMOS Reset Vref HOut The monostable circuit can be implemented with a capacitor charged from a constant supply through a resistor. If the unregulated Vdc is used to feed the charge resistor, any ripple of Vdc, which would normally entail an equivalent ripple on B+, will be automatically compensated by a proportional variation of the conduction time (feed forward compensation). -
Page 51: Frame-Top Distortion Related To Keystone Correction
AN1290 DC/DC Converter Section Considering that the BOut control pulse will have constant duration (Open loop), or nearly constant (Current mode, Step-up or Step-down), you can choose to trigger conduction: at low frequency, with HOut down, at high frequency, after flyback, and obtain that the switching always takes place inside the first half of H positive ramp, which is the least critical period regarding parasitic voltage. -
Page 52: Chapter 8 Miscellaneous
Miscellaneous AN1290 Miscellaneous Summary of Safety Functions Vertical, horizontal and B+ output stages will be inhibited (and for Vertical, voltage will be maintained near mid-range, i.e. 3.5 / 8 of the reference voltage) when the supply voltage is too low; following a proper I²C instruction (Sad17h/d1 and Sad17h/d2). -
Page 53: Early V Blanking And Lock/Unlock
AN1290 Miscellaneous BMute function (1Fd6): B+ can be enabled/disabled alone, it will come back with its own soft- start. BSafe function: if it is selected through I²C (Sad1Fh/d5), BOut will switch OFF as soon as the H oscillator Unlock is detected; when it locks again, B+ will come back with its own soft-start. HLock speed: If bit 1Fd2 is set, an Unlocked state will be detected twice as fast as with the rest of the family. - Page 54 Miscellaneous AN1290 Figure 24: H Lock and V Early Blanking H amp feedback TDA9112 0.1uF Blank 220k 100k The resistor divider which controls the base should take into account that a 1V blanking signal may be present even when Locked. An AC-coupled transistor will provide an early negative-going blanking pulse (to be ORed with a blanking pulse from V flyback).
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Page 55: Chapter 9 I²C Control Section
AN1290 I²C Control Section I²C Control Section I²C Bus Reminder Since I²C bus documentation is widespread today, a short reminder will be enough. I²C bus consists of two wires, SCL (clock) and SDA (data), plus ground. The logic is positive. Both SCL and SDA have a pull-up resistor to 5V, and all connected ports are open-collector or open- drain, i.e. -
Page 56: Sending Data
I²C Control Section AN1290 In order to make the transmission of long strings of data easier, the TDA9112 features an auto- increment function. This means that the sub address will increase by one after receiving each byte of data. This is especially useful when initializing all registers at start-up. The corresponding sequence on the bus would be as follows: (Start)(8C)(ackn)(00)(ackn)(data00)(ackn)(data01)(ackn)...(data0F)(ackn)(Stop) Some peculiarities of the various registers will be summarized later. - Page 57 AN1290 I²C Control Section Table 3: Detailed Register Description (including TDA9112A) (Sheet 2 of 3) Reg. Add. Comments 04d7 1: Hfocus amplitude will track Hamplitude / 0: no tracking. 05d7 1: The HFocus signal will start at middle of flyback; 0: - at beginning of flyback.
- Page 58 I²C Control Section AN1290 Table 3: Detailed Register Description (including TDA9112A) (Sheet 3 of 3) Reg. Add. Comments 17d3 Active only if 07d7 is set to 1, except the TDA9112A. 1: sets the triggering of B+ to HDrive UP/0: sets to HDrive DOWN. TDA9112A only: when 07d7 is 1, same as previous/when 07d7 is 0: if 17d3 is 0, same as previous (triggers after flyback) if 17d3 is 1, triggers with top of sawtooth, at half H frequency.
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Page 59: Management Of Status Register And Sync Priority
AN1290 I²C Control Section Management of Status Register and Sync Priority It is possible to read from the STATUS register (Bold = default value): in d0, whether pulses are present on pin 2 Vsync (1 = detected once/0 = not detected yet) in d1, whether pulses are present on pin 1 H/HVsync (1 = detected once/0 = not detected yet) in d2, whether a Vsync can be extracted from H/HV signal (1 = detected once/0 = not detected yet) -
Page 60: Chapter 10 I²C Bus Control Register Map
I²C Bus Control Register Map AN1290 I²C Bus Control Register Map The device slave address is 8C in write mode and 8D in read mode. The control register map is given in Table 5. The values in bold denote the default value at Power-On-Reset. I²C-bus data in the adjustment register is buffered and internally applied with discharge of the vertical oscillator (). - Page 61 AN1290 I²C Bus Control Register Map Table 5: I²C-bus Control Registers HSIZE Horizontal Size Reserved PCAC Pin Cushion Asymmetry Correction Reserved PARAL Parallelogram Correction Reserved TCAC Top Corner Asymmetry Correction Reserved BCAC Bottom Corner Asymmetry Correction VDyCorPol VDC-AMP Vertical Dynamic Correction 0:”∪“...
- Page 62 STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
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