Crystal Oscillator; Esp32 Power Traces In A Two-Layer Pcb Design - Espressif Systems ESP32 Series Hardware Design Manuallines

2. Schematic Checklist and PCB Layout Design
The central thermal pad at the bottom of the chip should be connected to the ground plane through at least
nine ground vias.
• Two-layer PCB design
In a two-layer PCB design, the 3.3 V power traces are routed as shown labelled with VDD33 in Figure 15.
In contrast to the design practices for a four-layer PCB design, the power traces in a two-layer PCB design
should be routed on the top layer, thus requiring a reduced size of a thermal pad in the center of the chip.
Route the power traces between the thermal pad and its surrounding signal pins. Employ vias only when the
power traces have to reach the bottom layer. The purpose of this practice is to maintain a complete ground
plane while reducing the surrounding area of the power traces.
Other good practices for routing power traces in four-layer PCB designs still apply to two-layer PCB designs.

2.2.1.4 Crystal Oscillator

For design of the crystal oscillator section, please refer to Figure 16. In addition, the following should be noted:
• The crystal oscillator should be placed far from the clock pin. The recommended gap is 2.7 mm. It is good
practice to add high-density ground via stitching around the clock trace for containing the high-frequency
clock signal.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.
• The external regulating capacitor should be placed on the near left or right side of the crystal oscillator and
at the end of the clock trace.
• Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The larger the copper area on the top layer is, the better.
• As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example, power-switching converter components or unshielded inductors.
Espressif Systems
Figure 15: ESP32 Power Traces in a Two-layer PCB Design
12 ESP32 Hardware Design Guidelines V2.7