NXP Semiconductors MPC5777C Reference Manual
  1. Manuals
  2. Brands
  3. NXP Semiconductors Manuals
  4. Motherboard
  5. MPC5777C
  6. Reference manual

NXP Semiconductors MPC5777C Reference Manual

Hide thumbs Also See for MPC5777C:
Table of Contents

Advertisement

Quick Links

See also: Manual
MPC5777C Reference Manual
Addendum
Supports maskset 2N45H
Document Number: MPC5777CRMAD
Rev. 1, 12/2015

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the MPC5777C and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for NXP Semiconductors MPC5777C

Summary of Contents for NXP Semiconductors MPC5777C

  • Page 1 MPC5777C Reference Manual Addendum Supports maskset 2N45H Document Number: MPC5777CRMAD Rev. 1, 12/2015...
  • Page 2 MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 3: Table Of Contents

    Modular CAN (M_CAN) 3.1 Chip-specific M_CAN information..........................19 3.1.1 M_CAN Message RAM allocation........................19 3.1.2 Introduction................................19 3.1.3 Functional Description............................20 3.1.4 External Signals..............................22 3.2 Overview...................................23 3.2.1 Features................................23 3.2.2 Block Diagram..............................24 3.2.3 Dual Clock Sources..............................26 MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 4 3.3.23 New Data 1 Register (M_CAN_NDAT1)......................60 3.3.24 New Data 2 Register (M_CAN_NDAT2)......................61 3.3.25 Rx FIFO 0 Configuration Register (M_CAN_RXF0C)..................61 3.3.26 Rx FIFO 0 Status Register (M_CAN_RXF0S)....................62 3.3.27 Rx FIFO 0 Acknowledge Register (M_CAN_RXF0A)..................63 MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 5 Tx Buffer Element...............................81 3.4.3 Tx Event FIFO Element............................83 3.4.4 Standard Message ID Filter Element........................84 3.4.5 Extended Message ID Filter Element........................85 3.5 Functional Description..............................87 3.5.1 Operating Modes..............................87 3.5.2 Timestamp Generation............................96 3.5.3 Timeout Counter..............................97 MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 6 Section number Title Page 3.5.4 Rx Handling.................................97 3.5.5 Tx Handling.................................108 3.5.6 FIFO Acknowledge Handling..........................114 3.5.7 Interface to DMA Controller..........................114 MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 7: Overview

    1.1 Overview For users of maskset 2N45H, this addendum supplements—and must be used in conjunction with—the latest version of the MPC5777C Reference Manual. The primary objective of this document is to define the major differences in functionality of maskset 2N45H from maskset 3N45H for software and hardware developers.

  • Page 8: Audience

    1.3 Audience This addendum is intended for system software and hardware developers and applications programmers who want to develop products with maskset 2N45H of the MPC5777C. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the Power Architecture®...

  • Page 9: Typographic Notation

    • Consider undefined locations in memory to be reserved. Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 10: References

    References 1.6 References This addendum must be used in conjunction with the latest version of the MPC5777C Reference Manual (document number MPC5777CRM). In addition, the following documents provide information about the operation of the MPC5777C: • MPC5777C Data Sheet (document number MPC5777C) •...

  • Page 11: Platform Configuration Module (Pcm)

    (hex) (in bits) page FEC Burst Optimization Master Control Register 0000_0000h 2.1.1/12 (PCM_FBOMCR) Bus Bridge Configuration Register 1 (PCM_IAHB_BE1) 0707_0707h 2.1.2/13 Bus Bridge Configuration Register 2 (PCM_IAHB_BE2) 0707_0707h 2.1.3/16 MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 12: Fec Burst Optimization Master Control Register (Pcm_Fbomcr)

    RBEN Read bursting from all XBAR slave ports is disabled. Read bursting is enabled from any XBAR slave port whose FXSBEn bit is 1. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 13: Bus Bridge Configuration Register 1 (Pcm_Iahb_Be1)

    Reset Reset PCM_IAHB_BE1 field descriptions Field Description 0–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 14 Pending reads are disabled Pending reads are enabled. Burst Read Enable Core0 Data BRE_CORE0_D This bit controls the bus gasket’s handling of burst read transactions. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 15 Burst writes are optimized for best system performance. Note this setting treats writes as “imprecise” such that an error response on any beat of the burst is reported on the last beat. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 16: Bus Bridge Configuration Register 2 (Pcm_Iahb_Be2)

    This read-only field is reserved and always has the value 0. Pending Read Enable Master Port 6 Concentrator PRE_M6 This bit controls the bus gasket’s handling of pending read transactions. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 17 Burst reads are converted into a series of single transactions on the slave side of the gasket. Burst reads are optimized for best system performance. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 18 Burst writes are optimized for best system performance. Note this setting treats writes as “imprecise” such that an error response on any beat of the burst is reported on the last beat. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 19: Chapter 3 Modular Can (M_Can)

    9.5 KB. 3.1.2 Introduction The M_CAN subsystem includes: • Two M_CAN modules • A Message RAM controller The M_CAN subsystem block diagram is shown in the following figure. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 20: Functional Description

    The Message RAM Arbiter is a dynamic round robin arbiter that selects which request is sent to the external Message RAM. These requests are made by the CPU, M_CAN_0, or M_CAN_1. This arbiter ensures: MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 21 The read or write accesses to the external Message RAM use two clock cycles. In the first clock cycle, the address is available, and in the second, the data is available. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 22: External Signals

    CPU can do 8/16/32-bit read accesses to the external Message RAM. 3.1.3.3 Transfer Error The M_CAN subsystem does not report any transfer error. 3.1.4 External Signals The M_CAN subsystem external signals are shown in the following table. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 23: Overview

    The following are the features of M_CAN. • Conforms with CAN protocol version 2.0 part A, B and ISO 11898-1 • CAN FD with up to 64 data bytes supported • CAN Error Logging MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 24 • Maskable module interrupts • 8/16/32-bit Generic Slave Interface for connection customer-specific Host CPUs • Two clock domains (CAN clock and Host clock) • Power-down support • Debug on CAN support MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 25: Block Diagram

    Tx Buffers, as Tx FIFO, part of a Tx Queue, or as a combination of them. A Tx Event FIFO stores Tx timestamps together with the corresponding Message ID. Transmit cancellation is also supported. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 26: Dual Clock Sources

    0 or to M_CAN interrupt 1. By default all interrupts are routed to interrupt line M_CAN interrupt 0. By programming ILE[EINT0] and ILE[EINT1], the interrupt lines can be enabled or disabled separately. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 27: Memory Map And Register Description

    3.3.11/40 Error Counter Register (M_CAN_ECR) 0000_0000h 3.3.12/41 Protocol Status Register (M_CAN_PSR) 0000_0707h 3.3.13/42 Interrupt Register (M_CAN_IR) 0000_0000h 3.3.14/45 Interrupt Enable Register (M_CAN_IE) 0000_0000h 3.3.15/49 Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 28: Core Release Register (M_Can_Crel)

    Tx Event FIFO Acknowledge Register (M_CAN_TXEFA) 0000_0000h 3.3.45/78 3.3.1 Core Release Register (M_CAN_CREL) The following table shows example field values for this register and explains how they encode a particular M_CAN core release. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 29: Endian Register (M_Can_Endn)

    One digit, BCD-coded. 16–23 Time Stamp Month Two digits, BCD-coded. 24–31 Time Stamp Day Two digits, BCD-coded. 3.3.2 Endian Register (M_CAN_ENDN) Address: 0h base + 4h offset = 4h Reset MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 30: Fast Bit Timing And Prescaler Register (M_Can_Fbtp)

    FSJW Reset M_CAN_FBTP field descriptions Field Description 0–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 31 (0x0–0x3)— Valid values are 0 to 3. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. NOTE: This field has Protected Write status. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 32: Test Register (M_Can_Test)

    M_CAN Tx to M_CAN Rx and FBTP[TDCO]. Valid value are 0 to 63 M_CAN clock periods. Receive Pin Monitors the actual value of M_CAN Rx Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 33: Ram Watchdog Register (M_Can_Rwd)

    Address: 0h base + 14h offset = 14h Reset M_CAN_RWD field descriptions Field Description 0–15 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 34: Cc Control Register (M_Can_Cccr)

    This node transmits no frames with bit rate switching This node transmits all frames (excluding remote frames) with bit rate switching CAN FD Operation Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 35 Bit MON can only be set by the CPU when both CCE and INIT are set to 1. The bit can be reset by the CPU at any time. Bus Monitoring Mode is disabled Bus Monitoring Mode is enabled Clock Stop Request Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 36: Bit Timing And Prescaler Register (M_Can_Btp)

    (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 37 (0x0-0xF)— Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. NOTE: This field has Protected Write status. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 38: Timestamp Counter Configuration Register (M_Can_Tscc)

    Timestamp counter value always 0x0000 Timestamp counter value incremented according to TCP Reserved Same as 00 3.3.9 Timestamp Counter Value Register (M_CAN_TSCV) Address: 0h base + 24h offset = 24h Reset MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 39: Timeout Counter Configuration Register (M_Can_Tocc)

    NOTE: This field has Protected Write status. 16–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 29–30 Timeout Select Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 40: Timeout Counter Value Register (M_Can_Tocv)

    The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC[TCP]. When decremented to zero, interrupt flag IR[TOO] is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC[TOS]. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 41: Error Counter Register (M_Can_Ecr)

    Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127. 24–31 Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 42: Protocol Status Register (M_Can_Psr)

    FLEC Reset M_CAN_PSR field descriptions Field Description 0–17 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 43 Synchronizing - node is synchronizing on CAN communication Idle - node is neither receiver nor transmitter Receiver - node is operating as receiver Transmitter - node is operating as transmitter Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 44 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Protocol Status Register MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 45: Interrupt Register (M_Can_Ir)

    A fixed format part of a received frame has the wrong format Acknowledge Error ACKE No Acknowledge Error detected A transmitted message was not acknowledged by another node Bit Error Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 46 The flag is set whenever a received message has been stored into a dedicated Rx Buffer. No Rx Buffer updated At least one received message stored into a Rx Buffer Timeout Occurred No timeout Timeout reached Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 47 Tx FIFO Empty Tx FIFO non-empty Tx FIFO empty Transmission Cancellation Finished No transmission cancellation finished Transmission cancellation finished Transmission Completed No transmission completed Transmission completed Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 48 Rx FIFO 0 fill level below watermark Rx FIFO 0 fill level reached watermark Rx FIFO 0 New Message RF0N No new message written to Rx FIFO 0 New message written to Rx FIFO 0 MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 49: Interrupt Enable Register (M_Can_Ie)

    Bit Error Interrupt Enable Interrupt disabled Interrupt enabled CRC Error Interrupt Enable CRCEE Interrupt disabled Interrupt enabled Watchdog Interrupt Enable WDIE Interrupt disabled Interrupt enabled Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 50 Interrupt enabled Tx Event FIFO Element Lost Interrupt Enable TEFLE Interrupt disabled Interrupt enabled Tx Event FIFO Full Interrupt Enable TEFFE Interrupt disabled Interrupt enabled Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 51 Interrupt enabled Rx FIFO 0 Message Lost Interrupt Enable RF0LE Interrupt disabled Interrupt enabled Rx FIFO 0 Full Interrupt Enable RF0FE Interrupt disabled Interrupt enabled Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 52: Interrupt Line Select Register (M_Can_Ils)

    Format Error Interrupt Line FOEL Interrupt assigned to M_CAN interrupt line 0 Interrupt assigned to M_CAN interrupt line 1 Acknowledge Error Interrupt Line ACKEL Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 53 Timeout Occurred Interrupt Line TOOL Interrupt assigned to M_CAN interrupt line 0 Interrupt assigned to M_CAN interrupt line 1 Message RAM Access Failure Interrupt Line MRAFL Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 54 Rx FIFO 1 Full Interrupt Line RF1FL Interrupt assigned to M_CAN interrupt line 0 Interrupt assigned to M_CAN interrupt line 1 Rx FIFO 1 Watermark Reached Interrupt Line RF1WL Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 55: Interrupt Line Enable Register (M_Can_Ile)

    Each of the two interrupt lines to the CPU can be enabled / disabled separately by programming bits EINT0 and EINT1. Address: 0h base + 5Ch offset = 5Ch Reset Reset MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 56: Global Filter Configuration Register (M_Can_Gfc)

    Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. NOTE: This field has Protected Write status. Accept in Rx FIFO 0 Accept in Rx FIFO 1 Reject Reject Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 57: Standard Id Filter Configuration Register (M_Can_Sidfc)

    M_CAN_SIDFC field descriptions Field Description 0–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 8–15 List Size Standard Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 58: Extended Id Filter Configuration Register (M_Can_Xidfc)

    Start address of extended Message ID filter list (32-bit word address, see Message RAM). NOTE: This field has Protected Write status. 30–31 This field is reserved. Reserved This read-only field is reserved and always has the value 0. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 59: Extended Id And Mask Register (M_Can_Xidam)

    BIDX Reset M_CAN_HPMS field descriptions Field Description 0–15 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 60: New Data 1 Register (M_Can_Ndat1)

    1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. Rx Buffer not updated Rx Buffer updated from new message MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 61: New Data 2 Register (M_Can_Ndat2)

    FIFO 0 Operation Mode F0OM FIFO 0 can be operated in blocking or in overwrite mode (see FIFOs). NOTE: This field has Protected Write status. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 62: Rx Fifo 0 Status Register (M_Can_Rxf0S)

    This read-only field is reserved and always has the value 0. 3.3.26 Rx FIFO 0 Status Register (M_CAN_RXF0S) Address: 0h base + A4h offset = A4h RF0L F0PI Reset F0GI F0FL Reset MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 63: Rx Fifo 0 Acknowledge Register (M_Can_Rxf0A)

    Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 Fill Level RXF0S[F0FL]. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 64: Rx Buffer Configuration Register (M_Can_Rxbc)

    FIFO 1 Operation Mode F1OM FIFO 1 can be operated in blocking or in overwrite mode (see FIFOs). NOTE: This field has Protected Write status. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 65: Rx Fifo 1 Status Register (M_Can_Rxf1S)

    Address: 0h base + B4h offset = B4h RF1L F1PI Reset Reserved F1GI F1FL Reset M_CAN_RXF1S field descriptions Field Description 0–1 Debug Message Status Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 66: Rx Fifo 1 Acknowledge Register (M_Can_Rxf1A)

    F1AI Reset M_CAN_RXF1A field descriptions Field Description 0–25 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 67: Rx Buffer / Fifo Element Size Configuration Register (M_Can_Rxesc)

    NOTE: This field has Protected Write status. 8 byte data field 12 byte data field 16 byte data field 20 byte data field 24 byte data field Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 68 8 byte data field 12 byte data field 16 byte data field 20 byte data field 24 byte data field 32 byte data field 48 byte data field 64 byte data field MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 69: Tx Buffer Configuration Register (M_Can_Txbc)

    Values greater than 32 are interpreted as 32 8–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 70: Tx Fifo/Queue Status Register (M_Can_Txfqs)

    Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. Address: 0h base + C4h offset = C4h TFQF TFQPI Reset TFGI TFFL Reset MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 71: Tx Buffer Element Size Configuration (M_Can_Txesc)

    Tx Buffer data field size TXESC[TBDS], the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding bytes). NOTE: This field has Protected Write status. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 72: Tx Buffer Request Pending Register (M_Can_Txbrp)

    • when the transmission has not yet been started at the point of cancellation • when the transmission has been aborted due to lost arbitration • when an error occurred during frame transmission MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 73: Tx Buffer Add Request Register (M_Can_Txbar)

    Tx scan process has completed. No transmission request added Transmission requested added 3.3.38 Tx Buffer Cancellation Request Register (M_CAN_TXBCR) Address: 0h base + D4h offset = D4h Reset MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 74: Tx Buffer Transmission Occurred Register (M_Can_Txbto)

    1 to the corresponding bit of register TXBAR. No transmission occurred Transmission occurred 3.3.40 Tx Buffer Cancellation Finished Register (M_CAN_TXBCF) Address: 0h base + DCh offset = DCh Reset M_CAN_TXBCF field descriptions Field Description 0–31 Cancellation Finished MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 75: Tx Buffer Transmission Interrupt Enable Register (M_Can_Txbtie)

    M_CAN_TXBCIE field descriptions Field Description 0–31 Cancellation Finished Interrupt Enable CFIE Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. Cancellation finished interrupt disabled Cancellation finished interrupt enabled MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 76: Tx Event Fifo Configuration Register (M_Can_Txefc)

    Start address of Tx Event FIFO in Message RAM (32-bit word address, Message RAM). NOTE: This field has Protected Write status. 30–31 This field is reserved. Reserved This read-only field is reserved and always has the value 0. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 77: Tx Event Fifo Status Register (M_Can_Txefs)

    Reserved This read-only field is reserved and always has the value 0. 26–31 Event FIFO Fill Level EFFL Number of elements stored in Tx Event FIFO, range 0 to 32. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 78: Tx Event Fifo Acknowledge Register (M_Can_Txefa)

    M_CAN information. It is not necessary to configure each of the sections listed in the following figure, and there is no restriction with respect to the sequence of the sections. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 79: Rx Buffer And Fifo Element

    CAN FD messages with up to 64 bytes data field via register RXESC. Table 3-48. Rx Buffer and FIFO Element 24 23 16 15 ID[28:0] Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 80 1 CAN FD frame format (new DLC-coding and CRC) R1 Bit 20 BRS: Bit Rate Switch 0 Frame received without bit rate switching 1 Frame received with bit rate switching Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 81: Tx Buffer Element

    Tx Buffer configuration TXBC.TFQS and TXBC.NDTB. The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via register TXESC. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 82 DB7[7:0]: Data Byte 7 T3 Bits 23:16 DB6[7:0]: Data Byte 6 T3 Bits 15:8 DB5[7:0]: Data Byte 5 T3 Bits 7:0 DB4[7:0]: Data Byte 4 Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 83: Tx Event Fifo Element

    1 Remote frame transmitted E0 Bits 28:0 ID[28:0]: Identifier Standard or extended identifier depending on bit XTD. A standard identifier is stored into ID[28:18]. Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 84: Standard Message Id Filter Element

    Standard Message ID Filter element, its address is the Filter List Standard Start Address SIDFC[FLSSA] plus the index of the filter element (0…127). Table 3-54. Standard Message ID Filter Element 24 23 16 15 SFEC[2:0 SFID1[10:0] SFID2[10:0] MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 85: Extended Message Id Filter Element

    Host clock period in case the filter matches. SFID2[5:0]: Defines the offset to the Rx Buffer Start Address RXBC.RBSA for storage of a matching message. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 86 01 Dual ID filter for EFID1 or EFID2 10 Classic filter: EFID1 = filter, EFID2 = mask 11 Range filter from EFID1 to EFID2 (EFID2 >= EFID1), XIDAM mask not applied Table continues on the next page... MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 87: Functional Description

    (= Bus_Idle) before it can take part in bus activities and start the message transfer. Access to the M_CAN configuration registers is only enabled when both bits CCCR[INIT] and CCCR[CCE] are set (protected write). MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 88 CAN bus and is ready for communication. After passing the acceptance filtering, received messages including Message ID and DLC are stored into a dedicated Rx Buffer or into Rx FIFO 0 or Rx FIFO 1. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 89 When CCCR[CME] is not 00, received CAN FD frames are interpreted according to the CAN FD Protocol Specification. The reserved bit in CAN frames with 11-bit identifiers and the first reserved bit in CAN frames with 29-bit identifiers will be decoded as EDL MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 90 (Error Status Indicator) is determined by the transmitter’s error state at the start of the transmission. If the transmitter is error passive, ESI is transmitted recessive, else it is transmitted dominant. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 91 FBTP[TDCO] to the measured transceiver delay. The transceiver delay compensation value TEST[TDCV] is the sum of the measured transceiver delay and the transceiver delay compensation offset. The transceiver delay MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 92 CCCR[ASM]. The bit can only be set by the Host when both CCCR[CCE] and CCCR[INIT] are set to 1. The bit can be reset by the Host at any time. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 93 The following figure shows the connection of signals M_CAN Tx and Rx to the M_CAN in Bus Monitoring Mode. MCAN MCAN transmit output receive input MCAN Figure 3-50. Pin Control in Bus Monitoring Mode MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 94 When all pending transmission requests have completed, the M_CAN waits until bus idle state is detected. Then the M_CAN sets then CCCR[INIT] to one to prevent any further CAN transfers. Now the M_CAN acknowledges that it is ready for power down by MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 95 This mode is provided for hardware self-test. To be independent from external stimulation, the M_CAN ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. In this mode the M_CAN MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 96 M_CAN_Tx is held recessive. The following figure shows the connection of M_CAN_Tx and M_CAN_Rx to the M_CAN in case of Internal Loopback Mode. MCAN MCAN transmit output receive input MCAN Figure 3-52. Pin Control in Internal Loopback Mode MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 97: Timestamp Generation

    / re-synchronization mechanism of the CAN Core. If the baud rate switch feature in CAN FD is used, the timeout counter is clocked differently in arbitration and data field. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 98: Rx Handling

    • Store received frame in FIFO 0 or FIFO 1 • Store received frame in Rx Buffer • Store received frame in Rx Buffer and generate pulse at filter event pin MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 99 • EFT = "00": The Message ID of received frames is ANDed with the Extended ID AND Mask (XIDAM) before the range filter is applied • EFT = "11": The Extended ID AND Mask (XIDAM) is not used for range filtering MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 100 Controlled by the Global Filter Configuration GFC and the Standard ID Filter Configuration SIDFC Message ID, Remote Transmission Request bit (RTR), and the Identifier Extension bit (IDE) of received frames are compared against the list of configured filter elements. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 101 3.5.4.1.5 Extended Message ID Filtering The figure below shows the flow for extended Message ID (29-bit Identifier) filtering. The Extended Message ID Filter element is described in Extended Message ID Filter Element. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 102 GFC[ANFE ] = ‘0’ target FIFO full(blocking) or Rx Buffer ND =‘1’ append to target FIFO or store to Rx Buffer Figure 3-54. Extended Message ID Filter Path MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 103 Figure 3-55. Rx FIFO Status When reading from an Rx FIFO, Rx FIFO Get Index RXFnS[FnGI] x FIFO Element Size has to be added to the corresponding Rx FIFO start address RXFnC[FnSA]. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc. ...
  • Page 104 CPU accesses the Rx FIFO. The following figure shows an offset of two with respect to the get index when reading the Rx FIFO. In this case the two messages stored in element 1 and 2 are lost. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 105 Table 3-60. Example Filter Configuration for Rx buffers Filter Element SFID1[10:0] EFID1[28:0] SFID2[10:9] EFID2[10:9] SFID2[5:0] EFID2[5:0] ID message 1 00 0000 ID message 2 00 0001 ID message 3 00 0010 MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 106 Now the M_CAN is prepared to receive the next set of debug messages. NOTE To use full ‘Debug on CAN Support’ feature on a M_CAN instance, a DMA channel is required. Refer to device DMA MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 107 The DMA request is activated only when all three debug messages A, B, C have been received in correct order. The status of the debug message handling state machine is signaled via RXF1S[DMS]. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 108: Tx Handling

    Get Indices, and the Tx Event FIFO. Up to 32 Tx Buffers can be set up for message transmission. The Tx Buffer element is described in Tx Buffer Element. Note AUTOSAR requires at least three Tx Queue Buffers and support of transmit cancellation. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 109 Host CPU. Each Dedicated Tx Buffer is configured with a specific Message ID. In case that multiple Tx Buffers are configured with the same Message ID, the Tx Buffer with the lowest buffer number is transmitted first. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 110 When a single message is added to the Tx FIFO, the transmission is requested by writing a 1 to the TXBAR bit related to the Tx Buffer referenced by the Tx FIFO's Put Index. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 111 (free) Tx Queue Buffer is calculated by adding Tx FIFO/Queue Put Index TXFQS[TFQPI] (0…31) x Element Size to the Tx Buffer Start Address TXBC[TBSA]. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 112 Dedicated Tx Buffers Tx Queue Buffer Index ID3 ID15 ID8 ID24 Tx Sequence Put Index Figure 3-59. Example of mixed Configuration Dedicated Tx Buffers / Tx Queue Tx prioritization: MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 113 Message Marker from the transmitted Tx Buffer is copied into the Tx Event FIFO element. The Tx Event FIFO can be configured to a maximum of 32 elements. The Tx Event FIFO element is described in Tx Event FIFO Element. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 114: Fifo Acknowledge Handling

    FIFO elements would be lost. Note The application has to ensure that a valid value is written to the FIFO Acknowledge Index. The M_CAN does not check for erroneous values. MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.

  • Page 115: Interface To Dma Controller

    A, B, C are unlocked and may be overwritten by received debug messages. M_CAN host clk M_CAN DMA request M_CAN DMA acknowledge Figure 3-60. Timing of DMA Interface Signals MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 116 Functional Description MPC5777C Reference Manual Addendum, Rev. 1, 12/2015 Freescale Semiconductor, Inc.
  • Page 117 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express Home Page: or implied copyright licenses granted hereunder to design or fabricate freescale.com any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to Web Support: any products herein.

Table of Contents

Save PDF