Power integrations InnoSwitch3 Application Note page 8

Application Note
• Higher VOR reduces the voltage stress on the output diodes and SR
FETs, which in some cases may allow a lower voltage rating for
higher efficiency.
• Higher VOR increases leakage inductance which reduces power
supply efficiency.
• Higher VOR increases peak and RMS current on the secondary-side
which may increase secondary side copper, diode and SR FET losses
thereby reducing efficiency.
It should be noted that there are exceptions to this guidance
especially for very high output currents where the VOR should be
reduced to obtain highest efficiency. Higher output voltages
(above 15 V) should employ a higher VOR to maintain acceptable
peak inverse voltage (PIV) across the output SR FET.
Optimal selection of the VOR value depends on the specific
application and is based on a compromise between the factors
mentioned above.
Output Suggested VOR
Voltage
5 V
9 V
12 V - 20 V
Table 6. Suggested Values for VOR.
Primary
Secondary
Primary
Secondary
Figure 6. Discontinuous Mode Current Waveform, K
8
Rev. A 10/18
Suggested
Value Range
55 V 45 V - 60 V
85 V 80 V - 90 V
110 V 100 V - 120 V
K ≡ K
P
T = 1/f
D × T
t
(a) Discontinuous, K > 1
P
T = 1/f
D × T
(b) Borderline Discontinuous/Continuous, K
≥1.
P
Mode of Operation, K
K is a measure of how discontinuous or continuous the mode of
P
switching is. K > 1 is said to be in discontinuous operation (DCM),
P
while K < 1 denotes continuous operation (CCM).
P
Ripple to Peak Current Ratio, K
Below 1 (indicating continuous conduction mode), K
ripple to peak primary current (Figure 5).
I
R
Primary
(a) Continuous, K
Primary I
R
(b) Borderline Continuous/Discontinuous, K
Figure 5. Continuous Mode Current Waveform, K
(1-D) × T
=
DP
t
S
(1-D) × T
S
(1-D) × T = t
= 1
P
P
P
is the ratio of
P
I
R
K ≡ K =
P RP
I
P
I
P
< 1
P
I
P
= 1
P
≤1.
P
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