Power integrations InnoSwitch3 Application Note page 20

Application Note
Part PIV I
DRAIN
(V) (A)
AO4260 60 18.0
AO4264 60 12.0
AON6244 60 85.0
AON6266 60 30.0
AON7246 60 34.5
AO4294 100 11.5
AON7292 100 23.0
AO4292 100 8
AO4294 100 11.5
AO4296 100 13.5
AOD294A 100 55
AOD296A 100 70
AOD2910 100 31
AOD2916 100 25
AOD2544 150 23.0
AON7254 150 17.0
Table 10. List of MOSFETs Suitable for Synchronous Rectification.
At the instance of voltage reversal at the winding due to primary
MOSFET turn-ON, the interaction between the leakage reactance of
the output windings and the SR FET capacitance (C
ringing on the voltage waveform. This ringing can be suppressed
using a RC snubber connected across the SR FET. A snubber resistor
of 10 Ω to 47 Ω may be used (higher resistance values will lead to a
noticeable drop in efficiency). A capacitance value of 1 nF to 2.2 nF
is adequate for most designs.
When the primary MOSFET turns on, a fast rising voltage is
transfered to the secondary via the transformer across the drain-
source of the SR FET. This high dv/dt combined with high ratio of C
to CISS MOSFET capacitances will induce gate-source voltage on the
SR FET. If the induced gate voltage exceeds the minimum gate
threshold voltage, V , then it will turn-on the SR FET causing
GS(TH)
cross-conduction possibly leading to catastrophic failure. The
recommended C (CRSS), is less than 35 pF, and the ratio of CRSS to
GD
CISS to be less than 2%.
20
Rev. A 10/18
V V CISS CRSS
GS(TH) GS(TH)
Max Min
(V) (V) (pF) (pF)
2.4 1.3 4940 32.0
2.5 1.4 2007 12.5
2.5 1.5 3838 14.5
2.5 1.5 1340 10.0
2.5 1.5 1340 10.0
2.4 1.4 2420 11.0
2.6 1.6 1170
2.7 1.6 1190
2.4 1.4 2420
2.3 1.3 3130 12.5
2.5 1.5 2305 11.5
2.3 1.3 3130 12.5
2.7 1.6 1190
2.7 1.6 870
2.7 1.7 675
2.7 1.7 675
) leads to
OSS
CRSS/
R R
CISS
G DS(ON)
(%) (Ω) (Ω)
0.65 0.9 6.3
0.62 1.2 13.5
0.38 1.0 6.2
0.75 1.5 19.0
0.75 1.5 19.0
0.45 0.6 15.5
8.0 0.68 0.7 32.0
7 0.59 3 33
11 0.45 3 15.5
0.40 3 10.6
0.50 3 15.5
0.40 3 10.6
7 0.59 3 33
3.5 0.40 3 43.5
4.0 0.59 2.9 66.0
4.0 0.59 2.9 66.0
Another important parameter in the selection of SR FET is the reverse
recovery time (T ) of its body diode. The reverse recovery
RR
characteristics of the SR FET's body diode can influence the level of
voltage stress on the drain when the primary MOSFET switches on.
As shown in Figure 17, the SR FET with a slow body diode (> 40 ns
T ) has twice the voltage stress compared to the one with a fast
RR
body diode. The recommended maximum reverse recovery time
(T ) of the body diode is less than 40 ns.
RR
Output Filter Capacitance (C
The current ripple rating of the output capacitor(s) should be greater
than the calculated value in the spreadsheet, IRIPPLE_CAP_OUTPUT1.
However in designs with high peak to continuous (average) power
GD
and for those with long duration peak load conditions, the capacitor
rating may need to be increased. Selection in this one should be
based on the measured capacitor temperature rise under worst-case
load and ambient temperature conditions. The spread- sheet
calculates the output capacitor ripple current using the average
T Package Manufacturer
RR
(ns)
8-SOIC (0.154",
22 Alpha & Omega
3.90 mm Width)
8-SOIC (0.154",
15 Alpha & Omega
3.90 mm Width)
8-PowerSMD,
17 Alpha & Omega
Flat Leads
8-PowerSMD,
17 Alpha & Omega
Flat Leads
15 8-PowerVDFN Alpha & Omega
8-SOIC (0.154",
25 Alpha & Omega
3.90 mm Width)
8-WDFN
24 Alpha & Omega
Exposed Pad
20 SOIC-8 Alpha & Omega
25 SOIC-8 Alpha & Omega
28 SOIC-8 Alpha & Omega
30 TO-252 Alpha & Omega
30 TO-252 Alpha & Omega
30 TO-252 Alpha & Omega
20 TO-252 Alpha & Omega
37 TO-252 DPAK Alpha & Omega
8-WDFN
37 Alpha & Omega
Exposed Pad
)
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