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ADV7170KSU (IC402)
ADV7170KSU Terminal Function
Pin
Pin Name
I/O
No.
1
VAA
2
P5
3
P6
4
P7
5
P8
6
P9
7
P10
8
P11
9
P12
10
GND
11
VAA
12
P13
13
P14
14
P15
15
HSYNC
I/O
16
FIELD/VSYNC
I/O
17
BLANK
I/O
18
ALSB
19
GND
20
VAA
21
GND
22
RESET
23
SCLOCK
24
SDATA
I/O
25
COMP
26
DAC C
27
DAC D
28
VAA
29
GND
30
VAA
31
DAC B
32
DAC A
33
VREF
I/O
34
RSET
35
SCRESET/RTC
36
TTXREQ/GND
37
TTX/VAA
38
P0
39
P1
40
P2
41
P3
42
P4
43
GND
44
CLOCK
44
43
42
41
V
1
AA
P5
2
P6
3
4
P7
P8
5
TOP VIEW
P9
6
P10
7
P11
8
P12
9
GND
10
V
11
AA
12 13 14 15 16 17 18 19 20 21 22
P
Power supply (+3V~+5V)
I
8-bit 4:2:2 multiplexed YCrCb pixel port (P7-P0)
I
8-bit 4:2:2 multiplexed YCrCb pixel port (P7-P0)
I
8-bit 4:2:2 multiplexed YCrCb pixel port (P7-P0)
I
16-bit YCrCb pixel port (P15-P8)
I
16-bit YCrCb pixel port (P15-P8)
I
16-bit YCrCb pixel port (P15-P8)
I
16-bit YCrCb pixel port (P15-P8)
I
16-bit YCrCb pixel port (P15-P8)
G
GND
P
Power supply (+3V~+5V)
I
16-bit YCrCb pixel port (P15-P8)
I
16-bit YCrCb pixel port (P15-P8)
I
16-bit YCrCb pixel port (P15-P8)
/HSYNC (Modes 1 and 2) control signal
Dual function FIELD (Mode 1) and /VSYNC (Mode 2) control signal
Video blanking control signal
I
TTL address input
G
GND
P
Power supply (+3V~+5V)
G
GND
I
The input resets the on chip timing generator
I
MPU port serial interface clock input
MPU port serial data input/output
O
Compensation capacitor connect pin
O
RED/S-Video C/V analog output
O
GREEN/S-Video Y/Y analog output
P
Power supply (+3V~+5V)
G
GND
P
Power supply (+3V~+5V)
O
BLUE/Composite/U analog output
O
PAL/NTSC composite video signal output
Voltage reference input for DACs or voltage reference output (1.235V)
I
Resistor connect pin to control full-scale amplitudes of the video signals
I
Sub-carrier reset / Real time control (RTC) input
O
Teletext data request signal / Default to GND when teletext not selected
I
Teletext data / Default to VAA when teletext not selected
I
8-bit 4:2:2 multiplexed YCrCb pixel port (P7-P0)
I
8-bit 4:2:2 multiplexed YCrCb pixel port (P7-P0)
I
8-bit 4:2:2 multiplexed YCrCb pixel port (P7-P0)
I
8-bit 4:2:2 multiplexed YCrCb pixel port (P7-P0)
I
8-bit 4:2:2 multiplexed YCrCb pixel port (P7-P0)
G
GND
I
TTL clock input, requires a stable 27MHz reference clock
40
39
38
37
36
35
34
33
V
REF
32
DAC A
31
DAC B
30
V
AA
29
GND
28
V
AA
27
DAC D
26
DAC C
25
COMP
24
SDATA
23
SCLOCK
Function
DN-V1700
22
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