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I/O
I/O
Pin Name
During
After
Config.
Config.
LDC
O
I/O
INIT
I/O
I/O
PGCK1-
Weak
PGCK4
I or I/O
Pull-up
(Spartan)
Weak
SGCK1-
Pull-up
SGCK4
(except
I or I/O any of these pins is a user-programmable I/O pin.
(Spartan)
SGCK4
is DOUT)
Weak
Pull-up
GCK1-GCK8
(except
I or I/O pins is a user-programmable I/O pin.
(Spartan-XL)
GCK6 is
DOUT)
CS1
I
I/O
(Spartan-XL)
D0-D7
I
I/O
(Spartan-XL)
DIN
I
I/O
DOUT
O
I/O
Unrestricted User-Programmable I/O pins
Weak
I/O
I/O
Pull-up
BT864A (IC401)
FS ADJUST
1
VBIAS
2
VREF
3
VAA
4
COMP
5
AGND
6
AGND
7
CVBS/B
8
AGND
9
CVBS/G
10
11
AGND
C/R
12
Y/CVBS
13
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a control output
indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ to 10kΩ external pull-up resistor
is recommended.
As an active Low open-drain output, INIT is held Low during the power stabilization and internal
clearing of the configuration memory. As an active Low input, it can be used to hold the FPGA in the
internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an
additional 30 to 300 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has occurred. After
the I/O go active, INIT is a user-programmable I/O pin.
Four Primary Global inputs each drive a dedicated internal global net with short delay and minimal
skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol connected
directly to the input of a BUFGP symbol is automatically placed on one of these pins.
Four Secondary Global inputs each drive a dedicated internal global net with short delay and minimal
skew. These internal global nets can also be driven from internal logic. If not used to drive a global net,
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad
symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins.
Eight Global inputs each drive a dedicated internal global net with short delay and minimal skew. These
internal global nets can also be driven from internal logic. If not used to drive a global net, any of these
The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew Buffers. Any input pad
symbol connected directly to the input of a BUFGLS symbol is automatically placed on one of these pins.
During Express configuration, CS1 is used as a serial-enable signal for daisy-chaining.
During Express configuration, these eight input pins receive configuration data.
After configuration, they are user-programmable I/O pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration data input receiving
data on the rising edge of CCLK. After configuration, DIN is a user-programmable I/O pin.
During Slave Serial or Master Serial configuration, DOUT is the serial configuration data output that can
drive the DIN of daisy-chained slave FPGAs.
DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at
the DIN input.
In Spartan-XL Express mode, DOUT is the status output that can drive the CS1 of daisy-chained
FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
These pins can be configured to be input and/or output after configuration is completed. Before
configuration is completed, these pins have an internal high-value pull-up resistor network that defines
the logic level as High.
SDA
2
SCL
I
C Interface
ALTADDR
39
SLEEP
38
TTXREQ
37
VDD
36
GND
35
P[7]
8
P[7:0]
34
P[6]
33
P[5]
DEMUX,
4:2:2 -> 4:4:4
32
P[4]
Upsample,
8
31
P[3]
Y[7:0]
Magnitude
Scaling
30
P[2]
29
P[1]
28
P[0]
27
TTXDAT
CLK
RGBOUT
SLEEP
VDD3V
Pin Description
VBIAS
Internal Voltage
SLAVE
Reference
FIELD
Video
Timing
HSYNC
BLANK
Control
VSYNC
TTXDAT
TTXREQ
RESET
Teletext/
CGMS
NTSC
Sync
Blanking
Rise/Fall
Pedestal
Expander
Luminance
Closed
Y
10
10
+
+
Captioning,
2X
Macrovision
Upsample
Color
Space
Convert
Modulator
1.3 MHz LPF
U/V
10
10
10
and 2X
and
Upsample
Mixer
BLANK
DN-V1700
VREF
FSADJUST
COMP
10
Y/CVBS
DAC
10
10
+
DAC
CVBS/G
9
Luma
+
Delay
G
9
B
10
DAC
CVBS/B
R
9
DAC
C/R
10
18
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