Denon DN-V1700 Service Manual page 20

Pin No. Name
127 Receive Data Valid
44 Local Bus Clock
Asynchronous
40
Ready
nSynchronous
45
Ready
48 nReady Return
31 Interrupt
47 nLocal Device
33 nReady Strobe
34 nWrite Strobe
nData Path
36
Chip Select
83-94 Address
80-82 Address
43 Address Enable
96-99 nByte Enable
106-109,
101-104,
75-78, 70-73, Data Bus
65-68, 60-63,
55-58, 50-53
32 Reset
39 nAddress Strobe
37 nCycle
38 Write/nRead
42 nVL Bus Access
Collision Detect
114
100 Mbps
115-118 Transmit Data
111 Transmit Clock
Buffer
Symbol
Type
I with Input from MII PHY. Envelope of data valid reception. Used for receive data
RX_DV
pulldown framing.
Input. Used to interface synchronous buses. Maximum frequency is 50 MHz.
LCLK I**
Limited to 8.33 MHz for EISA DMA burst mode.
Open drain output. ARDY may be used when interfacing asynchronous buses to
extend accesses. Its rising (access completion) edge is controlled by the XTAL1
clock and, therefore, asynchronous to the host CPU or bus clock. ARDY is
ARDY OD16
negated during Asynchronous cycle when one of the following conditions
occurs: 1) No_Wait Bit in the Configuration Register is cleared. 2) Read FIFO
contains less than 4 bytes when read. 3) Write FIFO is full when write.
Output. This output is used when interfacing synchronous buses and nVLBUS=0
nSRDY O16 to extend accesses. This signal remains normally inactive, and its falling edge
indicates completion. This siganal is synchronous to the bus clock LCLK.
Input. This input is used to complete synchronous read cycles. In EISA burst
nRDYRTN I** mode it is sampled on falling LCLK edges, and synchronous cycles are delayed
until it is sampled high.
Interrupt Output-Used to interrupt the Host on a status event.
Note: The selection bits used to determined by the value of INT SEL 1-0 bits in
INTR0 O24
the Configuration Register are no longer required and have been set to
reserved in this revision of the FEAST family of devices.
Output. This active low output is asserted when AEN is low and A4-A15 decode
to the LAN91C111 address programmed into the high byte of the Base Address
nLDEV O16
Register. nLDEV is a combinatorial decode of unlatched address and AEN
signals.
nRD IS** Input. Used in asynchronous bus interfaces.
nWR IS** Input. Used in asynchronous bus interfaces.
Input. When nDATACS is low, the Data Path can be accessed regardless of the
I with values of AEN, A1-A15 and the content of the BANK SELECT Register.
nDATACS
pullup** nDATACS provides an interface for bursting to and from the LAN91C111 32 bits
at a time.
A4-A15 I** Input. Decoded by LAN91C111 to determine access to its registers.
A1-A3 I** Input. Used by LAN91C111 for internal register selection.
Input. Used as an address qualifier. Address decoding is only enabled when
AEN I**
AEN is low.
Input. Used during LAN91C111 register accesses to determine the width of the
nBE0-
I** access and the register(s) being access. nBE0-nBE3 are ignored when
nBE3
nDATACS is low (burst accesses) because 32 bit transfers are assumed.
Bidirectional. 32 bit data bus used to access the LAN91C111's internal registers.
D0-D31 I/O24** Data bus has weak internal pullups. Supports direct connection to the system
bus without external buffering. For 16 bit systems, only D0-D15 are used.
Input. When this pin is asserted high, the controller performs an internal system
(MAC&PHY) reset. It programs all the registers to their default value, the
RESET IS** controller will read the EEPROM device through the EEPROM interface(1). This
input is not considered active unless it is active for at least 100ns to filter narrow
glitches.
Input. For systems that require address latching, the rising edge of nADS
nADS IS** indicates the latching moment for A1-A15 and AEN. All LAN91C111 internal
functions of A1-A15, AEN are latched except for nLDEV decoding.
Input. This active low signal is used to control LAN91C111 EISA burst mode
nCYCLE I**
synchronous bus cycle.
Input. Defines the direction of synchronous cycles. Write cycles when high, read
W/nR IS**
cycles when low.
Input. When low the LAN91C111 synchronous bus interface is configured for VL
I with
nVLBUS Bus accesses. Otherwise, the LAN91C111 is configured for EISA DMA burst
pullup**
accesses. Does not affect the asynchronous bus interface.
I with
COL100 Input from MII PHY. Collision detection input.
pulldown
TXD0-
O12 Output. Transmit Data nibble to MII PHY.
TXD3
I with Input. Transmit clock input from MII. Nibble rate clock
TX25
pullup (25MHz for 100Mbps & 2.5MHz for 10Mbps).
Description
DN-V1700
20