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Configuration
Registers
Channel Enable
Registers
Writing to the Registers
Status/Control
Register
Channel Enable
Registers
98 Relay Driver Register Definitions
A read of the configuration registers will return their current value. All bits
are normally left open which will return FFFF
contained in the 8 least significant bits used in the three Configuration
Registers. The upper 8 bits of each configuration register are always high.
The only bits defined are bits CNFG 0 through CNFG 4 in Configuration
Register 0. All other bits are ignored by the SCPI Driver.
A read of any of the Channel Enable registers always returns FFFF
regardless of the driver states.
You can write to the following Relay Driver Module registers. A description
of each register follows. See "Register Definitions" for additional details on
each register
Register
Status/Control Register
Channel Enable Register 0
Channel Enable Register 1
Channel Enable Register 2
Channel Enable Register 3
Channel Enable Register 4
Channel Enable Register 5
The Status/Control register (base + 04
resets the module. All drivers will be open, no longer sinking current.
Resetting the module will also enable interrupts. It is necessary to write a "0'
to bit 0 after the reset has been performed before any other commands can
be programmed and executed.
To disable the interrupt generated when channels are opened/closed, write a
"1' to bit 6 of the Status/Control Register.Typically, interrupts are disabled
when doing register level access to a module. Refer to the operating manual
of the Command Module or the embedded controller being used to handle
interrupts. A SYSRESET will re-enable interrupts.
Writes to the Channel Enable registers (base + 10
enable you to open or close the desired channel (see "Register Definitions").
When a channel is closed, it sinks current. Setting a bit to "1" closes a
channel. Writing a "0" to a channel opens the channel, thus causing it
to stop sinking current.
. There are 24 bits of input
h
Address
base + 04
h
base + 10
h
base + 12
h
base + 14
h
base + 16
h
base + 18
h
base + 1A
h
) is set to bit 0. Writing a "1" to bit 0
h
through base + lA
h
,
h
)
h
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