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10.3.2
8067 ESI interface pinouts
In 8067, the ESI function becomes a bi-directional interface. Three pins are defined for control functions and
the remaining four pins become a 4-bit nibble interface. Table 58 is a mapping of the Select pins to the 8067
ESI interface function. 8067 specifies that open-collector type drivers be used for signals on the P_ESI and
Select lines.
Table 58:
SFF 8067 ESI pinouts
Pin
ESI function
–DSK_WR
SEL 6
–DSK_RD
SEL 5
–ENCL_ACK
SEL 4
Data (3)
SEL 3
Data (2)
SEL 2
Data (1)
SEL 1
Data (0)
SEL 0
10.3.3
8067 information format
ESI in 8067 mode is transferred on the ESI interface a nibble (4 bits) at a time. Refer to Table 59 for the trans-
fer order in bits and Table 60 for byte order.
Table 59:
Bit order in 8067 mode ESI transfers
Bit order byte
Transfer order on ESI interface
Bit order is ESI data
Table 60:
Byte order in 8067 mode ESI transfers
Byte order in SCSI transfer
Byte order is ESI transfer
Fibre Channel Interface Manual, Rev. D
MSB
7
6
5
First Nibble
D(3)
D(2)
D(1)
0
1
..........
first
second
..........
4
3
2
Second Nibble
D(0)
D(3)
D(2)
n – 1
n
n – 1
n
LSB
1
0
D(1)
D(0)
105
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