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Summary of Contents for IDT Tsi382
- Page 1 ® Tsi382 (BGA) ™ Evaluation Board User Manual 60E2010_MA001_03 September 28, 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2009 Integrated Device Technology, Inc.
- Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
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Page 3: Table Of Contents
J22 Tsi382 JTAG ........ - Page 4 LEDs ................. . . 31 Tsi382 (BGA) Evaluation Board User Manual...
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Page 5: About This Document
About this Document This document describes how to test the key features of the Tsi382 using the Tsi382 evaluation board. It can be used in conjunction with the Tsi382 Evaluation Board Schematics. Related Information • Tsi382 User Manual • Tsi382 Evaluation Board Schematics •... - Page 6 About this Document Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com...
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Page 7: Board Design
“Hardware Reset” on page 16 • “Logic Analyzer Connectivity” on page 17 Overview The key features of the Tsi382 evaluation board include the following (see also Figure • Single x1 lane, 2.5 Gbps PCIe 1.1 compatible riser card (extended height form factor) •... - Page 8 EEPROM Header EEPROM JTAG Management 3.3V PCI 32-bit Connector Slot 0 3.3V PCI 32-bit Connector Slot 1 3.3V PCI 32-bit Connector Slot 2 3.3V PCI 32-bit Connector Slot 3 Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com...
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Page 9: Pci Interface
The following pull-ups are added to the PCI bus, in which a value of 8.2Kohm is used. Table 2: PCI Pull-up Signals Signal Description PCI_REQ#[0:3] Bus request PCI_GNT#[0:3] Bus grant PCI_FRAME# Control signal PCI_IRDY#, PCI_TRDY# Control signal Integrated Device Technology Tsi382 (BGA) Evaluation Board User Manual www.idt.com 60E2010_MA001_03... -
Page 10: Pcie Interface
PCI Power Management Event occurred PCIe Interface The Tsi382 evaluation board implements a single lane PCIe Interface. It is designed to connect to a PCIe system with a standard x1 finger connector. The system must provide the REFCLK and PERSTN signals. -
Page 11: Power Requirements
PCIe 3.3V supply 3.3V_A_384 Passive Filter The target power draw of the Tsi382 is a maximum of 1W, all supplies combined. The supplies to the Tsi382 are controlled during ramp up using enable pins on regulators and switches. 1.4.2.1 PCIe The PCIe CEM Specification 1.1 defines power limits on PCIe slots according to the number of lanes... - Page 12 The evaluation board senses the presence of this supply, and disables the slave PCIe slot power. For the case of a separate external ATX supply, all four slots are provided with the required power. Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03...
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Page 13: Power Sequencing
1. Board Design > Power Management 1.4.3 Power Sequencing On power-up, the board’s power sequence is as follows: 1. 1.2V powered on 2. PCI I/O slot power and pull-ups, and Tsi382 3.3V 12V/-12V/5V PCI are not sequence controlled. 1.4.4 System Power Design Figure 2 illustrates the power distribution for the riser card. -
Page 14: Pci Vaux (Pci Auxiliary) Support
The evaluation board supports master and slave clocking for PCI. • Master – When in master mode, the Tsi382 generates the required PCI clock for all slots. • Slave – When in slave mode, an on-board selectable 25–66 MHz clock generator is used. -
Page 15: System Clock Distribution
Other Interfaces 1.6.1 JTAG Interface To support debug and testing of device, JTAG access to the Tsi382 is available using a standard JTAG header for Wiggler connection. For more information about accessing the Tsi382 using JTAG, see the JTAG Register Access Software Application Note. -
Page 16: Gpio Interface
— D1: GPIO1, active led when driven low — D13: GPIO2, active led when driven low — D12: GPIO3, active led when driven low Hardware Reset The following figure shows the reset options of the Tsi382 evaluation board. Figure 4: Board Reset Reset PUSHBUTTON... -
Page 17: Logic Analyzer Connectivity
For more information on cold, warm, and hot reset levels, see the “Resets, Clocking, and Initialization Options” chapter in the Tsi382 User Manual. Logic Analyzer Connectivity The serial buses have Midbus pads (TMS818 probe) for visibility of SerDes lines using a pre-processor. - Page 18 1. Board Design > Logic Analyzer Connectivity Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com...
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Page 19: Configurable Options
DIP Switches Switches S1 to S6 combine four, small slide switches identified with numbers 1 to 4 (see Figure 6 individual switch definition). Figure 5: DIP Switch Package/Individual Switch Position Integrated Device Technology Tsi382 (BGA) Evaluation Board User Manual www.idt.com 60E2010_MA001_03... - Page 20 2. Configurable Options > Switches Figure 6: Switch Locations Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com...
- Page 21 Switches S3 and S4 are used to set the PCI bus external clock frequency. By default the PCI bus clock source is the Tsi382. The external clock can only be connected to the PCI bus by replacing resistors on the board. When an external clock source is used, an on-board PLL is used to set the proper bus clock frequency.
- Page 22 OFF = On-board PCIe clock multiplexer is enabled. enable PCIe clock ON = On-board PCIe reference clock is used. source select OFF = System PCIe reference clock is used. Switch S6 configures Tsi382’s power-up options. Table 11: S6 Settings Switch Default Number Description...
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Page 23: Push Button
2.1.2 Push Button SW1 is used to turn the ATX power supply ON. This switch is used only when the Tsi382 evaluation board is powered up with a stand-alone ATX power supply. SW2 is used to reset the evaluation board. When pushing the reset button, the board is reset the same way a PCIe system reset would reset the board. -
Page 24: Shunt Jumpers
2. Configurable Options > Shunt Jumpers Shunt Jumpers Shunt jumpers control special features on the evaluation board (see Figure 7). These jumpers are explained in the following sub-sections. Figure 7: Shunt Jumper Locations Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com... -
Page 25: J6 Shunt Jumper
Normal operation, ATX power supply is turned On/OFF from push button. 2.2.2 J21 Shunt Jumper J21 is used to force the Tsi382 into a special debug mode. The Default State for this jumper is ON. Integrated Device Technology Tsi382 (BGA) Evaluation Board User Manual www.idt.com... -
Page 26: Debug Headers
2. Configurable Options > Debug Headers Debug Headers Debug headers are used to connect to signals on the evaluation board (see Figure 8). This section provides header pinouts. Figure 8: Debug Header Locations Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com... -
Page 27: J22 Tsi382 Jtag
2. Configurable Options > Debug Headers 2.3.1 J22 Tsi382 JTAG Table 13: J22 Pin Assignment Number Signal Assignment Pin Location 3.3V 3.3V Integrated Device Technology Tsi382 (BGA) Evaluation Board User Manual www.idt.com 60E2010_MA001_03... -
Page 28: J23 Logic Analyzer Pads
2. Configurable Options > Debug Headers 2.3.2 J23 Logic Analyzer PADs Table 14: J23 Pin Assignment Number Signal Assignment Pin Location PCIE_RXD_EDG_P0 PCIE_RXD_EDG_N0 PCIE_TXD_EDG_P0 PCIE_TXD_EDG_N0 Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com... -
Page 29: Connectors
2. Configurable Options > Connectors Connectors Figure 9: Board Connector Locations J2 (Slot 0) J36 (Slot 1) J1 (Slot 2) J37 (Slot 3) Figure 10: Integrated Device Technology Tsi382 (BGA) Evaluation Board User Manual www.idt.com 60E2010_MA001_03... -
Page 30: J1, J2, J36, J37 Connectors
2. Configurable Options > Connectors 2.4.1 J1, J2, J36, J37 Connectors These connectors are used to connect a plug-in card to the Tsi382’s PCI Interface. The connectors’ pin assignments are as per the PCI standard for 32-bit connectors. 2.4.2 J3 ATX Power Connector A standard ATX power supply can be used to power up the board when used stand alone (not plugged into a PCIe system). -
Page 31: P1 X1 Pcie Finger Connector
LEDs D2–D8 indicate voltage supplies that are present on the evaluation board. Depending on whether your board is powered from the PCIe slot or the ATX power connector, the LEDs will indicate the source of power for the board. Integrated Device Technology Tsi382 (BGA) Evaluation Board User Manual www.idt.com 60E2010_MA001_03... - Page 32 2. Configurable Options > LEDs Figure 11: LED Locations D2-D8 Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com...
- Page 33 Default Description State On/Off Setting PCI 66 MHz OFF = The Tsi382 PCI Interface is operating at 66 MHz. ON = The Tsi382 PCI Interface is operating at 33 MHz. Integrated Device Technology Tsi382 (BGA) Evaluation Board User Manual www.idt.com...
- Page 34 2. Configurable Options > LEDs Tsi382 (BGA) Evaluation Board User Manual Integrated Device Technology 60E2010_MA001_03 www.idt.com...
- Page 35 Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
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