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ST SPC560P34 Reference Manual

32-bit mcu on the embedded power architecture

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RM0046

Reference manual

SPC560P34/SPC560P40 32-bit MCU family

®

built on the embedded Power Architecture

Introduction

®

The SPC560P40/34 microcontroller is built on the Power Architecture

platform. The Power

Architecture based 32-bit microcontrollers represent the latest achievement in integrated

automotive application controllers. This device family integrates the most advanced and up-

to-date motor control design features.

The safety features included in SPC560P40/34 (such us fault collection unit, safety port or

flash memory and SRAM with ECC) support the design of system applications where safety

is a requirement.

September 2013

Doc ID 16912 Rev 5

1/936

www.st.com

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Summary of Contents for ST SPC560P34

Page 1 RM0046 Reference manual SPC560P34/SPC560P40 32-bit MCU family ® built on the embedded Power Architecture Introduction ® The SPC560P40/34 microcontroller is built on the Power Architecture platform. The Power Architecture based 32-bit microcontrollers represent the latest achievement in integrated automotive application controllers. This device family integrates the most advanced and up- to-date motor control design features.
Page 2: Table Of Contents
Contents RM0046 Contents Preface ............45 Overview .
Page 3 RM0046 Contents 1.6.20 Controller area network (FlexCAN) ......60 1.6.21 Safety port (FlexCAN) ........61 1.6.22 Serial communication interface module (LINFlex) .
Page 4 Contents RM0046 Alternate module clock domains ....... 96 4.3.1 FlexCAN clock domains ........96 4.3.2 SWT clock domains .
Page 5 RM0046 Contents 5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) . . 128 5.5.7 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) ..128 5.5.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) . . 129 5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) .
Page 6 Contents RM0046 Introduction ..........184 7.1.1 Overview .
Page 7 RM0046 Contents 9.6.3 Handshaking with processor ....... . 230 Initialization/application information ......232 9.7.1 Initialization flow .
Page 8 Contents RM0046 11.6.1 General ..........267 11.6.2 Pad control .
Page 9 RM0046 Contents 14.6.5 Priority assignment ........284 14.6.6 Arbitration .
Page 10 Contents RM0046 17.2.11 Error termination ......... 317 17.2.12 Access pipelining .
Page 11 RM0046 Contents 18.7.4 DMA arbitration mode considerations ......417 18.7.5 DMA transfer ..........417 18.7.6 TCD status .
Page 12 Contents RM0046 20.6.2 Signal names and descriptions ......441 20.7 Memory map and registers description ......442 20.7.1 Memory map .
Page 13 RM0046 Contents 21.8 Functional description ........518 21.8.1 UART mode .
Page 14 Contents RM0046 23.1.1 Device-specific features ........575 23.1.2 Device-specific pin configuration features .
Page 15 RM0046 Contents 24.4.2 ADC commands list format ....... . . 610 24.4.3 ADC results .
Page 16 Contents RM0046 25.2 Features ..........643 25.3 Modes of operation .
Page 17 RM0046 Contents 25.8.10 Manual correction ........693 25.8.11 Output logic .
Page 18 Contents RM0046 26.10 DMA ........... . 736 Functional Safety .
Page 19 RM0046 Contents 29.3 External signal description ........776 29.4 Memory map and registers description .
Page 20 Contents RM0046 32.2.1 Standard features ........796 32.3 Block diagram .
Page 21 RM0046 Contents IEEE 1149.1 Test Access Port Controller (JTAGC) ....841 35.1 Introduction ..........841 35.2 Block diagram .
Page 22 Contents RM0046 36.6 External signal description ........856 36.7 Memory map and registers description .
Page 23 RM0046 Contents 36.15 Functional description ........912 36.15.1 Enabling Nexus clients for TAP access .
Page 24 List of tables RM0046 List of tables Table 1. SPC560P40/34 device comparison ......... . 48 Table 2.
Page 25 RM0046 List of tables Table 49. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions. . . 167 Table 50. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions ....168 Table 51.
Page 26 List of tables RM0046 Table 101. PSMI[0_3:32_35] field descriptions ......... 260 Table 102.
Page 27 RM0046 List of tables Table 153. LMS field descriptions........... . 352 Table 154.
Page 28 List of tables RM0046 Table 205. DSPI memory map ............442 Table 206.
Page 29 RM0046 List of tables Table 257. IFMR[IFM] configuration ..........515 Table 258.
Page 30 List of tables RM0046 Table 309. CDR field descriptions ........... 602 Table 310.
Page 31 RM0046 List of tables Table 361. Fault mapping ............696 Table 362.
Page 32 List of tables RM0046 Table 413. Bi-stable coding ............775 Table 414.
Page 33 RM0046 List of tables Table 465. DBERC0 Resource Control ..........886 Table 466.
Page 34 List of figures RM0046 List of figures Figure 1. Electric power steering application ......... . . 47 Figure 2.
Page 35 RM0046 List of figures Figure 49. Debug Mode Transition Status Register (ME_DMTS) ......155 Figure 50.
Page 36 List of figures RM0046 Figure 101. Interrupt Request Enable Register (IRER) ........255 Figure 102.
Page 37 RM0046 List of figures Figure 153. Module Configuration Register (MCR) ........342 Figure 154.
Page 38 List of figures RM0046 Figure 205. DSPI block diagram ........... . . 437 Figure 206.
Page 39 RM0046 List of figures Figure 257. UART mode 9-bit data frame ..........518 Figure 258.
Page 40 List of figures RM0046 Figure 309. Trigger Generator Sub-unit Input Selection Register (TGSISR) ....621 Figure 310. Trigger Generator Sub-unit Control Register (TGSCR) ......624 Figure 311.
Page 41 RM0046 List of figures Figure 361. Center-aligned example ..........675 Figure 362.
Page 42 List of figures RM0046 Figure 413. Quadrature incremental position encoder........730 Figure 414.
Page 43 RM0046 List of figures Figure 465. STM Control Register (STM_CR) ......... . . 791 Figure 466.
Page 44 List of figures RM0046 Figure 517. OnCE Command Register ..........896 Figure 518.
Page 45: Preface
As with any technical documentation, it is the reader’s responsibility to be sure he or she is using the most recent version of the documentation. To locate any published errata or updates for this document, visit the ST Web site at www.st.com.
Page 46: Introduction
Introduction RM0046 Introduction The SPC560P40/34 microcontroller family ® The SPC560P40/34 microcontroller is built on the Power Architecture platform. The Power Architecture based 32-bit microcontrollers represent the latest achievement in integrated automotive application controllers. This device family integrates the most advanced and up- to-date motor control design features.
Page 47: Target Applications
RM0046 Introduction Target applications The SPC560P40/34 belongs to an expanding range of automotive-focused products designed to address and target the following chassis and safety market segments: ● Electric hydraulic power steering (EHPS) ● Lower end of electric power steering (EPS) ●...
Page 48: Features
SPC560P40/34 family and their features—relative to full-featured version—to enable a comparison among the family members and an understanding of the range of functionality offered within this family. Table 1. SPC560P40/34 device comparison SPC560P34 SPC560P40 Feature Full-featured Full-featured...
Page 49 RM0046 Introduction Table 1. SPC560P40/34 device comparison (continued) SPC560P34 SPC560P40 Feature Full-featured Full-featured INTC (interrupt controller) channels PIT (periodic interrupt timer) 1 (with four 32-bit timers) eDMA (enhanced direct memory access) channels 1,(2) FlexCAN (controller area network) Yes (via second FlexCAN...
Page 50: Table 2. Spc560P40 Device Configuration Differences
Introduction RM0046 Table 2. device configuration differences SPC560P40 Configuration Feature Airbag Full-featured SRAM (with ECC) 16 KB 20 KB FlexCAN (controller area network) Safety port (via second FlexCAN module) FlexPWM (pulse-width modulation) channels (capture capability not supported) CTU (cross triggering unit) Figure 1.4 shows a top-level block diagram of the SPC560P40/34 microcontroller.
Page 51: Figure 3. Block Diagram (Spc560P40 Full-Featured Configuration)
RM0046 Introduction External ballast e200z0 Core 32-bit 1.2 V regulator general control purpose registers XOSC Integer Special Exception Interrupt execution purpose handler controller 16 MHz unit registers RC oscillator Variable Instruction length FMPLL_0 unit encoded (System) instructions Branch Load/store JTAG prediction unit unit...
Page 52: Critical Performance Parameters
Introduction RM0046 Critical performance parameters ● Fully static operation, 0–64 MHz ● –40 °C to 150 °C junction temperature ● Low power design – Less than 450 mW power dissipation – Halt and STOP mode available for power reduction – Resuming from Halt/STOP mode can be initiated via external pin ●...
Page 53: Module Features
RM0046 Introduction ● Interrupts and events – 16-channel eDMA controller – 16 priority level controller – Up to 25 external interrupts – PIT implements four 32-bit timers – 120 interrupts are routed via INTC ● General purpose I/Os – Individually programmable as input, output or special function –...
Page 54: Crossbar Switch (Xbar)
Introduction RM0046 ● Branch processing acceleration using lookahead instruction buffer ● Load/store unit – 1-cycle load latency – Misaligned access support – No load-to-use pipeline bubbles ● Thirty-two 32-bit general purpose registers (GPRs) ● Separate instruction bus and load/store bus Harvard architecture ●...
Page 55: Flash Memory
RM0046 Introduction data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. The eDMA module provides the following features: ● 16 channels support independent 8-, 16- or 32-bit single value or block transfers ●...
Page 56: Static Random Access Memory (Sram)
Introduction RM0046 ● Read page sizes – Code flash memory: 128 bits (4 words) – Data flash memory: 32 bits (1 word) ● ECC with single-bit correction, double-bit detection for data integrity – Code flash memory: 64-bit ECC – Data flash memory: 32-bit ECC ●...
Page 57: System Status And Configuration Module (Sscm)
RM0046 Introduction ● Ability to modify the ISR or task priority: modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. ● 1 external high priority interrupt (NMI) directly accessing the main core and I/O processor (IOP) critical interrupt mechanism 1.6.7 System status and configuration module (SSCM)
Page 58: Main Oscillator
Introduction RM0046 1.6.10 Main oscillator The main oscillator provides these features: ● Input frequency range: 4–40 MHz ● Crystal input mode or oscillator input mode ● PLL reference 1.6.11 Internal RC oscillator This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a capacitor.
Page 59: Fault Collection Unit (Fcu)
RM0046 Introduction 1.6.15 Fault collection unit (FCU) The FCU provides an independent fault reporting mechanism even if the CPU is malfunctioning. The FCU module has the following features: ● FCU status register reporting the device status ● Continuous monitoring of critical fault signals ●...
Page 60: Error Correction Status Module (Ecsm)
Introduction RM0046 every time the device is powered on if the alternate boot mode has been selected by the user. The BAM provides the following features: ● Serial bootloading via FlexCAN or LINFlex ● Ability to accept a password via the used serial communication channel to grant the legitimate user access to the non-volatile memory 1.6.18 Error correction status module (ECSM)
Page 61: Safety Port (Flexcan)
RM0046 Introduction The FlexCAN module provides the following features: ● Full implementation of the CAN protocol specification, version 2.0B – Standard data and remote frames – Extended data and remote frames – Up to 8-bytes data length – Programmable bit rate up to 1 Mbit/s ●...
Page 62: Serial Communication Interface Module (Linflex)
Introduction RM0046 1.6.22 Serial communication interface module (LINFlex) The LINFlex (local interconnect network flexible) on the SPC560P40/34 features the following: ● Supports LIN Master mode (both instances), LIN Slave mode (only one instance) and UART mode ● LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications ●...
Page 63: Pulse Width Modulator (Flexpwm)
RM0046 Introduction ● End-of-transmission interrupt flag ● Programmable transfer baud rate ● Programmable data frames from 4 to 16 bits ● Up to 8 chip select lines available: – 8 on DSPI_0 – 4 each on DSPI_1 and DSPI_2 ● 8 clock and transfer attributes registers ●...
Page 64: Etimer
Introduction RM0046 ● Channels not used for PWM generation can be used for input capture functions ● Enhanced dual-edge capture functionality ● eDMA support with automatic reload ● 2 fault inputs ● Capture capability for PWMA, PWMB, and PWMX channels not supported 1.6.25 eTimer The SPC560P40/34 includes one eTimer module which provides six 16-bit general purpose...
Page 65: Analog-To-Digital Converter (Adc) Module
RM0046 Introduction 1.6.26 Analog-to-digital converter (ADC) module The ADC module provides the following features: Analog part: ● 1 on-chip analog-to-digital converter – 10-bit AD resolution – 1 sample and hold unit – Conversion time, including sampling time, less than 1 µs (at full precision) –...
Page 66: Nexus Development Interface (Ndi)
Introduction RM0046 It implements the following features: ● Double buffered trigger generation unit with up to 8 independent triggers generated from external triggers ● Trigger generation unit configurable in sequential mode or in triggered mode ● Each trigger can be appropriately delayed to compensate the delay of external low pass filter ●...
Page 67: On-Chip Voltage Regulator (Vreg)
● Autocode generation tools ● Initialization tools Package In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.
Page 68 Introduction RM0046 SPC560P40/34 family members are offered in the following package types: ● 64-pin LQFP, 0.5 mm pitch, 10 mm × 10 mm outline ● 100-pin LQFP, 0.5 mm pitch, 14 mm × 14 mm outline 68/936 Doc ID 16912 Rev 5...
Page 69: Spc560P40/34 Memory Map
RM0046 SPC560P40/34 memory map SPC560P40/34 memory map Table 3 shows the memory map for the SPC560P40/34. All addresses on the SPC560P40/34, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block. Table 3.
Page 70 SPC560P40/34 memory map RM0046 Table 3. Memory map (continued) Size Start address End address Region name (KB) 0xC3FF_0000 0xC3FF_3FFF Periodic Interrupt Timer (PIT) 0xC3FF_4000 0xC3FF_FFFF Reserved 0xFFE0_0000 0xFFE0_3FFF Analog to Digital Converter 0 (ADC_0) 0xFFE0_4000 0xFFE0_BFFF Reserved 0xFFE0_C000 0xFFE0_FFFF CTU_0 0xFFE1_0000 0xFFE1_7FFF Reserved...
Page 71 RM0046 SPC560P40/34 memory map Table 3. Memory map (continued) Size Start address End address Region name (KB) 0xFFFE_C000 0xFFFF_BFFF Reserved 0xFFFF_C000 0xFFFF_FFFF Boot Assist Module (BAM) 1. This address space contains also VREG registers. See 34, “Voltage Regulators and Power Supplies.” Doc ID 16912 Rev 5 71/936...
Page 72: Signal Description
Signal Description RM0046 Signal Description This chapter describes the signals of the SPC560P40/34. It includes a table of signal properties and detailed descriptions of signals. 100-pin LQFP pinout Figure 4 Figure 5 shows the pinout of the 100-pin LQFP. A[4] VPP_TEST A[6] D[14]...
Page 73: Figure 5. 100-Pin Lqfp Pinout - Airbag Configuration (Top View)
RM0046 Signal Description A[4] VPP_TEST A[6] D[14] D[1] C[14] A[7] C[13] C[4] D[12] A[8] N.C. C[5] N.C. A[5] D[13] C[7] VSS_LV_COR1 C[3] VDD_LV_COR1 N.C. A[3] N.C. VDD_HV_IO2 VDD_HV_IO1 LQFP100 VSS_HV_IO2 VSS_HV_IO1 D[9] VDD_HV_OSC VSS_HV_OSC XTAL A[2] EXTAL C[12] RESET C[11] D[8] D[11] D[5]...
Page 74: 64-Pin Lqfp Pinout
Signal Description RM0046 64-pin LQFP pinout A[4] A[6] VPP_TEST D[14]] A[7] D[12] A[8] D[13 A[5] VSS_LV_COR1 VDD_HV_IO1 VSS_HV_IO1 VDD_LV_COR1 A[3] D[9] LQFP64 VDD_HV_IO2 VDD_HV_OSC VSS_HV_IO2 VSS_HV_OSC XTAL EXTAL RESET D[8] C[12] VSS_LV_COR0 C[11] VDD_LV_COR0 Figure 6. 64-pin LQFP pinout – Full featured configuration (top view) 74/936 Doc ID 16912 Rev 5...
Page 75: Pin Description
RM0046 Signal Description A[4] A[6] VPP_TEST D[14] A[7] D[12] A[8] D[13] A[5] VSS_LV_COR1 VDD_HV_IO1 VSS_HV_IO1 VDD_LV_COR1 A[3] D[9] LQFP64 VDD_HV_IO2 VDD_HV_OSC VSS_HV_IO2 VSS_HV_OSC XTAL EXTAL RESET D[8] C[12] VSS_LV_COR0 C[11] VDD_LV_COR0 Figure 7. 64-pin LQFP pinout – Airbag configuration (top view) Pin description The following sections provide signal descriptions and related information about the functionality and configuration of the SPC560P40/34 devices.
Page 76: System Pins
Signal Description RM0046 Table 4. Supply pins Supply Symbol Description 64-pin 100-pin VREG control and power supply pins. Pins available on 64-pin and 100-pin packages BCTRL Voltage regulator external NPN ballast base control pin DD_HV_REG Voltage regulator supply voltage (3.3 V or 5.0 V) ADC_0 reference and supply voltage.
Page 77: Pin Multiplexing
RM0046 Signal Description Table 5. System pins Pad speed Symbol Description Direction SRC = 0 SRC = 1 64-pin 100-pin Dedicated pins Non-maskable Interrupt Input only Slow — Analog output of the oscillator amplifier XTAL circuit—needs to be grounded if oscillator is —...
Page 78: Table 6. Pin Muxing
Signal Description RM0046 Table 6. Pin muxing Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion Port A (16-bit) ALT0 GPIO[0] SIUL ALT1 ETC[0] eTimer_0 A[0] PCR[0] ALT2 DSPI_2 Slow Medium —...
Page 79 RM0046 Signal Description Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[7] SIUL ALT1 SOUT DSPI_1 A[7] PCR[7] ALT2 — — — Slow Medium ALT3 —...
Page 80 Signal Description RM0046 Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[14] SIUL ALT1 Safety Port_0 A[14] PCR[14] ALT2 — — — Slow Medium ALT3 —...
Page 81 RM0046 Signal Description Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[23] SIUL ALT1 — — ALT2 — — B[7] PCR[23] Input only —...
Page 82 Signal Description RM0046 Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[30] SIUL ALT1 — — ALT2 — — ALT3 — — B[14] PCR[30] Input only —...
Page 83 RM0046 Signal Description Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[36] SIUL ALT1 DSPI_0 C[4] PCR[36] ALT2 X[1] FlexPWM_0 Slow Medium — ALT3 DEBUG[4] SSCM...
Page 84 Signal Description RM0046 Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[45] SIUL ALT1 — — — ALT2 — — — C[13] PCR[45] Slow Medium —...
Page 85 RM0046 Signal Description Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[54] SIUL ALT1 DSPI_0 D[6] PCR[54] ALT2 — — — Slow Medium —...
Page 86 Signal Description RM0046 Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[63] SIUL ALT1 — — ALT2 — — D[15] PCR[63] Input only —...
Page 87 RM0046 Signal Description Table 6. Pin muxing (continued) Alternate Pad speed Port (1), function Functions Peripheral direc- register SRC = 0 SRC = 1 64-pin 100-pin tion ALT0 GPIO[70] SIUL ALT1 — — E[6] PCR[70] ALT2 — — Input only —...
Page 88: Ctu / Adc / Flexpwm / Etimer Connections
Signal Description RM0046 CTU / ADC / FlexPWM / eTimer connections Figure 8 shows the interconnections between the CTU, ADC, FlexPWM, and eTimer. External pins FlexPWM External pins PWMA0 Master reload PWM_REL TRIGGER_0 ADC0 PWMB0 OUT_TRIG0_0 PWM_ODD_0 ADC_CMD_0 OUT_TRIG0_1 NEXT_CMD_0 PWMA1 PWM_ODD_1 PWMB1...
Page 89 RM0046 Signal Description Table 7. CTU / ADC / FlexPWM / eTimer connections (continued) Source module Target module Comment (Signal) (Signal) PWM (OUT_TRIG0_3) CTU (PWM_ODD_3) OUT_TRIG0 sub-module 3 PWM (OUT_TRIG1_3) CTU (PWM_EVEN_3) OUT_TRIG1 sub-module 3 PWM (PWMX3) CTU (PWM_REAL_3) — PWM (PWMA0) SIU lite —...
Page 90 Signal Description RM0046 Table 7. CTU / ADC / FlexPWM / eTimer connections (continued) Source module Target module Comment (Signal) (Signal) The same GPIO pin as used for CTU (EXT_IN) and the PWM SIU lite CTU (EXT_IN) (EXT_SYNC) The same GPIO pin as used for CTU (EXT_IN) and the PWM SIU lite PWM (EXT_SYNC) (EXT_SYNC)
Page 91: Clock Description
RM0046 Clock Description Clock Description This chapter describes the clock architectural implementation for SPC560P40/34. The following clock related modules are implemented on the SPC560P40/34: ● Clock, Reset, and Mode Handling – Clock Generation Module (CGM) (see Chapter 5: Clock Generation Module (MC_CGM)) –...
Page 92: Figure 9. Spc560P40/34 System Clock Generation
Clock Description RM0046 IRC_CLK IRC_CLK RC Oscillator (IRC) 16 MHz 16 MHz SYS_CLK FMPLL_0_PCS_CLK PHI_PCS FMPLL_0 Oscillator FMPLL_0_CLK 64 MHz—50% 64 MHz (XOSC40) XOSC_CLK XOSC_CLK 8 MHz—50% 8 MHz—50% Clockout  1,  2,  4,  8 30/32 MHz Clock Out Divider IRC_CLK XOSC_CLK...
Page 93: Figure 10. Spc560P40/34 System Clock Distribution Part A
RM0046 Clock Description SafetyPort SP_CLK Module Clock XOSC_CLK Protocol Clock SP_CLK IPS @ SP_CLK IPS @ SYS_CLK eTimer_0 MC_CLK Module Clock IPS @ MC_CLK FlexPWM MC_CLK Module Clock IPS @ MC_CLK ADC_0 MC_CLK Module Clock IPS @ MC_CLK DSPI_0 Module Clock SYS_CLK DSPI_1 SYS_CLK...
Page 94: Available Clock Domains
Clock Description RM0046 SYS_CLK SYS_CLK LINFlex_0 SYS_CLK SYS_CLK Module clock Module clock LINFlex_1 ECSM SYS_CLK SYS_CLK Module clock Module clock Platform Flash Controller SYS_CLK SYS_CLK Module clock Code Flash 0 Module clock IRCOSC_CLK Protocol clock Data Flash 0 DMA Mux SIUL SYS_CLK SYS_CLK...
Page 95: Clock Selectors
RM0046 Clock Description 4.2.2 Clock selectors System clock selector 0 for SYS_CLK The system clock selector 0 selects the clock source for the system clock (SYS_CLK) from clock signals: ● Internal RC oscillator clock (IRC) ● Progressive output clock of FMPLL_0 ●...
Page 96: Alternate Module Clock Domains
Clock Description RM0046 Alternate module clock domains This section lists the different clock domains for each module. If not otherwise noted, all modules on the SPC560P40/34 device are clocked on the SYS_CLK. 4.3.1 FlexCAN clock domains The FlexCAN modules have two distinct software controlled clock domains. One of the clock domains is always derived from the system clock.
Page 97: Clock Behavior In Stop And Halt Mode
RM0046 Clock Description Safety Port clock domains The Safety Port module has two distinct software-controlled clock domains. The first clock domain (Module Clock) is always supplied from the SP_PLL_CLK. The source for the second clock domain (Protocol Clock) can either be the SP_PLL_CLK or the XOSC_CLK. The user must ensure that the frequency of the first clock domain (Module Clock) clocked from the MC_PLL_CLK is always the same or greater than the clock selected for the second clock domain (Protocol Clock).
Page 98: Irc 16 Mhz Internal Rc Oscillator (Rc_Ctl)
Clock Description RM0046 Upon the detection of one of the above mentioned failures, the SPC560P40/34 device either asserts a reset, generates an interrupt, or sends the device into the SAFE state. The reaction to each of the clock failures and system parameters (like active clocks and SYS_CLK clock source) that become active in SAFE state are under software control and can be configured in the ME module.
Page 99: Functional Description
RM0046 Clock Description Main features are: ● Oscillator clock available interrupt ● Oscillator bypass mode 4.7.1 Functional description The crystal oscillator circuit includes an internal oscillator driver and an external crystal circuitry. The XOSC provides an output clock to the PLL or it is used as a reference clock to specific modules depending on system needs.
Page 100: Frequency Modulated Phase Locked Loop (Fmpll)
Clock Description RM0046 Figure 13. Crystal Oscillator Control register (OSC_CTL) 0xC3FE_0000 Access: Supervisor read/write; User read- Address: only (Base + 0x0000) R OSC EOCV[7:0] Reset R M_ Reset Table 11. OSC_CTL field descriptions Field Description Crystal Oscillator bypass This bit specifies whether the oscillator should be bypassed or not. Software can only set this bit. System reset is needed to reset this bit.
Page 101: Overview
RM0046 Clock Description 4.8.2 Overview The FMPLL enables the generation of high speed system clocks from a common 4–40 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor and output clock divider ratio are all software configurable.
Page 102: Register Description
Clock Description RM0046 Table 12. FMPLL memory map Offset from ME_CGM_BASE Register Access Reset value Location FMPLL_0: 0xC3FE_00A0 0x0000 CR—Control Register 0x0080_0000 on page 4-102 0x0004 MR—Modulation register 0x0080_0000 on page 4-104 0x0004–0x000F Reserved 1. FMPLL_x are mapped through the ME_CGM Register Slot 4.8.5 Register description The PLL operation is controlled by two registers.
Page 103: Table 13. Cr Field Descriptions
RM0046 Clock Description Table 13. CR field descriptions Field Description Input Division Factor The value of this field sets the PLL input division factor. 0000: Divide by 1 0001: Divide by 2 0010: Divide by 3 0011: Divide by 4 0100: Divide by 5 0101: Divide by 6 0110: Divide by 7...
Page 104: Table 14. Mr Field Descriptions
Clock Description RM0046 Table 13. CR field descriptions (continued) Field Description This bit is set by hardware whenever there is a lock/unlock event.It is cleared by software, writing i_lock This bit indicates whether the PLL has acquired lock. s_lock 0: PLL unlocked 1: PLL locked This bit masks the pll_fail output.
Page 105: Functional Description
RM0046 Clock Description Table 14. MR field descriptions (continued) Field Description Modulation period The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following formula: modperiod -------------------- - MOD_PERIOD  where: fref: represents the frequency of the feedback divider fmod: represents the modulation frequency Frequency modulation enable The FM_EN bit enables the frequency modulation.
Page 106: Table 15. Progressive Clock Switching On Pll_Select Rising Edge
Clock Description RM0046 Table 15. Progressive clock switching on pll_select rising edge Number of PLL output clock cycles ck_pll_div frequency (PLL output frequency) (ck_pll_out frequency)  8 (ck_pll_out frequency)  4 (ck_pll_out frequency)  2 onward (ck_pll_out frequency) Division factors ck_pll_out ck_pll_div of 8, 4, 2, or 1...
Page 107 RM0046 Clock Description The following values show the input setting for one possible configuration of the PLL: ● PLL input frequency: 4 MHz ● Loop divider (LDF): 64 ● Input divider (IDF): 1 ● VCO frequency = 4 MHz × 64 = 256 MHz ●...
Page 108: Recommendations
Clock Description RM0046 Frequency Center Spread Down Spread 2 × md Time Figure 18. Frequency modulation depth spreads Powerdown mode To reduce consumption, the FMPLL can be switched off when not required by programming the registers ME_x_MC on the ME module. 4.8.7 Recommendations To avoid any unpredictable behavior of the PLL clock, it is recommended to follow these...
Page 109: Main Features
RM0046 Clock Description When mismatch occurs in the CMU either with the PLL monitor or the XOSC monitor, the CMU notifies the RGM, ME and the FCU (Fault Collection Unit) modules. The default behavior is such that a reset occurs and a status bit is set in the RGM. The user also has the option to change the behavior of the action by disabling the reset and selecting an alternate action.
Page 110: Functional Description
Clock Description RM0046 4.9.3 Functional description The clock and frequency names referenced in this block are defined as follows: ● CK_XOSC: clock coming from the external crystal oscillator ● CK_IRC: clock coming from the low frequency internal RC oscillator ● CK_PLL: clock coming from the PLL ●...
Page 111: Memory Map And Register Description
RM0046 Clock Description If F is greater than a reference value determined by the SYS_CLK CMU_1_HFREFR_A[HFREF_A] bits and the system clock is enabled, then: ● CMU_1_ISR[FHHI] is set ● A failure event is signaled to the MC_RGM and FCU, which in turn can generate a ‘functional' reset, a SAFE mode request, or an interrupt 4) and the system clock If F...
Page 112: Table 18. Cmu_0_Csr Field Descriptions
Clock Description RM0046 Table 17. CMU memory map (continued) Offset from CMU_BASE Register Access Reset value Location (0xC3FE_0100) Low Frequency Reference Register FMPLL_0 0x000C 0x0000_0000 on page 4-114 (CMU_0_LFREFR_A) 0x0010 Interrupt Status Register (CMU_0_ISR) 0x0000_0000 on page 4-114 0x0014 Reserved 0x0018 Measurement Duration Register (CMU_0_MDR) 0x0000_0000...
Page 113: Table 19. Cmu_0_Fdr Field Descriptions
RM0046 Clock Description Frequency Display Register (CMU_0_FDR) Figure 21. Frequency Display Register (CMU_0_FDR) Address: Base + 0x0004 Access: User read-only FD[19:16] Reset FD[15:0] Reset Table 19. CMU_0_FDR field descriptions Field Description Measured frequency bits FD[19:0] This register displays the measured frequency f with respect to f .
Page 114: Table 21. Cmu_0_Lfrefr_A Fields Descriptions
Clock Description RM0046 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) Figure 23. Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) Address: Base + 0x000C Access: User read/write Reset LFREF[11:0] Reset Table 21. CMU_0_LFREFR_A fields descriptions Field Description Low Frequency reference value LFREF_A These bits determine the low reference value for the FMPLL_0. The reference value is given by: (LFREF_A[11:0]/16) * (f /4).
Page 115: Table 23. Cmu_0_Mdr Field Descriptions
RM0046 Clock Description Table 22. CMU_0_ISR field descriptions (continued) Field Description FMPLL_0 Clock frequency higher than high reference interrupt This bit is set by hardware when CK_FMPLL_ 0 frequency becomes higher than HFREF_A value and CK_FMPLL_0 is ‘ON’ and the PLL locked as signaled by the ME. It can be cleared by software by FHHI_0 writing 1.
Page 116: Clock Generation Module (Mc_Cgm)
Clock Generation Module (MC_CGM) RM0046 Clock Generation Module (MC_CGM) Overview The clock generation module (MC_CGM) generates reference clocks for all the SoC blocks. The MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the system clock selection (see the MC_ME chapter for more details). Peripheral clock selection is controlled by MC_CGM control registers.
Page 117: Figure 26. Mc_Cgm Block Diagram
RM0046 Clock Generation Module (MC_CGM) MC_CGM 16 MHz_IRC MC_ME XOSC0 Registers Platform Interface MC_RGM PLL0 System Clock peripherals Multiplexer/Divider Auxiliary Clock PAD[22] Selector/Divider core Output Clock Selector/Divider mapped peripherals Figure 26. MC_CGM Block Diagram Doc ID 16912 Rev 5 117/936...
Page 118: Features
Clock Generation Module (MC_CGM) RM0046 Features The MC_CGM includes the following features: ● generates system and peripheral clocks ● selects and enables/disables the system clock supply from system clock sources according to MC_ME control ● contains a set of registers to control clock dividers for divided clock generation ●...
Page 119: Table 25. Mc_Cgm Memory Map
RM0046 Clock Generation Module (MC_CGM) Note: Any access to unused registers as well as write accesses to read-only registers will not change register content, and cause a transfer error. Table 25. MC_CGM Memory Map Address Name 0xC3FE _0000 … XOSC registers 0xC3FE _001C 0xC3FE...
Page 120 Clock Generation Module (MC_CGM) RM0046 Table 25. MC_CGM Memory Map (continued) Address Name 0xC3FE _0100 … CMU0 registers 0xC3FE _011C 0xC3FE _0120 … reserved 0xC3FE _013C 0xC3FE _0140 … reserved 0xC3FE _015C 0xC3FE _0160 … reserved 0xC3FE _017C 0xC3FE _0180 …...
Page 121 RM0046 Clock Generation Module (MC_CGM) Table 25. MC_CGM Memory Map (continued) Address Name 0xC3FE _0220 … reserved 0xC3FE _023C 0xC3FE _0240 … reserved 0xC3FE _025C 0xC3FE _0260 … reserved 0xC3FD _C27C 0xC3FE _0280 … reserved 0xC3FE _029C 0xC3FE _02A0 … reserved 0xC3FE _02BC...
Page 122 Clock Generation Module (MC_CGM) RM0046 Table 25. MC_CGM Memory Map (continued) Address Name 0xC3FE _0340 … reserved 0xC3FE _035C 0xC3FE _0360 … reserved 0xC3FE _036C 0xC3FE CGM_OC_EN _0370 SELDIV SELCTL 0xC3FE CGM_OCDS_ _0374 SELSTAT 0xC3FE CGM_SC_SS _0378 DIV0 0xC3FE CGM_SC_DC _037C SELCTL 0xC3FE...
Page 123: Register Descriptions
RM0046 Clock Generation Module (MC_CGM) Table 25. MC_CGM Memory Map (continued) Address Name SELCTL 0xC3FE CGM_AC1_S _0388 0xC3FE CGM_AC1_D DIV0 _038C SELCTL 0xC3FE CGM_AC2_S _0390 0xC3FE CGM_AC2_D DIV0 _0394 0xC3FE _0398 … reserved 0xC3FE _3FFC Register Descriptions All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian.
Page 124: Output Clock Enable Register (Cgm_Oc_En)
Clock Generation Module (MC_CGM) RM0046 5.5.1 Output Clock Enable Register (CGM_OC_EN) Figure 27. Output Clock Enable Register (CGM_OC_EN) Address 0xC3FE_0370 Access: User read, Supervisor read/write, Test read/write Reset Reset This register is used to enable and disable the output clock. Table 26.
Page 125: System Clock Select Status Register (Cgm_Sc_Ss)
RM0046 Clock Generation Module (MC_CGM) Table 27. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions Field Description Output Clock Division Select 00 output selected Output Clock without division SELDIV 01 output selected Output Clock divided by 2 10 output selected Output Clock divided by 4 11 output selected Output Clock divided by 8 Output Clock Source Selection Control —...
Page 126: System Clock Divider Configuration Register (Cgm_Sc_Dc0)
Clock Generation Module (MC_CGM) RM0046 Table 28. System Clock Select Status Register (CGM_SC_SS) Field Descriptions Field Description System Clock Source Selection Status — This value indicates the current source for the system clock. 0000 16 MHz int. RC osc. 0001 reserved 0010 4 MHz crystal osc.
Page 127: Auxiliary Clock 0 Select Control Register (Cgm_Ac0_Sc)
RM0046 Clock Generation Module (MC_CGM) 5.5.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Figure 31. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Address 0xC3FE_0380 Access: User read, Supervisor read/write, Test read/write SELCTL Reset Reset This register is used to select the current clock source for the following clocks: ●...
Page 128: Auxiliary Clock 0 Divider Configuration Register (Cgm_Ac0_Dc0)
Clock Generation Module (MC_CGM) RM0046 5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) Figure 32. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) Address 0xC3FE_0384 Access: User read, Supervisor read/write, Test read/write DIV0 Reset Reset This register controls the auxiliary clock 0 divider. Table 31.
Page 129: Auxiliary Clock 1 Divider Configuration Register (Cgm_Ac1_Dc0)
RM0046 Clock Generation Module (MC_CGM) Table 32. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Field Descriptions Field Description Auxiliary Clock 1 Source Selection Control — This value selects the current source for auxiliary clock 0000 (no clock) 0001 reserved 0010 reserved 0011 reserved 0100 reserved 0101 reserved...
Page 130: Auxiliary Clock 2 Select Control Register (Cgm_Ac2_Sc)
Clock Generation Module (MC_CGM) RM0046 5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) Figure 35. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) Address 0xC3FE_0390 Access: User read, Supervisor read/write, Test read/write SELCTL Reset Reset This register is used to select the current clock source for the following clocks: ●...
Page 131: Auxiliary Clock 2 Divider Configuration Register (Cgm_Ac2_Dc0)
RM0046 Clock Generation Module (MC_CGM) 5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Figure 36. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Address 0xC3FE_0394 Access: User read, Supervisor read/write, Test read/write DIV0 Reset Reset This register controls the auxiliary clock 2 divider. Table 35.
Page 132: System Clock Source Selection
Clock Generation Module (MC_CGM) RM0046 system clock is disabled if 16 MHz int. RC osc. ME_<current mode>_MC.SYSCLK = “1111” 4 MHz crystal osc. system PLL ’0’ system clock CGM_SC_DC0 Register MC_RGM SAFE mode request divided system clock 0 clock divider “0000”...
Page 133: Figure 38. Mc_Cgm Auxiliary Clock 0 Generation Overview
RM0046 Clock Generation Module (MC_CGM) (no clock) (no clock) (no clock) (no clock) (unused) (no clock) CGM_AC0_DC0 Register (unused) clock divider CGM_AC0_SC Register Figure 38. MC_CGM Auxiliary Clock 0 Generation Overview (no clock) (unused) CGM_AC1_DC0 Register (unused) clock divider CGM_AC1_SC Register Figure 39.
Page 134: Auxiliary Clock Source Selection
Clock Generation Module (MC_CGM) RM0046 (no clock) (no clock) (no clock) (no clock) (unused) (no clock) CGM_AC2_DC0 Register (unused) clock divider CGM_AC2_SC Register Figure 40. MC_CGM Auxiliary Clock 2 Generation Overview 5.8.1 Auxiliary Clock Source Selection During normal operation, the auxiliary clock selection is done via the CGM_AC0…2_SC registers.
Page 135: Output Clock Multiplexing
RM0046 Clock Generation Module (MC_CGM) 5.10 Output Clock Multiplexing The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as output clock sources. The selection is done via the CGM_OCDS_SC register. 5.11 Output Clock Division Selection 16 MHz int.
Page 136: Mode Entry Module (Mc_Me)
Mode Entry Module (MC_ME) RM0046 Mode Entry Module (MC_ME) Introduction 6.1.1 Overview The MC_ME controls the SoC mode and mode transition sequences in all functional states. It also contains configuration, control and status registers accessible for the application. Figure 42 depicts the MC_ME Block Diagram.
Page 137: Figure 42. Mc_Me Block Diagram
RM0046 Mode Entry Module (MC_ME) MC_ME VREG Flashes Registers Platform Interface MC_RGM 16 MHz_IRC XOSC0 MC_CGM PLL0 core Device Mode State Machine peripherals WKPU Figure 42. MC_ME Block Diagram Doc ID 16912 Rev 5 137/936...
Page 138: Features
Mode Entry Module (MC_ME) RM0046 6.1.2 Features The MC_ME includes the following features: ● control of the available modes by the ME_ME register ● definition of various device mode configurations by the ME_<mode>_MC registers ● control of the actual device mode by the ME_MCTL register ●...
Page 139: External Signal Description
RM0046 Mode Entry Module (MC_ME) Table 36. MC_ME Mode Descriptions (continued) Name Description Entry Exit These are software running modes where most processing software request system reset activity is done. These various run modes allow to enable from DRUN or assertion, SAFE different clock &...
Page 140 Mode Entry Module (MC_ME) RM0046 Table 37. MC_ME Register Description (continued) Access Address Name Description Size Location User Supervisor Test 0xC3FD ME_IS Interrupt Status word read read/write read/write on page 6-152 _C00C 0xC3FD ME_IM Interrupt Mask word read read/write read/write on page 6-153 _C010 0xC3FD...
Page 141 RM0046 Mode Entry Module (MC_ME) Table 37. MC_ME Register Description (continued) Access Address Name Description Size Location User Supervisor Test 0xC3FD Run Peripheral ME_RUN_PC7 word read read/write read/write on page 6-166 _C09C Configuration 7 0xC3FD Low-Power Peripheral ME_LP_PC0 word read read/write read/write on page 6-167...
Page 142: Table 38. Mc_Me Memory Map
Mode Entry Module (MC_ME) RM0046 Table 38. MC_ME Memory Map Address Name 0xC3FD ME_GS R S_CURRENT_MODE S_DFLA S_CFLA _C000 S_SYSCLK TARGET_MODE 0xC3FD ME_MCTL _C004 0xC3FD ME_ME _C008 0xC3FD ME_IS _C00C w1c w1c w1c w1c 0xC3FD ME_IM _C010 0xC3FD ME_IMTS _C014 w1c w1c w1c w1c w1c 142/936 Doc ID 16912 Rev 5...
Page 143 RM0046 Mode Entry Module (MC_ME) Table 38. MC_ME Memory Map (continued) Address Name PREVIOUS_MODE 0xC3FD ME_DMTS _C018 0xC3FD reserved _C01C DFLAON CFLAON 0xC3FD ME_RESET_ _C020 SYSCLK DFLAON CFLAON SYSCLK Doc ID 16912 Rev 5 143/936...
Page 144 Mode Entry Module (MC_ME) RM0046 Table 38. MC_ME Memory Map (continued) Address Name DFLAON CFLAON 0xC3FD ME_SAFE_M _C028 SYSCLK 0xC3FD ME_DRUN_M DFLAON CFLAON _C02C SYSCLK 0xC3FD _C030 ME_RUN0…3 … DFLAON CFLAON 0xC3FD _C03C SYSCLK 0xC3FD ME_HALT0_ DFLAON CFLAON _C040 SYSCLK 144/936 Doc ID 16912 Rev 5...
Page 145 RM0046 Mode Entry Module (MC_ME) Table 38. MC_ME Memory Map (continued) Address Name 0xC3FD reserved _C044 0xC3FD ME_STOP0_ DFLAON CFLAON _C048 SYSCLK 0xC3FD _C04C … reserved 0xC3FD _C05C 0xC3FD ME_PS0 _C060 0xC3FD ME_PS1 _C064 Doc ID 16912 Rev 5 145/936...
Page 146: Register Description
Mode Entry Module (MC_ME) RM0046 Table 38. MC_ME Memory Map (continued) Address Name 0xC3FD ME_PS2 _C068 0xC3FD reserved _C06C 0xC3FD reserved _C070 0xC3FD _C074 … reserved 0xC3FD _C07C 0xC3FD _C080 ME_RUN_PC … 0…7 0xC3FD _C09C 0xC3FD _C0A0 ME_LP_PC0 … …7 0xC3FD _C0BC 0xC3FD...
Page 147: Table 39. Global Status Register (Me_Gs) Field Descriptions
RM0046 Mode Entry Module (MC_ME) Global Status Register (ME_GS) Figure 43. Global Status Register (ME_GS) Address 0xC3FD_C000 Access: User read, Supervisor read, Test read S_CURRENT_MODE S_DFLA S_CFLA Reset S_SYSCLK Reset This register contains global mode status. Table 39. Global Status Register (ME_GS) Field Descriptions Field Description Current device mode status...
Page 148 Mode Entry Module (MC_ME) RM0046 Table 39. Global Status Register (ME_GS) Field Descriptions (continued) Field Description Output power-down status — This bit specifies output power-down status of I/Os. This bit is asserted whenever outputs of pads are forced to high impedance state or the pads power sequence driver is switched off.
Page 149: Figure 44. Mode Control Register (Me_Mctl)
RM0046 Mode Entry Module (MC_ME) Mode Control Register (ME_MCTL) Figure 44. Mode Control Register (ME_MCTL) Address 0xC3FD_C004 Access: User read, Supervisor read/write, Test read/write TARGET_MODE Reset Reset This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to ME_<mode>_MC registers must respect this for successful mode requests.
Page 150: Table 40. Mode Control Register (Me_Mctl) Field Descriptions
Mode Entry Module (MC_ME) RM0046 Table 40. Mode Control Register (ME_MCTL) Field Descriptions Field Description Target device mode — These bits provide the target device mode to be entered by software programming. The mechanism to enter into any mode by software requires the write operation twice: first time with key, and second time with inverted key.
Page 151: Table 41. Mode Enable Register (Me_Me) Field Descriptions
RM0046 Mode Entry Module (MC_ME) Table 41. Mode Enable Register (ME_ME) Field Descriptions Field Description STOP0 mode enable STOP0 0 STOP0 mode is disabled 1 STOP0 mode is enabled HALT0 mode enable HALT0 0 HALT0 mode is disabled 1 HALT0 mode is enabled RUN3 mode enable RUN3 0 RUN3 mode is disabled...
Page 152: Table 42. Interrupt Status Register (Me_Is) Field Descriptions
Mode Entry Module (MC_ME) RM0046 Interrupt Status Register (ME_IS) Figure 46. Interrupt Status Register (ME_IS) Address 0xC3FD_C00C Access: User read, Supervisor read/write, Test read/write Reset Reset This register provides the current interrupt status. Table 42. Interrupt Status Register (ME_IS) Field Descriptions Field Description Invalid mode configuration interrupt —...
Page 153: Table 43. Interrupt Mask Register (Me_Im) Field Descriptions
RM0046 Mode Entry Module (MC_ME) Interrupt Mask Register (ME_IM) Figure 47. Interrupt Mask Register (ME_IM) Address 0xC3FD_C010 Access: User read, Supervisor read/write, Test read/write Reset Reset This register controls whether an event generates an interrupt or not. Table 43. Interrupt Mask Register (ME_IM) Field Descriptions Field Description Invalid mode configuration interrupt mask...
Page 154: Table 44. Invalid Mode Transition Status Register (Me_Imts) Field Descriptions
Mode Entry Module (MC_ME) RM0046 Invalid Mode Transition Status Register (ME_IMTS) Figure 48. Invalid Mode Transition Status Register (ME_IMTS) Address 0xC3FD_C014 Access: User read, Supervisor read/write, Test read/write Reset Reset This register provides the status bits for the possible causes of an invalid mode interrupt. Table 44.
Page 155: Figure 49. Debug Mode Transition Status Register (Me_Dmts)
RM0046 Mode Entry Module (MC_ME) Debug Mode Transition Status Register (ME_DMTS) Figure 49. Debug Mode Transition Status Register (ME_DMTS) Address 0xC3FD_C018 Access: User read, Supervisor read/write, Test read/write PREVIOUS_MODE Reset Reset This register provides the status of different factors which influence mode transitions. It is used to give an indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking longer than expected.
Page 156: Table 45. Debug Mode Transition Status Register (Me_Dmts) Field Descriptions
Mode Entry Module (MC_ME) RM0046 Table 45. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions Field Description Previous device mode — These bits show the mode in which the device was prior to the latest change to the current mode. 0000 RESET 0001 TEST 0010 SAFE...
Page 157 RM0046 Mode Entry Module (MC_ME) Table 45. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued) Field Description 16 MHz_IRC State Change during mode transition indicator — This bit is set when the 16 MHz internal RC oscillator is requested to change its power up/down state. It is cleared when the 16 MHz internal RC oscillator has completed its state change.
Page 158: Figure 50. Reset Mode Configuration Register (Me_Reset_Mc)
Mode Entry Module (MC_ME) RM0046 RESET Mode Configuration Register (ME_RESET_MC) Figure 50. RESET Mode Configuration Register (ME_RESET_MC) Address 0xC3FD_C020 Access: User read, Supervisor read/write, Test read/write DFLAON CFLAON Reset SYSCLK Reset This register configures system behavior during RESET mode. Please refer to Table 46 details.
Page 159: Figure 52. Safe Mode Configuration Register (Me_Safe_Mc)
RM0046 Mode Entry Module (MC_ME) This register configures system behavior during TEST mode. Please refer to Table 46 details. Note: Byte write accesses are not allowed to this register. SAFE Mode Configuration Register (ME_SAFE_MC) Figure 52. SAFE Mode Configuration Register (ME_SAFE_MC) Address 0xC3FD_C028 Access: User read, Supervisor read/write, Test read/write DFLAON...
Page 160: Figure 53. Drun Mode Configuration Register (Me_Drun_Mc)
Mode Entry Module (MC_ME) RM0046 DRUN Mode Configuration Register (ME_DRUN_MC) Figure 53. DRUN Mode Configuration Register (ME_DRUN_MC) Address 0xC3FD_C02C Access: User read, Supervisor read/write, Test read/write DFLAON CFLAON Reset SYSCLK Reset This register configures system behavior during DRUN mode. Please refer to Table 46 details.
Page 161: Figure 54. Run0
RM0046 Mode Entry Module (MC_ME) … RUN0…3 Mode Configuration Registers (ME_RUN0 3_MC) Figure 54. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) Address 0xC3FD_C030 - 0xC3FD_C03C Access: User read, Supervisor read/write, Test read/write DFLAON CFLAON Reset SYSCLK Reset This register configures system behavior during RUN0…3 modes. Please refer to Table 46 for details.
Page 162: Table 46. Mode Configuration Registers (Me__Mc) Field Descriptions
Mode Entry Module (MC_ME) RM0046 This register configures system behavior during HALT0 mode. Please refer to Table 46 details. Note: Byte write accesses are not allowed to this register. Note: The reset value of the DFLAON field in the ME_HALT0_MC register is “10”. This reset value is illegal for the data flash.
Page 163 RM0046 Mode Entry Module (MC_ME) Table 46. Mode Configuration Registers (ME_<mode>_MC) Field Descriptions (continued) Field Description DFLAON Data flash power-down control — This bit specifies the operating mode of the data flash after entering this mode. 00 reserved 01 Data flash is in power-down mode 10 reserved 11 Data flash is in normal mode CFLAON...
Page 164: Figure 58. Peripheral Status Register 1 (Me_Ps1)
Mode Entry Module (MC_ME) RM0046 Peripheral Status Register 0 (ME_PS0) Figure 57. Peripheral Status Register 0 (ME_PS0) Address 0xC3FD_C060 Access: User read, Supervisor read, Test read Reset Reset This register provides the status of the peripherals. Please refer to Table 47 for details.
Page 165: Table 47. Peripheral Status Registers 0
RM0046 Mode Entry Module (MC_ME) This register provides the status of the peripherals. Please refer to Table 47 for details. Peripheral Status Register 2 (ME_PS2) Figure 59. Peripheral Status Register 2 (ME_PS2) Address 0xC3FD_C068 Access: User read, Supervisor read, Test read Reset Reset This register provides the status of the peripherals.
Page 166: Table 48. Run Peripheral Configuration Registers (Me_Run_Pc0
Mode Entry Module (MC_ME) RM0046 … Run Peripheral Configuration Registers (ME_RUN_PC0 Figure 60. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Address 0xC3FD_C080 - 0xC3FD_C09C Access: User read, Supervisor read/write, Test read/write Reset Reset These registers configure eight different types of peripheral behavior during run modes. Table 48.
Page 167: Table 49. Low-Power Peripheral Configuration Registers (Me_Lp_Pc0
RM0046 Mode Entry Module (MC_ME) … Low-Power Peripheral Configuration Registers (ME_LP_PC0 Figure 61. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Address 0xC3FD_C0A0 - 0xC3FD_C0BC Access: User read, Supervisor read/write, Test read/write Reset Reset These registers configure eight different types of peripheral behavior during non-run modes. Table 49.
Page 168: Functional Description
Mode Entry Module (MC_ME) RM0046 Table 50. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions Field Description Peripheral control in debug mode — This bit controls the state of the peripheral in debug mode 0 Peripheral state depends on RUN_CFG/LP_CFG bits and the device mode 1 Peripheral is frozen if not already frozen in device modes.
Page 169: Modes Details
RM0046 Mode Entry Module (MC_ME) Any modification of the mode configuration register of the currently selected mode will not be taken into account immediately but on the next request to enter this mode. This means that transition requests such as RUN0…3 Æ RUN0…3, DRUN Æ DRUN, SAFE Æ SAFE, and TEST Æ...
Page 170 Mode Entry Module (MC_ME) RM0046 ME_RESET_MC register. This mode has a pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock. DRUN Mode The device enters this mode on the following events: ● automatically from RESET mode after completion of the reset sequence ●...
Page 171 RM0046 Mode Entry Module (MC_ME) If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the PDO bit of the ME_SAFE_MC register should be set. The input levels remain unchanged. TEST Mode The device enters this mode on the following events: ●...
Page 172: Mode Transition Process
Mode Entry Module (MC_ME) RM0046 SAFE (on SAFE mode request), or DRUN (on reset), and an invalid mode interrupt is not generated. This mode is intended as a first-level low-power mode with ● the core clock frozen ● only a few peripherals running and to be used by software ●...
Page 173: Table 51. Mc_Me Resource Control Overview
RM0046 Mode Entry Module (MC_ME) defined rules to initiate the process. If the request fails to satisfy these rules, it is ignored, and the TARGET_MODE bit field is not updated. An optional interrupt can be generated for invalid mode requests. Refer to Section 6.4.5, “Mode Transition Interrupts for details.
Page 174 Mode Entry Module (MC_ME) RM0046 Table 51. MC_ME Resource Control Overview (continued) Mode Resource RESET TEST SAFE DRUN RUN0…3 HALT0 STOP0    Peripheral Clocks Disable On completion of the Target Mode Request step, the MC_ME requests each peripheral to enter its stop mode when: ●...
Page 175 RM0046 Mode Entry Module (MC_ME) The clocks to the processor and system memory are unaffected while transitioning between software running modes such as DRUN, RUN0…3, and SAFE. Warning: Clocks to the whole device including the processor and system memory can be disabled in TEST mode. Clock Sources Switch-On On completion of the Processor Low-Power Mode Entry...
Page 176 Mode Entry Module (MC_ME) RM0046 Peripheral Clocks Enable Based on the current and target device modes, the peripheral configuration registers ME_RUN_PC0…7, ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143, the MC_ME enables the clocks for selected modules as required. This step is executed only after the process is completed.
Page 177: Table 52. Mc_Me System Clock Selection Overview
RM0046 Mode Entry Module (MC_ME) Table 52. MC_ME System Clock Selection Overview System Mode Clock RESET TEST SAFE DRUN RUN0…3 HALT0 STOP0 Source 16 MHz        int. RC (default) (default) (default) (default) (default) (default) (default) osc.
Page 178 Mode Entry Module (MC_ME) RM0046 Flash Switch-Off Based on the CFLAON and DFLAON bit fields of the ME_<current mode>_MC and ME_<target mode>_MC registers, if any of the flashes is to be put in its low-power or power- down mode, the MC_ME requests the flash to enter the corresponding power mode and waits for the flash to acknowledge.
Page 179: Figure 64. Mc_Me Transition Diagram
RM0046 Mode Entry Module (MC_ME) Start Write ME_MCTL register Target Mode Request SAFE mode request interrupt/wakeup event Clock Sources Switch-On FLASH Outputs On Switch-On Peripheral Clocks Disable Processor & Memory Clock Enable Processor Low-Power Peripheral Clocks Entry Enable Processor System Clock Low-Power Switching Exit...
Page 180: Protection Of Mode Configuration Registers
Mode Entry Module (MC_ME) RM0046 6.4.4 Protection of Mode Configuration Registers While programming the mode configuration registers ME_<mode>_MC, the following rules must be respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be generated. ● If the 16 MHz int.
Page 181 RM0046 Mode Entry Module (MC_ME) ME_IMTS register is set. This condition is detected regardless of whether the proper key mechanism is followed while writing the ME_MCTL register. ● If some of the device modes are disabled as programmed in the ME_ME register, their respective configurations are considered reserved, and any access to the ME_MCTL register with those values results in an invalid mode transition request.
Page 182: Peripheral Clock Gating
Mode Entry Module (MC_ME) RM0046 pending bit is not set when the SAFE mode is entered by a software request (i.e., programming of ME_MCTL register). Mode Transition Complete interrupt Whenever the system fully completes a mode transition (i.e., the S_MTRANS bit of ME_GS register transits from ‘1’...
Page 183: Figure 65. Mc_Me Application Example Flow Diagram
RM0046 Mode Entry Module (MC_ME) START of mode change config for target mode okay? write ME_<target mode>_MC, ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers write ME_MCTL with target mode and key write ME_MCTL with target mode and inverted key start timer S_MTRANS cleared? timer expired?
Page 184: Power Control Unit (Mc_Pcu)
Power Control Unit (MC_PCU) RM0046 Power Control Unit (MC_PCU) Introduction 7.1.1 Overview The power control unit (MC_PCU) acts as a bridge for mapping the PMU peripheral to the MC_PCU address space. Figure 66 depicts the MC_PCU block diagram. MC_PCU Registers Platform Interface core mapped...
Page 185: External Signal Description
RM0046 Power Control Unit (MC_PCU) External Signal Description The MC_PCU has no connections to any external pins. Memory Map and Register Definition 7.3.1 Memory Map Table 53. MC_PCU Register Description Access Address Name Description Size Location User Supervisor Test 0xC3FE PCU_PSTAT Power Domain Status Register word read...
Page 186: Register Descriptions
Power Control Unit (MC_PCU) RM0046 7.3.2 Register Descriptions All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the PD0 field of the PCU_PSTAT register may be accessed as a word at address 0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address 0xC3FE_8043.
Page 187: Reset Generation Module (Mc_Rgm)
RM0046 Reset Generation Module (MC_RGM) Reset Generation Module (MC_RGM) Introduction 8.1.1 Overview The reset generation module (MC_RGM) centralizes the different reset sources and manages the reset sequence of the device. It provides a register interface and the reset sequencer. Various registers are available to monitor and control the device reset sequence. The reset sequencer is a state machine which controls the different phases (PHASE0, PHASE1, PHASE2, PHASE3, and IDLE) of the reset sequence and controls the reset signals generated in the system.
Page 188: Figure 68. Mc_Rgm Block Diagram
Reset Generation Module (MC_RGM) RM0046 MC_RGM power-on MC_ME 1.2V low-voltage detected software watchdog timer 2.7V low-voltage detected Registers (VREG) 2.7V low-voltage detected Platform Interface MC_CGM (flash) 2.7V low-voltage detected (I/O) peripherals Reset RESET_B State Machine JTAG initiated reset core core reset software reset checkstop reset PLL0 fail...
Page 189: Features
RM0046 Reset Generation Module (MC_RGM) 8.1.2 Features The MC_RGM contains the functionality for the following features: ● ‘destructive’ resets management ● ‘functional’ resets management ● signalling of reset events after each reset sequence (reset status flags) ● conversion of reset events to SAFE mode or interrupt request events ●...
Page 190: External Signal Description
Reset Generation Module (MC_RGM) RM0046 phase completion gates from either the system or internal to the MC_RGM are acknowledged. The device reset associated with the phase is then released, and the state machine proceeds to the next phase up to entering the IDLE phase. During this entire process, the MC_ME state machine is held in RESET mode.
Page 191: Table 57. Mc_Rgm Memory Map
RM0046 Reset Generation Module (MC_RGM) Table 57. MC_RGM Memory Map Address Name RGM_ FES / 0xC3FE _4000 RGM_ W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c W w1c w1c w1c w1c RGM_ FERD / 0xC3FE _4004 RGM_ DERD 0xC3FE...
Page 192: Register Descriptions
Reset Generation Module (MC_RGM) RM0046 Table 57. MC_RGM Memory Map (continued) Address Name 0xC3FE RGM_ _4018 FESS 0xC3FE RGM_ _401C FBRE 0xC3FE _4020 … reserved 0xC3FE _7FFC 8.3.1 Register Descriptions Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes.
Page 193: Table 58. Functional Event Status Register (Rgm_Fes) Field Descriptions
RM0046 Reset Generation Module (MC_RGM) This register contains the status of the last asserted functional reset sources. It can be accessed in read/write on either supervisor mode or test mode. Register bits are cleared on write ‘1’. Table 58. Functional Event Status Register (RGM_FES) Field Descriptions Field Description Flag for External Reset...
Page 194: Table 59. Destructive Event Status Register (Rgm_Des) Field Descriptions
Reset Generation Module (MC_RGM) RM0046 Table 58. Functional Event Status Register (RGM_FES) Field Descriptions (continued) Field Description Flag for core reset F_CORE 0 No core reset event has occurred since either the last clear or the last destructive reset assertion 1 A core reset event has occurred Flag for JTAG initiated reset 0 No JTAG initiated reset event has occurred since either the last clear or the last destructive reset...
Page 195 RM0046 Reset Generation Module (MC_RGM) Table 59. Destructive Event Status Register (RGM_DES) Field Descriptions (continued) Field Description Flag for 2.7V low-voltage detected (VREG) 0 No 2.7V low-voltage detected (VREG) event has occurred since either the last clear or the last F_LVD27_VREG power-on reset assertion 1 A 2.7V low-voltage detected (VREG) event has occurred...
Page 196: Table 60. Functional Event Reset Disable Register (Rgm_Ferd) Field Descriptions
Reset Generation Module (MC_RGM) RM0046 Table 60. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions Field Description Disable External Reset D_EXR 0 An external reset event triggers a reset sequence Disable PLL1 fail 0 A PLL1 fail event triggers a reset sequence D_PLL1 1 A PLL1 fail event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_PLL1...
Page 197: Table 61. Destructive Event Reset Disable Register (Rgm_Derd) Field Descriptions
RM0046 Reset Generation Module (MC_RGM) Destructive Event Reset Disable Register (RGM_DERD) Figure 72. Destructive Event Reset Disable Register (RGM_DERD) Address 0xC3FE_4006 Access: User read, Supervisor read, Test read This register provides dedicated bits to disable particular destructive reset sources. It can be accessed in read-only in supervisor mode, test mode, and user mode.
Page 198: Table 62. Functional Event Alternate Request Register (Rgm_Fear) Field Descriptions
Reset Generation Module (MC_RGM) RM0046 Functional Event Alternate Request Register (RGM_FEAR) Figure 73. Functional Event Alternate Request Register (RGM_FEAR) Address 0xC3FE_4010 Access: User read, Supervisor read/write, Test read/write This register defines an alternate request to be generated when a reset on a functional event has been disabled.
Page 199: Table 63. Functional Event Short Sequence Register (Rgm_Fess) Field Descriptions
RM0046 Reset Generation Module (MC_RGM) Functional Event Short Sequence Register (RGM_FESS) Figure 74. Functional Event Short Sequence Register (RGM_FESS) Address 0xC3FE_4018 Access: User read, Supervisor read/write, Test read/write This register defines which reset sequence will be done when a functional reset sequence is triggered.
Page 200: Figure 75. Functional Bidirectional Reset Enable Register (Rgm_Fbre)
Reset Generation Module (MC_RGM) RM0046 Table 63. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions Field Description Short Sequence for PLL0 fail 0 The reset sequence triggered by a PLL0 fail event will start from PHASE1 SS_PLL0 1 The reset sequence triggered by a PLL0 fail event will start from PHASE3, skipping PHASE1 and PHASE2 Short Sequence for checkstop reset SS_CHKSTOP...
Page 201: Table 64. Functional Bidirectional Reset Enable Register (Rgm_Fbre) Field Descriptions
RM0046 Reset Generation Module (MC_RGM) Table 64. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions Field Description Bidirectional Reset Enable for External Reset BE_EXR 0RESET_B is asserted on an external reset event if the reset is enabled 1RESET_B is not asserted on an external reset event Bidirectional Reset Enable for PLL1 fail BE_PLL1 0RESET_B is asserted on a PLL1 fail event if the reset is enabled...
Page 202: Functional Description
Reset Generation Module (MC_RGM) RM0046 Functional Description 8.4.1 Reset State Machine The main role of MC_RGM is the generation of the reset sequence which ensures that the correct parts of the device are reset based on the reset source event. This is summarized in Table Table 65.
Page 203: Figure 76. Mc_Rgm State Machine
RM0046 Reset Generation Module (MC_RGM) power-on or enabled ‘destructive’ reset PHASE0 duration  3 16 MHz internal RC oscillator clock cycles 16 MHz IRC stable, VREG voltage okay done enabled non- shortened external or ‘functional’ PHASE1 reset duration  350 16 MHz internal RC oscillator clock cycles PHASE2 enabled shortened...
Page 204: Destructive Resets
Reset Generation Module (MC_RGM) RM0046 PHASE0 Phase This phase is entered immediately from any phase on a power-on or enabled ‘destructive’ reset event. The reset state machine exits PHASE0 and enters PHASE1 on verification of the following: ● all enabled ‘destructive’ resets have been processed ●...
Page 205: External Reset
RM0046 Reset Generation Module (MC_RGM) The status flag associated with a given ‘destructive’ reset event (RGM_DES.F_<destructive reset> bit) is set when the ‘destructive’ reset is asserted and the power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is the most critical for the application.
Page 206: Alternate Event Generation
Reset Generation Module (MC_RGM) RM0046 The ‘functional’ reset can be optionally disabled by software writing bit RGM_FERD.D_<functional reset>. Note: The RGM_FERD register can be written only once between two power-on reset events. An enabled functional reset will normally trigger a reset sequence starting from the beginning of PHASE1.
Page 207 RM0046 Reset Generation Module (MC_RGM) Note: RESET_B can be low as a consequence of the internal reset generation. This will force re- sampling of the boot mode pins. (See Table 65 for details.) Doc ID 16912 Rev 5 207/936...
Page 208: Interrupt Controller (Intc)
Interrupt Controller (INTC) RM0046 Interrupt Controller (INTC) Introduction The INTC provides priority-based preemptive scheduling of interrupt service requests (ISRs). This scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC supports 128 interrupt requests. It is targeted to work with Power Architecture technology and automotive applications where the ISRs nest to multiple levels, but it also can be used with other processors and applications.For high-priority interrupt requests in these target applications, the time from the assertion of the peripheral’s interrupt request to...
Page 209: Table 67. Interrupt Sources Available
RM0046 Interrupt Controller (INTC) Table 67. Interrupt sources available Interrupt sources (128) Number available Software ECSM eDMA2x SIUL MC_ME MC_RGM XOSC FlexCAN eTimer FlexPWM Safety Port DSPI LINFlex Doc ID 16912 Rev 5 209/936...
Page 210: Block Diagram
Interrupt Controller (INTC) RM0046 Block diagram Figure 77 shows a block diagram of the interrupt controller (INTC). Software Module Priority Set/Clear Hardware Select Configuration Interrupt Vector Enable Register Registers Registers End of Interrupt Vector Table Highest Lowest Register Entry Size 4-bits Priority Vector...
Page 211 RM0046 Interrupt Controller (INTC) INC_IACKR. Reading the INTC_IACKR negates the interrupt request to the associated processor. Even if a higher priority interrupt request arrived while waiting for this interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. The reading also pushes the PRI value in INTC_CPR onto the associated LIFO and updates PRI in the associated INTC_CPR with the new priority.
Page 212: Memory Map And Registers Description
Interrupt Controller (INTC) RM0046 Memory map and registers description 9.5.1 Module memory map Table 68 shows the INTC memory map. Table 68. INTC memory map Offset from INTC_BASE Register Location 0xFFF4_8000 0x0000 INTC Module Configuration Register (INTC_MCR) on page 9-213 0x0004 Reserved 0x0008...
Page 213: Table 69. Intc_Mcr Field Descriptions
RM0046 Interrupt Controller (INTC) INTC Module Configuration Register (INTC_MCR) The module configuration register configures options of the INTC. Figure 78. INTC Module Configuration Register (INTC_MCR) Address: Base + 0x0000 Access: User read/write Reset VTES HVEN Reset Table 69. INTC_MCR field descriptions Field Description Vector table entry size...
Page 214: Table 70. Intc_Cpr Field Descriptions
Interrupt Controller (INTC) RM0046 Table 70. INTC_CPR field descriptions Field Description Priority PRI is the priority of the currently executing ISR according to the following: 1111 Priority 15—highest priority 1110 Priority 14 1101 Priority 13 1100 Priority 12 1011 Priority 11 1010 Priority 10 28–31 1001 Priority 9...
Page 215: Table 71. Intc_Iackr Field Descriptions
RM0046 Interrupt Controller (INTC) INTC Interrupt Acknowledge Register(INTC_IACKR) Figure 80. INTC Interrupt Acknowledge Register (INTC_IACKR) Address Base + 0x0010 Access: User read/write VTBA (most significant 16 bits) Reset INTVEC VTBA (least significant 5 bits) Reset 1. When the VTES bit in INTC_MCR is asserted, INTVEC is shifted to the left one bit. Bit 29 is read as a ‘0’. VTBA is narrowed to 20 bits in width.
Page 216: Figure 81. Intc End-Of-Interrupt Register (Intc_Eoir)
Interrupt Controller (INTC) RM0046 INTC End-of-Interrupt Register (INTC_EOIR) Figure 81. INTC End-of-Interrupt Register (INTC_EOIR) Address Base + 0x0018 Access: Write-only Reset Reset Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR.
Page 217: Table 72. Intc_Sscir[0:7] Field Descriptions
RM0046 Interrupt Controller (INTC) Figure 83. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7]) Address Base + 0x0024 Access: User read/write SET4 SET5 Reset SET6 SET7 Reset Table 72. INTC_SSCIR[0:7] field descriptions Field Description Set Flag Bits 6, 14, 22, 30 Writing a ‘1’...
Page 218: Table 73. Intc_Psr0_3-Intc_Psr220-221 Field Descriptions
Interrupt Controller (INTC) RM0046 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) Figure 84. INTC Priority Select Register 0–3 (INTC_PSR[0:3]) Address Base + 0x0040 Access: User read/write PRI0 PRI1 Reset PRI2 PRI3 Reset Figure 85. INTC Priority Select Register 220–221 (INTC_PSR[220:221]) Address Base + 0x011C Access: User read/write PRI220 PRI221...
Page 219 RM0046 Interrupt Controller (INTC) Table 74. INTC Priority Select Register address offsets (continued) INTC_PSRx_x Offset Address INTC_PSRx_x Offset Address INTC_PSR28_31 0x005C INTC_PSR140_143 0x00CC INTC_PSR32_35 0x0060 INTC_PSR144_147 0x00D0 INTC_PSR36_39 0x0064 INTC_PSR148_151 0x00D4 INTC_PSR40_43 0x0068 INTC_PSR152_155 0x00D8 INTC_PSR44_47 0x006C INTC_PSR156_159 0x00DC INTC_PSR48_51 0x0070 INTC_PSR160_163 0x00E0...
Page 220: Functional Description
Interrupt Controller (INTC) RM0046 Functional description The functional description involves the areas of interrupt request sources, priority management, and handshaking with the processor. Note: The INTC has no spurious vector support. Therefore, if an asserted peripheral or software settable interrupt request, whose PRIn value in INTC_PSR0–INTC_PSR221 is higher than the PRI value in INTC_CPR, negates before the interrupt request to the processor for that peripheral or software settable interrupt request is acknowledged, the interrupt request to the processor still can assert or will remain asserted for that peripheral or software settable...
Page 221 RM0046 Interrupt Controller (INTC) Table 75. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0830 Channel 1 DMA2x 0x0834 Channel 2 DMA2x 0x0838 Channel 3 DMA2x 0x083C Channel 4 DMA2x 0x0840 Channel 5 DMA2x 0x0844 Channel 6 DMA2x 0x0848 Channel 7 DMA2x 0x084C...
Page 222 Interrupt Controller (INTC) RM0046 Table 75. Interrupt vector table (continued) IRQ # Offset Interrupt Module SIUL 0x08A4 SIU External IRQ_0 SIUL 0x08A8 SIU External IRQ_1 SIUL 0x08AC SIU External IRQ_2 SIUL 0x08B0 SIU External IRQ_3 SIUL 0x08B4 Reserved 0x08B8 Reserved 0x08BC Reserved 0x08C0...
Page 223 RM0046 Interrupt Controller (INTC) Table 75. Interrupt vector table (continued) IRQ # Offset Interrupt Module FLEXCAN_ESR_BOFF | 0x0908 FLEXCAN_Transmit_Warning | FlexCAN_0 FLEXCAN_Receive_Warning 0x090C FLEXCAN_ESR_WAK FlexCAN_0 0x0910 FLEXCAN_BUF_00_03 FlexCAN_0 0x0914 FLEXCAN_BUF_04_07 FlexCAN_0 0x0918 FLEXCAN_BUF_08_11 FlexCAN_0 0x091C FLEXCAN_BUF_12_15 FlexCAN_0 0x0920 FLEXCAN_BUF_16_31 FlexCAN_0 0x0924 Reserved DSPI0...
Page 224 Interrupt Controller (INTC) RM0046 Table 75. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0974 Reserved DSPI1 DSPI_SR[TFUF] 0x0978 DSPI_1 DSPI_SR[RFOF] 0x097C DSPI_SR[EOQF] DSPI_1 0x0980 DSPI_SR[TFFF] DSPI_1 0x0984 DSPI_SR[TCF] DSPI_1 0x0988 DSPI_SR[RFDF] DSPI_1 LINFlex1 0x098C LINFlex_RXI LINFlex_1 0x0990 LINFlex_TXI LINFlex_1 0x0994 LINFlex_ERR...
Page 225 RM0046 Interrupt Controller (INTC) Table 75. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x09E8 Reserved 0x09EC Reserved 0x09F0 Reserved 0x09F4 Reserved 0x09F8 Reserved 0x09FC PITimer Channel 3 0x0A00 Reserved 0x0A04 Reserved 0x0A08 Reserved 0x0A0C Reserved 0x0A10 Reserved 0x0A14 Reserved 0x0A18 Reserved...
Page 226 Interrupt Controller (INTC) RM0046 Table 75. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0A6C Reserved 0x0A70 Reserved eTimer 0x0A74 TC0IR eTimer_0 0x0A78 TC1IR eTimer_0 0x0A7C TC2IR eTimer_0 0x0A80 TC3IR eTimer_0 0x0A84 TC4IR eTimer_0 0x0A88 TC5IR eTimer_0 0x0A8C Reserved 0x0A90 Reserved 0x0A94...
Page 227 RM0046 Interrupt Controller (INTC) Table 75. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0AEC Reserved 0x0AF0 FlexPWM_0 0x0AF4 COF3 FlexPWM_0 0x0AF8 Reserved 0x0AFC FFLAG FlexPWM_0 0x0B00 FlexPWM_0 0x0B04 MRS_I CTU_0 0x0B08 T0_I CTU_0 0x0B0C T1_I CTU_0 0x0B10 T2_I CTU_0 0x0B14 T3_I...
Page 228: Interrupt Request Sources
Interrupt Controller (INTC) RM0046 Table 75. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0B68 Reserved 0x0B6C Reserved 0x0B70 Reserved 0x0B74 Reserved 9.6.1 Interrupt request sources The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt requests can assert on any clock cycle.
Page 229 RM0046 Interrupt Controller (INTC) any asserted peripheral or software configurable interrupt request is higher than the current priority for a given processor, then the interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or software settable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware vector mode, for the interrupt vector provided to the processor.
Page 230: Handshaking With Processor
Interrupt Controller (INTC) RM0046 However, the LIFO is only 14 entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities first pushed are overwritten.
Page 231: Figure 86. Software Vector Mode Handshaking Timing Diagram
RM0046 Interrupt Controller (INTC) Clock Interrupt request to processor Hardware vector enable Interrupt vector Interrupt acknowledge Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR PRI in INTC_CPR Peripheral interrupt request 100 Figure 86. Software vector mode handshaking timing diagram Hardware vector mode handshaking A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown Figure...
Page 232: Initialization/Application Information
Interrupt Controller (INTC) RM0046 Clock Interrupt request to processor Hardware vector enable Interrupt vector Interrupt acknowledge Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR PRI in INTC_CPR Peripheral interrupt request 100 Figure 87. Hardware vector mode handshaking timing diagram Initialization/application information 9.7.1 Initialization flow After exiting reset, all of the PRIn fields in INTC Priority Select Registers (INTC_PSR0_3–...
Page 233 RM0046 Interrupt Controller (INTC) Software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save SRR0 and SRR1 r3,INTC_IACKR@ha # form adjusted upper half of INTC_IACKR address r3,INTC_IACKR@l(r3) # load INTC_IACKR, which clears request to processor r3,0x0(r3) # load address of ISR from vector table wrteei 1 # enable processor recognition of interrupts...
Page 234: Isr, Rtos, And Task Hierarchy
Interrupt Controller (INTC) RM0046 interrupt_exception_handlerx only has space for four instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed. interrupt_exception_handlerx: b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue interrupt_exception_handler_continuedx: code to create stack frame, save working register, and save SRR0 and SRR1 wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 EABI...
Page 235: Order Of Execution
RM0046 Interrupt Controller (INTC) An ISR whose PRIn in INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) has a value of 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interrupt request is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit will cause it to remain negated, which consequently also will not cause an interrupt request to the processor.
Page 236: Priority Ceiling Protocol
Interrupt Controller (INTC) RM0046 Table 76. Order of ISR execution example (continued) Code Executing at End of Step PRI in Step INTC_CPR Interrupt Step Description ISR108 ISR20 ISR30 ISR40 at End of RTOS Exception Step Handler ISR308 completes. Interrupt exception handler writes to INTC_EOIR.
Page 237: Selecting Priorities According To Request Rates And Deadlines
RM0046 Interrupt Controller (INTC) OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource. To prevent corruption of a coherent data block, modifications to PRI in INTC_CPR can be made by those system services with the code sequence: disable processor recognition of interrupts PRI modification enable processor recognition of interrupts...
Page 238: Lowering Priority Within An Isr
Interrupt Controller (INTC) RM0046 value in the INTC_PSRx_x and will not cause preemptive scheduling inefficiencies. After generating a software settable interrupt request, the higher priority ISR completes. The lower priority ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the completion of the lower priority ISR.
Page 239: Examining Lifo Contents
RM0046 Interrupt Controller (INTC) Proper setting of interrupt request priority Whether an interrupt request negates outside its own ISR due to the side effect of an ISR execution or the intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly.
Page 240: System Status And Configuration Module (Sscm)
System Status and Configuration Module (SSCM) RM0046 System Status and Configuration Module (SSCM) 10.1 Introduction 10.1.1 Overview The System Status and Configuration Module (SSCM), pictured in Figure 88, provides central device functionality. System Status and Configuration Module RevID Hardmacro Core Debug Logic Port...
Page 241: Modes Of Operation
RM0046 System Status and Configuration Module (SSCM) 10.1.3 Modes of operation The SSCM operates identically in all system modes. 10.2 Memory map and register description This section provides a detailed description of all memory-mapped registers in the SSCM. 10.2.1 Memory map Table 77 shows the memory map for the SSCM.
Page 242: Table 78. Status Allowed Register Accesses
System Status and Configuration Module (SSCM) RM0046 System Status register (STATUS) The system status register is a read-only register that reflects the current state of the system. Figure 90. Status (STATUS) register Address: Base + 0x0000 Access: Read-only PUB SEC BMODE[2:0] RESET: Table 78.
Page 243: Table 80. Memconfig Field Descriptions
RM0046 System Status and Configuration Module (SSCM) System Memory Configuration register (MEMCONFIG) The system memory configuration register is a read-only register that reflects the memory configuration of the system. Figure 91. System memory configuration (MEMCONFIG) register Address: Base + 0x0002 Access: Read-only IVLD DVLD...
Page 244: Table 82. Error Field Descriptions
System Status and Configuration Module (SSCM) RM0046 Error Configuration (ERROR) register The Error Configuration register is a read-write register that controls the error handling of the system. Figure 92. Error Configuration (ERROR) register Address: Base + 0x0006 Access: User read/write PAE RAE Reset Table 82.
Page 245: Table 84. Debugport Field Descriptions
RM0046 System Status and Configuration Module (SSCM) Debug Status Port (DEBUGPORT) register The Debug Status Port register provides debug data on a set of pins. Figure 93. Debug Status Port (DEBUGPORT) register Address: Base + 0x0008 Access: User read/write DEBUG_MODE [2:0] Reset Table 84.
Page 246: Table 86. Debugport Allowed Register Accesses
System Status and Configuration Module (SSCM) RM0046 Table 86. DEBUGPORT allowed register accesses Access width Access type 8-bit 16-bit 32-bit Read Allowed Allowed Not allowed Write Allowed Allowed Not allowed 1. All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). Password comparison registers These registers allow to unsecure the device, if the correct password is known.
Page 247: Functional Description
RM0046 System Status and Configuration Module (SSCM) Table 88. PWCMPH/L allowed register accesses Access width Access type 8-bit 16-bit 32-bit Read Allowed Allowed Allowed Write Not allowed Not allowed Allowed 1. All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). 10.3 Functional description The primary purpose of the SSCM is to provide information about the current state and...
Page 248: System Integration Unit Lite (Siul)
System Integration Unit Lite (SIUL) RM0046 System Integration Unit Lite (SIUL) 11.1 Introduction This chapter describes the System Integration Unit Lite (SIUL), which is used for the management of the pads and their configuration. It controls the multiplexing of the alternate functions used on all pads and is responsible for managing the external interrupts to the device.
Page 249: Features
RM0046 System Integration Unit Lite (SIUL) SIUL Module Pad Configuration (IOMUXC) Pad Config (PCRs) GPIO Functionality Data Pads Pad Input Master Interrupt Functionality Interrupt Controller Interrupt – Configuration – Glitch Filter Figure 96. System Integration Unit Lite block diagram 11.3 Features The System Integration Unit Lite provides these features: ●...
Page 250: Register Protection
System Integration Unit Lite (SIUL) RM0046 11.3.1 Register protection Most of the configuration registers of the System Integration Unit Lite are protected from accidental writes, see Appendix A: Registers Under Protection. 11.4 External signal description The pad configuration allows flexible, centralized control of the pin electrical characteristics of the MCU with the GPIO control providing centralized general purpose I/O for an MCU that multiplexes GPIO with other signals at the I/O pads.
Page 251: Memory Map And Register Description
RM0046 System Integration Unit Lite (SIUL) 11.5 Memory map and register description This section provides a detailed description of all registers accessible in the SIUL module. 11.5.1 SIUL memory map Table 90 lists the SIUL registers. Table 90. SIUL memory map Offset from SIUL_BASE Register...
Page 252: Register Description
System Integration Unit Lite (SIUL) RM0046 Table 90. SIUL memory map (continued) Offset from SIUL_BASE Register Location (0xC3F9_0000) 0x1000–0x1060 Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24]) on page 11-265 0x1064–0x107C Reserved 0x1080 Interrupt Filter Clock Prescaler Register (IFCPR) on page 11-266 0x1084–0x3FFF Reserved Note: A transfer error will be issued when trying to access completely reserved register space.
Page 253: Table 91. Midr1 Field Descriptions
RM0046 System Integration Unit Lite (SIUL) Table 91. MIDR1 field descriptions Field Description MCU Part Number Device part number of the MCU. 0101_0110_0000_0001: 192 KB PARTNUM[15:0] 0101_0110_0000_0010: 256 KB 0101_0110_0000_0011: 320/384 KB For the full part number this field needs to be combined with MIDR2.PARTNUM[23:16] Always reads back 0 Package Settings Can by read by software to determine the package type that is used for the particular device:...
Page 254: Table 92. Midr2 Field Descriptions
Table 92. MIDR2 field descriptions Field Description Manufacturer 0: Reserved 1: ST Coarse granularity for Flash memory size Needs to be combined with FLASH_SIZE_2 to calculate the actual memory size. FLASH_SIZE[3:0] 0011: 192 KB 0100: 256 KB Other values are reserved.
Page 255: Table 93. Isr Field Descriptions
RM0046 System Integration Unit Lite (SIUL) Interrupt Status Flag Register (ISR) This register holds the interrupt flags. Figure 100. Interrupt Status Flag Register (ISR) Address: Base + 0x0014 Access: User read/write EIF[24:16] Reset EIF[15:0] Reset Table 93. ISR field descriptions Field Description External Interrupt Status Flag n...
Page 256: Table 95. Ireer Field Descriptions
System Integration Unit Lite (SIUL) RM0046 Interrupt Rising-Edge Event Enable Register (IREER) This register allows rising-edge triggered events to be enabled on the corresponding interrupt pads. Figure 102. Interrupt Rising-Edge Event Enable Register (IREER) Address: Base + 0x0028 Access: User read/write IREE[24:16] Reset IREE[15:0]...
Page 257: Table 97. Ifer Field Descriptions
RM0046 System Integration Unit Lite (SIUL) Note: If both the IREER.IREE and IFEER.IFEE bits are cleared for the same interrupt source, the interrupt status flag for the corresponding external interrupt will never be set. Interrupt Filter Enable Register (IFER) This register enables a digital filter counter on the corresponding interrupt pads to filter out glitches on the inputs.
Page 258: Table 98. Pcr[0:71] Field Descriptions
System Integration Unit Lite (SIUL) RM0046 Table 98. PCR[0:71] field descriptions Field Description Safe Mode Control This bit supports the overriding of the automatic deactivation of the output buffer of the associated pad upon entering Safe mode of the device. 0: In Safe mode, output buffer of the pad disabled 1: In Safe mode, output buffer remains functional Analog Pad Control...
Page 259: Table 99. Pcr[N] Reset Value Exceptions
RM0046 System Integration Unit Lite (SIUL) Table 99. PCR[n] reset value exceptions Field Description PCR[2] These registers correspond to the ABS[0], ABS[1], and FAB boot pins, respectively. Their default PCR[3] state is input, pull enabled. Their reset value is 0x0102. PCR[4] This register corresponds to the TDO pin.
Page 260: Table 101. Psmi[0_3:32_35] Field Descriptions
System Integration Unit Lite (SIUL) RM0046 Figure 106. Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35]) Base + 0x0500 (PSMI0_3) Base + 0x0514 (PSMI20_23) Base + 0x0504 (PSMI4_7) Base + 0x0518 (PSMI024_27) Address: Base + 0x0508 (PSMI8_11) Access: User read/write Base + 0x051C (PSMI28_31) Base + 0x050C (PSMI12_15) Base + 0x0520 (PSMI32_35) Base + 0x0510 (PSMI16_19)
Page 261 RM0046 System Integration Unit Lite (SIUL) Table 102. Pad selection (continued) LQFP pin PADSEL[3:0] Register PADSEL Module Port Port name value 64-pin 100-pin 0000 C[12] PADSEL0 eTimer0 ETC[5] 0001 B[8] PSMI8_11 PADSEL1 — — — — — — PADSEL2 — —...
Page 262: Table 103. Gpdo[0_3:68_71] Field Descriptions
System Integration Unit Lite (SIUL) RM0046 GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) These registers can be used to set or clear a single GPIO pad with a byte access. Figure 107. Port GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) Base + 0x0600 (GPDO0_3) Address: Access: User read/write...
Page 263: Table 104. Gpdi[0_3:68_71] Field Descriptions
RM0046 System Integration Unit Lite (SIUL) Table 104. GPDI[0_3:68_71] field descriptions Field Description Pad Data In This bit stores the value of the external GPIO pad associated with this register. PDI[x] 0: The value of the data in signal for the corresponding GPIO pad is logic low. 1: The value of the data in signal for the corresponding GPIO pad is logic high.
Page 264: Table 106. Pgpdi[0:3] Field Descriptions
System Integration Unit Lite (SIUL) RM0046 Figure 110. Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3]) Base + 0x0C40 (PGPDI0) Base + 0x0C45 (PGPDI2) Address: Access: User read-only Base + 0x0C44 (PGPDI1) Base + 0x0C4C (PGPDI3) PPDI[x][15:0] Reset PPDI[x + 1][15:0] Reset Table 106.
Page 265: Table 107. Mpgpdo[0:6] Field Descriptions
RM0046 System Integration Unit Lite (SIUL) Table 107. MPGPDO[0:6] field descriptions Field Description Mask Field MASK[x] Each bit corresponds to one data bit in the MPPDO[x] field at the same bit location. [15:0] 0: The associated bit value in the MPPDO[x] field is ignored. 1: The associated bit value in the MPPDO[x] field is written.
Page 266: Table 109. Ifcpr Field Descriptions
System Integration Unit Lite (SIUL) RM0046 Interrupt Filter Clock Prescaler Register (IFCPR) This register configures a clock prescaler that selects the clock for all digital filter counters in the SIUL. Figure 113. Interrupt Filter Clock Prescaler Register (IFCPR) Address: Base + 0x1080 Access: User read/write Reset IFCP[3:0]...
Page 267: Functional Description
RM0046 System Integration Unit Lite (SIUL) 11.6 Functional description 11.6.1 General This section provides a functional description of the System Integration Unit Lite. 11.6.2 Pad control The SIUL controls the configuration and electrical characteristic of the device pads. It provides a consistent interface for all pads, both on a by-port and a by-bit basis. The SIUL allows each pad to be configured as either a General Purpose Input Output pad (GPIO), and as one or more alternate functions (input or output).
Page 268: External Interrupts
System Integration Unit Lite (SIUL) RM0046 possibility of reading back an input or output value of a pad directly. This supports the ability to validate what is present on the pad rather than merely confirming the value that was written to the data register by accessing the data input registers. The data output registers support both read and write operations to be performed.
Page 269: Pin Muxing
RM0046 System Integration Unit Lite (SIUL) active falling edge or both edges being active. A setting of having both edge events disabled is reserved and should not be configured. The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER.
Page 270: E200Z0 And E200Z0H Core
e200z0 and e200z0h Core RM0046 e200z0 and e200z0h Core 12.1 Overview The SPC560P40/34 microcontroller implements the e200z0h core. The e200 processor family is a set of CPU cores built on the Power Architecture technology. e200 processors are designed for deeply embedded control applications that require low cost solutions rather than maximum performance.
Page 271: Microarchitecture Summary
RM0046 e200z0 and e200z0h Core ● Testability – Synthesizeable, full MuxD scan design – ABIST/MBIST for optional memory arrays 12.2.1 Microarchitecture summary The e200z0 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.
Page 272: Figure 116. E200Z0 Block Diagram
e200z0 and e200z0h Core RM0046 Block diagram OnCE/NEXUS CONTROL LOGIC CONTROL LOGIC INTEGER EXECUTION UNIT MULTIPLY INSTRUCTION UNIT UNIT INSTRUCTION BUFFER CONTROL EXTERNAL DATA INTERFACE (MTSPR/MFSPR) BRANCH UNIT UNIT LOAD/STORE UNIT Figure 116. e200z0 block diagram 272/936 Doc ID 16912 Rev 5...
Page 273: Figure 117. E200Z0H Block Diagram
RM0046 e200z0 and e200z0h Core OnCE/NEXUS CONTROL LOGIC CONTROL LOGIC NEXUS DEBUG INTEGER EXECUTION UNIT UNIT MULTIPLY INSTRUCTION UNIT UNIT INSTRUCTION BUFFER CONTROL EXTERNAL DATA INTERFACE (MTSPR/MFSPR) BRANCH UNIT UNIT LOAD/STORE UNIT DATA BUS INTERFACE UNIT ADDRESS DATA CONTROL Figure 117. e200z0h block diagram Doc ID 16912 Rev 5 273/936...
Page 274 e200z0 and e200z0h Core RM0046 Instruction unit features The features of the e200 Instruction unit are: ● 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or as many as two 16-bit VLE instructions per clock ● Instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a pair of 16-bit instructions ●...
Page 275: Core Registers And Programmer's Model
RM0046 e200z0 and e200z0h Core Nexus features The Nexus 1 module is compliant with Class 1 of the IEEE-ISTO 5001-2003 standard. The following features are implemented: ● Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities.
Page 276: Figure 118. E200Z0 Supervisor Mode Programmer's Model
e200z0 and e200z0h Core RM0046 Exception Handling/Control Registers General Registers SPR General Save and Restore Interrupt Vector Prefix Condition Register General-Purpose SPRG0 SPR 272 IVPR SPR 63 SRR0 SPR 26 Registers SPRG1 SPR 273 SRR1 SPR 27 GPR0 Count Register CSRR0 SPR 58 GPR1...
Page 277: Figure 119. E200Z0H Supervisor Mode Programmer's Model
RM0046 e200z0 and e200z0h Core Exception Handling/Control Registers General Registers SPR General Save and Restore Interrupt Vector Prefix Condition Register General-Purpose SPRG0 SPR 272 IVPR SPR 63 SRR0 SPR 26 Registers SPRG1 SPR 273 SRR1 SPR 27 GPR0 Count Register CSRR0 SPR 58 GPR1...
Page 278: Unimplemented Sprs And Read-Only Sprs
e200z0 and e200z0h Core RM0046 USER Mode Programmer Model General Registers General-Purpose Condition Register Registers Cache Registers GPR0 Count Register Cache Configuration GPR1 (Read-only) SPR 9 Link Register L1CFG0 SPR 515 SPR 8 GPR31 SPR 1 Figure 120. e200 User mode program model 12.3.1 Unimplemented SPRs and read-only SPRs mfspr...
Page 279: Peripheral Bridge (Pbridge)
RM0046 Peripheral Bridge (PBRIDGE) Peripheral Bridge (PBRIDGE) 13.1 Introduction The Peripheral Bridge (PBRIDGE) is the interface between the system bus and on-chip peripherals. 13.1.1 Block diagram System Bus Crossbar Switch (XBAR) eTimer_0 Asynchronous FlexPWM Bridge Peripheral ADC_0 Bridge Safety_Port Other peripherals Figure 121.
Page 280: Functional Description
Peripheral Bridge (PBRIDGE) RM0046 13.2 Functional description The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as a protocol translator. Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module selects for peripheral devices on the slave bus interface.
Page 281: Crossbar Switch (Xbar)
RM0046 Crossbar Switch (XBAR) Crossbar Switch (XBAR) 14.1 Introduction This chapter describes the multi-port crossbar switch (XBAR), which supports simultaneous connections between three master ports and three slave ports. XBAR supports a 32-bit address bus width and a 32-bit data bus width at all master and slave ports. 14.2 Block diagram Figure 122...
Page 282: Overview
Crossbar Switch (XBAR) RM0046 14.3 Overview The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests.
Page 283: General Operation
RM0046 Crossbar Switch (XBAR) 14.6.2 General operation When a master makes an access to the XBAR from an idle master state, the access is taken immediately by the XBAR. If the targeted slave port of the access is available (that is, the requesting master is currently granted ownership of the slave port), the access is immediately presented on the slave port.
Page 284: Slave Ports
Crossbar Switch (XBAR) RM0046 14.6.4 Slave ports The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are actively making requests. To do this the XBAR must not insert any bubbles onto the slave bus unless absolutely necessary.
Page 285 RM0046 Crossbar Switch (XBAR) Parking If no master is currently requesting the slave port, the slave port is parked. The slave port parks always to the most recently requesting master (park-on-last). When parked on the last master, the slave port is passing that master’s signals through to the slave bus. When the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port.
Page 286: Error Correction Status Module (Ecsm)
Error Correction Status Module (ECSM) RM0046 Error Correction Status Module (ECSM) 15.1 Introduction The Error Correction Status Module (ECSM) provides control functions for the device Standard Product Platform (SPP) including program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, and wakeup control for exiting sleep modes, and optional features such as an address map for the device’s crossbar switch, information on memory errors reported by error-correcting codes and/or generic access error information for certain processor cores.
Page 287: Memory Map
RM0046 Error Correction Status Module (ECSM) 15.4.1 Memory map Table 112 lists the registers in the ECSM. Table 112. ECSM registers Offset from ECSM_BASE Register Location Size (bits) 0xFFF4_0000 0x0000 PCT—Processor Core Type register on page 15-288 0x0002 REV—Revision register on page 15-288 0x0004 PLAMC —...
Page 288: Registers Description
Error Correction Status Module (ECSM) RM0046 Table 112. ECSM registers (continued) Offset from ECSM_BASE Register Location Size (bits) 0xFFF4_0000 0x006C REDR—RAM ECC Data register on page 15-305 0x0070–0x3FFF Reserved 15.4.2 Registers description Attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error.
Page 289: Table 114. Rev Field Descriptions
RM0046 Error Correction Status Module (ECSM) Table 114. REV field descriptions Name Description 0-15 Revision REV[15:0] The REV[15:0] field is specified by an input signal to define a software-visible revision number. Platform XBAR Master Configuration (PLAMC) The PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device’s AMBA-AHB Crossbar Switch (XBAR).
Page 290: Table 116. Asc Field Descriptions
Error Correction Status Module (ECSM) RM0046 Table 116. ASC field descriptions Field Description 64-bit Datapath DP64 0 Datapath width is 32 bits. 1 Datapath width is 64 bits. XBAR Slave Configuration ASC[7:0] 0 Bus slave connection to XBAR output port n is not present. 1 Bus slave connection to XBAR output port n is present.
Page 291: Table 118. Mrsr Field Descriptions
RM0046 Error Correction Status Module (ECSM) Figure 128. Miscellaneous Reset Status Register (MRSR) Address: Base + 0x000F Access: User read-only Reset Table 118. MRSR field descriptions Field Description Power-On Reset 0 Last recorded event was not caused by a power-on reset (based on a device input signal). 1 Last recorded event was caused by a power-on reset (based on a device input signal).
Page 292: Table 120. Mudcr Field Descriptions
Error Correction Status Module (ECSM) RM0046 Table 119. MIR field descriptions (continued) Field Description Flash Bank 1 Stall Interrupt 0 A flash bank 1 stall has not occurred. FB1SI 1 A flash bank 1 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no effect.
Page 293: Figure 131. Ecc Configuration Register (Ecr)
RM0046 Error Correction Status Module (ECSM) ECC registers There are a number of program-visible registers for the sole purpose of reporting and logging of memory failures. These registers include the following: ● ECC Configuration Register (ECR) ● ECC Status Register (ESR) ●...
Page 294: Table 121. Ecr Field Descriptions
Error Correction Status Module (ECSM) RM0046 Table 121. ECR field descriptions Field Description Enable RAM 1-bit Reporting This bit can only be set if the input enable signal is asserted. This signal is tied to 1 at SoC level and hence reporting of single-bit memory corrections is always enabled.
Page 295: Table 122. Esr Field Descriptions
RM0046 Error Correction Status Module (ECSM) where the combination of a properly enabled category in the ECR and the detection of the corresponding condition in the ESR produces the interrupt request. The ECSM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the association between the ESR and the corresponding address and attribute registers, which are loaded on each occurrence of an properly enabled ECC event.
Page 296: Figure 133. Ecc Error Generation Register (Eegr)
Error Correction Status Module (ECSM) RM0046 Table 122. ESR field descriptions (continued) Field Description RAM Non-Correctable Error The occurrence of a properly enabled non-correctable RAM error generates a ECSM ECC interrupt request. The faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT and REDR registers.
Page 297: Table 123. Eegr Field Descriptions
RM0046 Error Correction Status Module (ECSM) Table 123. EEGR field descriptions Field Description Force RAM Continuous 1-Bit Data Inversions 0 No RAM continuous 1-bit data inversions generated 1 1-bit data inversions in the RAM continuously generated The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit position specified in ERRBIT[6:0], continuously on every write operation.
Page 298 Error Correction Status Module (ECSM) RM0046 Table 123. EEGR field descriptions (continued) Field Description Force RAM One Non-Correctable Data Inversions 0 No RAM single 2-bit data inversions generated 1 One 2-bit data inversion in the RAM generated The assertion of this bit forces the RAM controller to create one 2-bit data inversion, as defined by the bit position specified in ERRBIT[6:0] and the overall odd parity bit, on the first write operation after this bit is set.
Page 299: Table 124. Fear Field Descriptions
RM0046 Error Correction Status Module (ECSM) Figure 134. Flash ECC Address register (FEAR) Address Base + 0x0050 Access: User read-only FEAR[31:16] Reset — — — — — — — — — — — — — — — — FEAR[15:0] Reset —...
Page 300: Table 126. Feat Field Descriptions
Error Correction Status Module (ECSM) RM0046 Configuration Register, an ECC event in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model;...
Page 301: Table 127. Fedr Field Descriptions
RM0046 Error Correction Status Module (ECSM) The data captured on a multi-bit non-correctable ECC error is undefined. This register can only be read from the IPS programming model; any attempted write is ignored. Figure 137. Flash ECC Data register (FEDR) Address: Base + 0x005C Access: User read-only FEDR[31:16]...
Page 302: Table 128. Rear Field Descriptions
Error Correction Status Module (ECSM) RM0046 Table 128. REAR field descriptions Name Description 0-31 RAM ECC Address Register REAR[31:0] This 32-bit register contains the faulting access address of the last properly enabled RAM ECC event. RAM ECC Syndrome Register (RESR) The RESR is an 8-bit register for capturing the error syndrome of the last properly enabled ECC event in the RAM memory.
Page 303 RM0046 Error Correction Status Module (ECSM) Table 130. RAM syndrome mapping for single-bit correctable errors (continued) RESR[7:0] Data Bit in Error 0x06 DATA ODD BANK[31] 0x08 ECC ODD[3] 0x0A DATA ODD BANK[30] 0x0C DATA ODD BANK[29] 0x0E DATA ODD BANK[28] 0x10 ECC ODD[4] 0x12...
Page 304: Table 131. Remr Field Descriptions
Error Correction Status Module (ECSM) RM0046 Table 130. RAM syndrome mapping for single-bit correctable errors (continued) RESR[7:0] Data Bit in Error 0x4C DATA ODD BANK[0] 0x03,0x05..0x4D Multiple bit error > 0x4D Multiple bit error RAM ECC Master Number Register (REMR) The REMR is an 8-bit register in which the 4-bit field REMR[0:3] is used for capturing the XBAR bus master number of the last properly enabled ECC event in the RAM memory.
Page 305: Table 132. Reat Field Descriptions
RM0046 Error Correction Status Module (ECSM) Figure 141. RAM ECC Attributes (REAT) register Address: Base + 0x0067 Access: User read/write WRITE SIZE[2:0] PROTECTION[3:0] Reset — — — — — — — — Table 132. REAT field descriptions Name Description AMBA-AHB HWRITE 0 AMBA-AHB read access WRITE 1 AMBA-AHB write access...
Page 306: Ecsm_Reg_Protection
Error Correction Status Module (ECSM) RM0046 Figure 142. Platform RAM ECC Data register (PREDR) Address: Base + 0x006C Access: User read-only REDR[31:16] Reset — — — — — — — — — — — — — — — — REDR[15:0] Reset —...
Page 307: Figure 143. Spp_Ips_Reg_Protection Block Diagram
RM0046 Error Correction Status Module (ECSM) INTC ips_supervisor_access ECSM PBRIDGE ECSM_REG_PROTECTION Figure 143. Spp_Ips_Reg_Protection block diagram Attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the programming model must match the size of the register;...
Page 308: Internal Static Ram (Sram)
Internal Static RAM (SRAM) RM0046 Internal Static RAM (SRAM) 16.1 Introduction The general-purpose SRAM has a size of 20 KB. The SRAM provides the following features: ● SRAM can be read/written from any bus master ● Byte, halfword, word and doubleword addressable ●...
Page 309: Access Timing
RM0046 Internal Static RAM (SRAM) Internal SRAM write operations are performed on the following byte boundaries: ● 1 byte (0:7 bits) ● 2 bytes (0:15 bits) ● 4 bytes or 1 word (0:31 bits) If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated across the 32-bit data bus.
Page 310: Reset Effects On Sram Accesses
Internal Static RAM (SRAM) RM0046 Table 136. Number of wait states required for SRAM operations (continued) Operation type Current operation Previous operation Number of wait states required Idle Read Pipelined 8- or 16-bit write 8 or 16-bit write 32-bit write Write 8 or 16-bit write (write to the same address)
Page 311: Flash Memory
RM0046 Flash Memory Flash Memory 17.1 Introduction The Flash memory comprises a platform Flash controller interface and two Flash memory arrays: one array of 256 KB for code (code Flash) and one array of 64 KB for data (data Flash). The Flash architecture of the SPC560P40/34 device is illustrated in Figure 144.
Page 312 Flash Memory RM0046 connections, one to each memory bank. On the SPC560P40/34 device, bank0 and bank1 are internal to the device. ● Array—Each memory bank has one Flash array instantiation. ● Page—This value defines the number of bits read from the Flash array in a single access.
Page 313: Modes Of Operation
RM0046 Flash Memory states) for accesses that hit in the holding register. There is no support for prefetching associated with bank1. ● Programmable response for read-while-write sequences including support for stall- while-write, optional stall notification interrupt, optional Flash operation termination, and optional termination notification interrupt ●...
Page 314: Table 137. Flash-Related Regions In The System Memory Map
Flash Memory RM0046 system memory map defines one code Flash array and one data Flash array. See Table 137. Caution: Software executing from flash memory must not write to registers that control flash behavior (such as wait state settings or prefetch enable/disable). Doing so can cause data corruption. On this chip, these registers include PFCR0 and PFAPR.
Page 315: Functional Description
RM0046 Flash Memory Note: To perform program and erase operations, the control registers in the actual referenced Flash array must both be programmed, but the configuration of the platform Flash controller module is defined by the platform Flash controller control registers of code array0. The 32-bit memory map for the platform Flash controller control registers is shown in Table 138.
Page 316: Access Protections
Flash Memory RM0046 Accesses are terminated under control of the appropriate read/write wait state control setting. Thus, the access time of the operation is determined by the settings of the wait state control fields. Access timing can be varied to account for the operating conditions of the device (frequency, voltage, temperature) by appropriately setting the fields in the programming model for either bank.
Page 317: Write Cycles
RM0046 Flash Memory Likewise, the bank1 logic includes a single 128-bit temporary holding register and sequential accesses that “hit” in this register are also serviced with a 0 wait state response. 17.2.10 Write cycles In a write cycle, address, write data, and control signals are launched off the same edge of hclk at the completion of the first AHB data phase cycle.
Page 318: Flash Error Response Operation
Flash Memory RM0046 17.2.13 Flash error response operation The Flash array may signal an error response by asserting bkn_fl_xfr_err to terminate a requested access with an error. This may occur due to an uncorrectable ECC error, or because of improper sequencing during program/erase operations. When an error response is received, the platform Flash controller does not update or validate a bank0 page read buffer nor the bank1 temporary holding register.
Page 319 RM0046 Flash Memory Invalid—the buffer contains no valid data. Used—the buffer contains valid data that has been provided to satisfy an AHB burst type read. Valid—the buffer contains valid data that has been provided to satisfy an AHB single type read. Prefetched—the buffer contains valid data that has been prefetched to satisfy a potential future AHB access.
Page 320: Bank1 Temporary Holding Register
Flash Memory RM0046 Buffer allocation Allocation of the line read buffers is controlled via page buffer configuration (Bx_Py_BCFG) field. This field defines the operating organization of the four page buffers. The buffers can be organized as a “pool” of available resources (with all four buffers in the pool) or with a fixed partition between buffers allocated to instruction or data accesses.
Page 321: Read-While-Write Functionality
RM0046 Flash Memory single_ecc_error;// single-bit correctable ECC indicator from Flash array bk1_page_buffer; For the general case, a temporary holding register is written at the completion of an error- free Flash access and the valid bit asserted. Subsequent Flash accesses that “hit” the buffer, that is, the current access address matches the address stored in the temporary holding register, can be serviced in 0 AHB wait states as the stored read data is routed from the temporary register back to the requesting bus master.
Page 322: Wait State Emulation
Flash Memory RM0046 phase cycle to “retry” the read reference and sends the registered information to the array as bkn_fl_rd_en is asserted. Once the retried address phase is complete, the read is processed normally and once the data is valid, it is forwarded to the AHB bus and hready_out negated to terminate the system bus transfer.
Page 323: Timing Diagrams
RM0046 Flash Memory The platform Flash controller inserts additional wait states according to the values of haddr[28:24],where haddr represents the Flash address. When these inputs are non-zero, additional cycles are added to AHB read cycles. Write cycles are not affected. In addition, no page read buffer prefetches are initiated, and buffer hits are ignored.
Page 324: Figure 145. 1-Cycle Access, No Buffering, No Prefetch
Flash Memory RM0046 performance. The following diagrams illustrate operation of various cycle types and responses referenced earlier in this chapter including stall-while-read (Figure 149) and terminate-while-read (Figure 150) diagrams. Read, no buffering, no prefetch, APC = 0, RWSC = 0, PFLM = 0 hclk nonseq htrans...
Page 325: Figure 146. 3-Cycle Access, No Prefetch, Buffering Disabled
RM0046 Flash Memory Burst Read, buffer miss, no prefetch, APC=2, RWSC=2, PFLM=0 hclk nonseq htrans addr y addr y+8 addr y addr y+12 addr y+4 haddr,hprot hwrite C(y) C(y+4) hrdata hwdata hready_out okay okay okay okay okay okay okay okay hresp bkn_fl_addr bkn_fl_rd_en...
Page 326: Figure 147. 3-Cycle Access, No Prefetch, Buffering Enabled
Flash Memory RM0046 Burst Read, buffer miss, no prefetch, APC = 2, RWSC = 2, PFLM = 0 hclk htrans nonseq addr y haddr,hprot addr y+4 addr y+8 addr y+12 hwrite C(y) C(y+4) C(y+8) C(y+12) hrdata hwdata hready_out okay okay okay okay okay...
Page 327: Figure 148. 3-Cycle Access, Prefetch And Buffering Enabled
RM0046 Flash Memory Burst Read, buffer miss, prefetch, APC = 2, RWSC = 2, PFLM = 2 hclk nonseq htrans addr y+20 addr y addr y+8 addr y+16 addr y+4 addr y+12 haddr, hprot hwrite C(y+16) C(y+4) C(y+12) C(y) C(y+8) hrdata hwdata hready_out...
Page 328: Figure 149. 3-Cycle Access, Stall-And-Retry With Bkn_Rwwc = 11X
Flash Memory RM0046 Burst Read, Stall-and-Retry, APC = 2, RWSC = 2, PFLM = 2 hclk nonseq htrans addr y+4 addr y+8 haddr, hprot addr y hwrite C(y) C(y+4) hrdata hwdata hready_out okay okay okay okay okay okay okay okay okay okay hresp...
Page 329: Figure 150. 3-Cycle Access, Terminate-And-Retry With Bkn_Rwwc = 10X
RM0046 Flash Memory Burst Read, Abort-and-Retry, APC = 2, RWSC = 2, PFLM = 2 hclk nonseq htrans addr y addr y+8 addr y+4 haddr, hprot hwrite C(y+4) C(y) hrdata hwdata hready_out hresp okay okay okay okay okay okay okay okay okay okay...
Page 330: Flash Memory
Flash Memory RM0046 17.3 Flash memory 17.3.1 Introduction The Flash module provides electrically programmable and erasable non-volatile memory (NVM), which may be used for instruction and/or data storage. The Flash module is arranged as two functional units: the Flash core and the memory interface.
Page 331: Figure 151. Data Flash Module Structure
RM0046 Flash Memory HV generator Flash Program/Erase Flash Bank 1 Controller 64 KB + 8 KB TestFlash Data Flash Registers Registers Matrix Interface Interface Figure 151. Data Flash module structure Code Flash The code Flash module contains the matrix modules normally used for Code storage. No Read-While-Modify operations are possible.
Page 332: Functional Description
Flash Memory RM0046 HV generator Flash Program/Erase Flash Bank 0 Controller 256 KB + 16 KB TestFlash Code Flash + 16 KB Shadow Registers Registers Matrix Interface Interface Figure 152. Code Flash module structure 17.3.4 Functional description Macrocell structure The Flash macrocell provides high density non-volatile memories with high-speed read access.
Page 333: Table 142. 288 Kb Code Flash Module Sectorization
RM0046 Flash Memory An erased bit in the Flash module reads as logic level 1 (or high). Program and erase of the Flash module requires multiple system clock cycles to complete. The erase sequence may be suspended. The program and erase sequences may be terminated. Flash module sectorization The code Flash module supports 256 KB of user memory, plus 16 KB of test memory (a portion of which is one-time programmable by the user).
Page 334: Table 144. Testflash Structure
Flash Memory RM0046 Table 143. 64 KB data Flash module sectorization (continued) Bank Sector Addresses Size (KB) Address space Reserved 0x0081_0000 to 0x00C0_1FFF 4040 Reserved B1TF 0x00C0_2000 to 0x00C0_3FFF Test Address Space Reserved 0x00C0_4000 to 0x00FF_FFFF 4080 Reserved Each Flash module is divided into blocks to implement independent program/erase protection.
Page 335 RM0046 Flash Memory Shadow block A Shadow block is present in each Code flash module, but not in the Data flash module. The Shadow block can be enabled by the BIU. When the Shadow space is enabled, all the operations are mapped to the Shadow block. User mode program and erase of the shadow block are enabled only when MCR[PEAS] is set.
Page 336: Operating Modes
Flash Memory RM0046 Table 145. Shadow sector structure Size Name Description Addresses (bytes) — User Area 0x0020_0000–0x0020_3DCF 15824 — Reserved 0x0020_3DD0–0x0020_3DD7 NVPWD0–1 Non-volatile private censorship password 0–1 registers 0x0020_3DD8–0x0020_3DDF NVSCI0–1 Non-volatile system censorship information 0–1 registers 0x0020_3DE0–0x0020_3DE7 — Reserved 0x0020_3DE8–0x0020_3DFF NVBIU2–3 Non-volatile bus interface unit 2–3 registers 0x0020_3E00–0x0020_3E0F...
Page 337 RM0046 Flash Memory The main, shadow, and test address space can be read only in the read state. The Flash registers are always available for reads. When the module is in power-down mode, most (but not all) registers are available for reads. The exceptions are documented. The Flash module enters the read state on reset.
Page 338 Flash Memory RM0046 Power-down mode cannot be entered when Low-power mode is active. The module must first be set to User mode (or reset) when cycling between Low-power mode and Power- down mode. Power-down mode The Power-down mode allows turning off all Flash DC current sources so that power dissipation is limited only to leakage in this mode.
Page 339: Registers Description
RM0046 Flash Memory 17.3.6 Registers description The Flash user registers mapping is shown in Table 146. Except as noted, registers and offsets are identical for the code Flash and data Flash blocks. Table 146. Flash registers Offset from xxxx_BASE Register Location (0xFFFE_C000) 0x0000...
Page 340 Flash Memory RM0046 Table 147. Flash 256 KB bank0 register map (continued) Address Register offset name 0x04 TSLK LLK15 LLK14 LLK13 LLK12 LLK11 LLK10 LLK9 LLK8 LLK7 LLK6 LLK5 LLK4 LLK3 LLK2 LLK1 LLK0 0x08 Reserved 0x0C STSLK SLK15 SLK14 SLK13 SLK12 SLK11 SLK10 SLK9 SLK8 SLK7...
Page 341: Table 148. Flash 64 Kb Bank1 Register Map
RM0046 Flash Memory Table 148. Flash 64 KB bank1 register map Address Register offset name 0x00 SIZE2 SIZE1 SIZE0 LAS2 LAS1 LAS0 PEAS DONE PSUS ESUS 0x04 TSLK LLK15 LLK14 LLK13 LLK12 LLK11 LLK10 LLK9 LLK8 LLK7 LLK6 LLK5 LLK4 LLK3 LLK2 LLK1...
Page 342: Table 149. Mcr Field Descriptions
Flash Memory RM0046 Module Configuration Register (MCR) The Module Configuration Register enables and monitors all the modify operations of each Flash module. Identical MCRs are provided in the code Flash and the data Flash blocks. Figure 153. Module Configuration Register (MCR) Address: Base + 0x0000 Access: User read/write R EDC...
Page 343 RM0046 Flash Memory Table 149. MCR field descriptions (continued) Field Description Low Address Space 2–0 The value of the LAS field corresponds to the configuration of the Low Address Space: Reserved Reserved 32 KB + (2 × 16 KB) + (2 × 32 KB) + 128 KB (the value for the SPC560P40/34device in the LAS[2:0] code Flash module) Reserved...
Page 344 Flash Memory RM0046 Table 149. MCR field descriptions (continued) Field Description Program/Erase Access Space PEAS indicates which space is valid for program and Erase operations: main array space or shadow/test space. PEAS = 0 indicates that the main address space is active for all Flash module program and erase PEAS operations.
Page 345 RM0046 Flash Memory Table 149. MCR field descriptions (continued) Field Description Reserved (Read Only) 23:26 A write to these bits has no effect. A read of these bits always outputs 0. Program PGM sets up the Flash module for a program operation. A 0-to-1 transition of PGM initiates a program sequence.
Page 346: Table 150. Mcr Bits Set/Clear Priority Levels
Flash Memory RM0046 Table 149. MCR field descriptions (continued) Field Description Enable High Voltage The EHV bit enables the Flash module for a high voltage program/Erase operation. EHV is cleared on reset. EHV must be set after an interlock write to start a program/Erase sequence. EHV may be set under one of the following conditions: –...
Page 347: Table 151. Lml And Nvlml Field Descriptions
RM0046 Flash Memory In the code Flash module, the LML register has a related Non-Volatile Low/Mid Address Space Block Locking register (NVLML) located in TestFlash that contains the default reset value for LML. The NVLML register is read during the reset phase of the Flash module and loaded into the LML.
Page 348 Flash Memory RM0046 Table 151. LML and NVLML field descriptions (continued) Field Description Test/Shadow Address Space Block Lock This bit locks the block of Test and Shadow Address Space from program and Erase (Erase is any case forbidden for Test block). A value of 1 in the TSLK register signifies that the Test/Shadow block is locked for program and Erase.
Page 349: Figure 156. Secondary Low/Mid Address Space Block Locking Reg (Sll)
RM0046 Flash Memory Secondary Low/Mid Address Space Block Locking register (SLL) The Secondary Low/Mid Address Space Block Locking register provides an alternative means to protect blocks from being modified. These bits, along with bits in the LML register, determine if the block is locked from program or Erase. An “OR” of LML and SLL determine the final lock status.
Page 350: Table 152. Sll And Nvsll Field Descriptions
Flash Memory RM0046 Table 152. SLL and NVSLL field descriptions Field Description Secondary Low/Mid Address Space Block Enable This bit enables the Lock registers (STSLK and SLK[15:0]) to be set or cleared by registers writes. This bit is a status bit only. The method to set this bit is to write a password, and if the password matches, the SLE bit is set to reflect the status of enabled, and is enabled until a reset operation occurs.
Page 351: Figure 158. Low/Mid Address Space Block Select Register (Lms)
RM0046 Flash Memory Table 152. SLL and NVSLL field descriptions (continued) Field Description Secondary Low Address Space Block Lock 15–0 These bits are used as an alternate means to lock the blocks of Low Address Space from program and Erase. For code Flash, SLK[5:0] are related to sectors B0F[5:0], respectively.
Page 352: Table 153. Lms Field Descriptions
Flash Memory RM0046 Table 153. LMS field descriptions Field Description Reserved (Read Only) 0:13 A write to these bits has no effect. A read of these bits always outputs 0. 14:15 Reserved Low Address Space Block Select 15–0 A value of 1 in the select register signifies that the block is selected for erase. A value of 0 in the select register signifies that the block is not selected for erase.
Page 353: Table 155. Adr Content: Priority List
RM0046 Flash Memory Table 154. ADR field descriptions (continued) Field Description Address 22–3 ADR provides the first failing address in the event of ECC error (MCR[EER] set) or the first failing address in the event of RWW error (MCR[RWE] set), or the address of a failure that may have occurred in a FPEC operation (MCR[PEG] cleared).
Page 354: Table 156. Pfcr0 Field Descriptions
Flash Memory RM0046 Figure 160. Platform Flash Configuration Register 0 (PFCR0) Address: Base + 0x001C Access: User read/write BK0_APC BK0_WWSC BK0_RWSC Reset Reset Table 156. PFCR0 field descriptions Field Description Bank0 Address Pipelining Control This field controls the number of cycles between Flash array access requests. This field must be set to a value appropriate to the operating frequency of the PFlash.
Page 355 RM0046 Flash Memory Table 156. PFCR0 field descriptions (continued) Field Description Bank0 Read Wait State Control This field controls the number of wait states to be added to the Flash array access time for reads. This field must be set to a value corresponding to the operating frequency of the PFlash and the actual read access time of the PFlash.
Page 356 Flash Memory RM0046 Table 156. PFCR0 field descriptions (continued) Field Description Bank0, Port 0 Page Buffer Configuration This field controls the configuration of the four page buffers in the PFlash controller. The buffers can be organized as a “pool” of available resources, or with a fixed partition between instruction and data buffers.
Page 357: Table 157. Pfcr1 Field Descriptions
RM0046 Flash Memory Platform Flash Configuration Register 1 (PFCR1) The Platform Flash Configuration Register 1 (PFCR1) defines the configuration associated with Flash memory bank1. This corresponds to the data Flash. The register is described in Figure 161 Table 157. Note: This register is not implemented on the data Flash block.
Page 358 Flash Memory RM0046 Table 157. PFCR1 field descriptions (continued) Field Description Bank1 Read Wait State Control This field controls the number of wait states to be added to the Flash array access time for reads. This field must be set to a value corresponding to the operating frequency of the PFlash and the actual read access time of the PFlash.
Page 359: Table 158. Pfapr Field Descriptions
RM0046 Flash Memory Table 157. PFCR1 field descriptions (continued) Field Description Bank1, Port 0 Buffer Enable This bit enables or disables read hits from the 128-bit holding register. It is also used to invalidate the contents of the holding register. This bit is set by hardware reset, enabling the use of the holding register.
Page 360: Figure 163. User Test 0 Register (Ut0)
Flash Memory RM0046 Table 158. PFAPR field descriptions (continued) Field Description Master x Prefetch Disable (x = 0,1,2,...,7) These bits control whether prefetching may be triggered based on the master number of the requesting AHB master. This field is further qualified by the PFCR0[B0_Px_DPFE, B0_Px_IPFE, 8-15 Bx_Py_BFE] bits.
Page 361: Table 159. Ut0 Field Descriptions
RM0046 Flash Memory Table 159. UT0 field descriptions Field Description User Test Enable This status bit indicates when User Test is enabled. All bits in UT0–2 and UMISR0–4 are locked when this bit is 0. This bit is not writeable to a 1, but may be cleared. The reset value is 0. The method to set this bit is to provide a password, and if the password matches, the UTE bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write.
Page 362: Figure 164. User Test 1 Register (Ut1)
Flash Memory RM0046 Table 159. UT0 field descriptions (continued) Field Description Array Integrity Sequence AIS determines the address sequence to be used during array integrity checks or Margin Mode. The default sequence (AIS = 0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths.
Page 363: Table 160. Ut1 Field Descriptions
RM0046 Flash Memory Table 160. UT1 field descriptions Field Description Data Array Input 31–0 These bits represent the input of the even word of ECC logic used in the ECC Logic Check. DAI[31:0] The DAI[31:0] bits correspond to the 32 array bits representing Word 0 within the double word. 0:31 0 The array bit is forced at 0.
Page 364: Table 162. Umsir0 Field Descriptions
Flash Memory RM0046 Figure 166. User Multiple Input Signature Register 0 (UMISR0) Address: Base + 0x0048 Access: User read/write R MS Reset R MS Reset Table 162. UMSIR0 field descriptions Field Description Multiple input Signature 031–000 MS[031:000] These bits represent the MISR value obtained by accumulating the bits 31:0 of all the pages read from the Flash memory.
Page 365: Table 164. Umisr2 Field Descriptions
RM0046 Flash Memory User Multiple Input Signature Register 2 (UMISR2) The Multiple Input Signature Register (UMISR2) provides a mean to evaluate the array integrity. UMISR2 represents the bits 95-64 of the whole 144-bit word (2 double words including ECC). UMISR2 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.
Page 366: Table 165. Umisr3 Field Descriptions
Flash Memory RM0046 Figure 169. User Multiple Input Signature Register 3 (UMISR3) Address: Base + 0x0054 Access: User read/write R MS Reset R MS Reset Table 165. UMISR3 field descriptions Field Description Multiple Input Signature 127–096 MS[127:096] These bits represent the MISR value obtained accumulating bits 127:96 of all the pages read from the Flash memory.
Page 367: Table 166. Umisr4 Field Descriptions
RM0046 Flash Memory Table 166. UMISR4 field descriptions Field Description Multiple Input Signature 159:128 These bits represent the MISR value obtained accumulating: – MS[135:128]—8 ECC bits for the even double word – MS138—Single ECC error detection for even double word MS[159:128] –...
Page 368: Table 168. Nvpwd1 Field Descriptions
Flash Memory RM0046 Figure 172. Non-Volatile Private Censorship Password 1 register (NVPWD1) Address: 0x20_3DDC Access: User read/write R PWD Reset R PWD Reset Table 168. NVPWD1 field descriptions Field Description PWD63–32: PassWorD 63–32 0:31 The PWD63–32 registers represent the 32 MSB of the Private Censorship Password. Non-Volatile System Censoring Information 0 register (NVSCI0) The Non-Volatile System Censoring Information 0 register (NVSCI0) stores the 32 LSB of the Censorship Control Word of the device.
Page 369: Table 170. Nvsci1 Field Descriptions
RM0046 Flash Memory Table 169. NVSCI0 field descriptions (continued) Field Description Censorship control Word 15–0 CW[15:0] These bits represent the 16 LSB of the Censorship Control Word (CCW). 16:31 If CW[15:0] = 0x55AA and NVSCI1 = NVSCI0, the Censored mode is disabled. If CW[15:0] ...
Page 370: Code Flash Programming Considerations
Flash Memory RM0046 NVUSRO is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care” bits that are eventually used to manage ECC codes. Note: This register is not implemented on the data Flash block. Figure 175.
Page 371: Table 172. Flash Modify Operations
RM0046 Flash Memory All the sectors of the Flash module belong to the same partition (Bank), therefore when a Modify operation is active on some sectors, no read access is possible on any other sector (Read-While-Modify is not supported). During a Flash modify operation, any attempt to read any Flash location will output invalid data and the MCR[RWE] bit will be automatically set.
Page 372 Flash Memory RM0046 Double word program A Flash program sequence operates on any double word within the Flash core. One or both words within a double word may be altered in a single program operation. Whenever the Flash is programmed, ECC bits are also programmed (unless the selected address belongs to a sector in which the ECC has been disabled in order to allow bit manipulation).
Page 373 RM0046 Flash Memory An interlock write must be performed before setting MCR[EHV]. The user may terminate a program sequence by clearing MCR[PGM] prior to setting MCR[EHV]. After the interlock write, additional writes only affect the data to be programmed at the word location determined by address bit 2.
Page 374 Flash Memory RM0046 Note: Lock and Select are independent. If a block is selected and locked, no erase will occur. Write to any address in Flash. This is referred to as an erase interlock write. Set MCR[EHV] to start the internal erase sequence, or skip to step 9 to terminate. Wait until the MCR[DONE] bit goes high.
Page 375 RM0046 Flash Memory Once suspended, the array may be read. Flash core reads while MCR[ESUS] = 1 from the block(s) being erased return indeterminate data. Example 3Sector Erase Suspend = 0x00000007; /* Set ESUS in MCR: Erase Suspend */ /* Loop to wait for DONE=1 */ { tmp = MCR;...
Page 376 Flash Memory RM0046 The 128-bit data and the 16-bit ECC data are sampled before the eventual ECC correction, while the single and double error flags are sampled after the ECC evaluation. Only data from existing and unlocked locations are captured by the MISR. The MISR can be seeded to any value by writing the UMISR0–4 registers.
Page 377 RM0046 Flash Memory Since Margin reads are done at voltages that differ than the normal read voltage, the lifetime expectancy of the Flash macrocell is impacted by the execution of Margin reads. Repeated Margin reads will result in degradation of the Flash array, and will shorten the expected lifetime experienced at normal read levels.
Page 378 Flash Memory RM0046 data4 = UMISR4; /* Read UMISR4 content*/ UT0 = 0x80000034; /* Reset AIE in UT0: Operation End */ UT0 = 0x00000000; /* Reset UTE, MRE, MRV, AIS in UT0: Deselect Op. */ ECC logic check ECC logic can be checked by forcing the input of ECC logic: The 64 bits of data and the 8 bits of ECC syndrome can be individually forced and they will drive simultaneously at the same value the ECC logic of the whole page (2 double words).
Page 379: Table 173. Bits Manipulation: Double Words With The Same Ecc Value
RM0046 Flash Memory ECC algorithms The Flash macrocell supports the ECC algorithm “All 1s No Error”. All 1s No Error The All 1s No Error algorithm detects as valid any double word read on a just erased sector (all the 72 bits are 1s). This option allows performing a Blank Check after a Sector Erase operation.
Page 380 Flash Memory RM0046 Modify protection The Flash modify protection information is stored in non-volatile Flash cells located in the TestFlash. This information is read once during the Flash initialization phase following the exit from reset and they are stored in Volatile registers that act as actuators. The reset state of all the volatile modify protection registers is the protected state.
Page 381: Table 174. Bits Manipulation: Censorship Management
RM0046 Flash Memory The Flash block provides two levels of protection against piracy: ● If bits NVSCI0[CW[15:0]] are programmed to 0x55AA and NVSC1 = NVSCI0, Censored mode is disabled. All other possible values enable Censored mode. ● If bits NVSCI0[SC[15:0]] are programmed to 0x55AA and NVSC1 = NVSCI0, Public Access is disabled.
Page 382: Enhanced Direct Memory Access (Edma)
Enhanced Direct Memory Access (eDMA) RM0046 Enhanced Direct Memory Access (eDMA) 18.1 Introduction This chapter describes the enhanced Direct Memory Access (eDMA) Controller, a second- generation module capable of performing complex data transfers with minimal intervention from a host processor. 18.2 Overview The enhanced direct memory access (eDMA) controller hardware microarchitecture...
Page 383: Features
RM0046 Enhanced Direct Memory Access (eDMA) 18.3 Features The eDMA is a highly programmable data transfer engine, which has been optimized to minimize the required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known, and is not defined within the data packet itself.
Page 384: Debug Mode
Enhanced Direct Memory Access (eDMA) RM0046 18.4.2 Debug mode If enabled by EDMA_CR[EDBG] and the CPU enters debug mode, the eDMA does not grant a service request when the debug input signal is asserted. If the signal asserts during a data block transfer as described by a minor loop in the current active channel’s TCD, the eDMA continues the operation until the minor loop completes.
Page 385 RM0046 Enhanced Direct Memory Access (eDMA) Table 175. eDMA memory map (continued) Offset from EDMA_BASE Register Location (0xFFF4_4000) 0x0028 Reserved 0x002C EDMA_ERL—eDMA Error Register on page 18-397 0x0030 Reserved EDMA_HRSL—eDMA Hardware Request Status 0x0034 on page 18-397 Register 0x0038–0x00FF Reserved 0x0100 EDMA_CPR0—eDMA Channel 0 Priority Register on page 18-398...
Page 386: Register Descriptions
Enhanced Direct Memory Access (eDMA) RM0046 Table 175. eDMA memory map (continued) Offset from EDMA_BASE Register Location (0xFFF4_4000) 0x10E0 TCD07—Transfer Control Descriptor 7 on page 18-399 0x1100 TCD08—Transfer Control Descriptor 8 on page 18-399 0x1120 TCD09—Transfer Control Descriptor 9 on page 18-399 0x1140 TCD10—Transfer Control Descriptor 10 on page 18-399...
Page 387: Table 176. Edma_Cr Field Descriptions
RM0046 Enhanced Direct Memory Access (eDMA) Table 176. EDMA_CR field descriptions Field Description 0-28 Reserved. Enable round-robin channel arbitration. 0 Fixed-priority arbitration is used for channel selection within each group. ERCA 1 Round-robin arbitration is used for channel selection within each group. Enable debug.
Page 388: Table 177. Edma_Esr Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0046 The occurrence of any type of error causes the eDMA engine to stop the active channel, and the appropriate channel bit in the eDMA error register to be asserted. At the same time, the details of the error condition are loaded into the EDMA_ESR. The major loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected.
Page 389 RM0046 Enhanced Direct Memory Access (eDMA) Table 177. EDMA_ESR field descriptions (continued) Field Description Source offset error. 0 No source offset configuration error. 1 The last recorded error was a configuration error detected in the TCD.SOFF field, indicating TCD.SOFF is inconsistent with TCD.SSIZE. Destination address error.
Page 390: Table 178. Edma_Erqrl Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0046 Figure 179. eDMA Enable Request Low Register (EDMA_ERQRL) Address: Base + 0x000C Access: User read/write Reset R ERQ Reset Table 178. EDMA_ERQRL field descriptions Field Description Enable DMA hardware service request n. 16–31 0 The DMA request signal for channel n is disabled. ERQn 1 The DMA request signal for channel n is enabled.
Page 391: Table 179. Edma_Eeirl Field Descriptions
RM0046 Enhanced Direct Memory Access (eDMA) Figure 180. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL) Address: Base + 0x0014 Access: User read/write Reset EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00 Reset Table 179.
Page 392: Table 181. Edma_Cerqr Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0046 eDMA Clear Enable Request Register (EDMA_CERQR) The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERQRL to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the EDMA_ERQRL to be cleared.
Page 393: Table 182. Edma_Seeir Field Descriptions
RM0046 Enhanced Direct Memory Access (eDMA) Table 182. EDMA_SEEIR field descriptions Field Description Reserved. Set enable error interrupt. 0–15 Set corresponding bit in EDMA_EIRRL 16–63 Reserved 1–7 64–127 Set all bits in EDMA_EEIRL SEEI[0:6] Bit 2 (SEEI1) is not used. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) The EDMA_CEEIR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_EEIRL to disable the error interrupt for a given channel.
Page 394: Table 184. Edma_Cirqr Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0046 Figure 185. eDMA Clear Interrupt Request (EDMA_CIRQR) Address: Base + 0x001C Access: User write-only CINT[0:6] Reset Table 184. EDMA_CIRQR field descriptions Field Description Reserved. Clear interrupt request. 0–15 Clear corresponding bit in EDMA_IRQRL 1–7 16–63 Reserved CINT[0:6] 64–127 Clear all bits in EDMA_IRQRL...
Page 395: Table 186. Edma_Ssbr Field Descriptions
RM0046 Enhanced Direct Memory Access (eDMA) eDMA Set START Bit Register (EDMA_SSBR) The EDMA_SSBR provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set.
Page 396: Table 187. Edma_Cdsbr Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0046 Table 187. EDMA_CDSBR field descriptions Field Description Reserved. Clear DONE status bit. 0–15 Clear the corresponding channel’s DONE bit 16–63 Reserved 1–7 64–127 Clear all TCD DONE bits CDSB[0:6] Bit 2 (CDSB1) is not used. eDMA Interrupt Request Register (EDMA_IRQRL) The EDMA_IRQRL provide a bit map for the 16 channels signaling the presence of an interrupt request for each channel.
Page 397: Table 189. Edma_Erl Field Descriptions
RM0046 Enhanced Direct Memory Access (eDMA) eDMA Error Register (EDMA_ERL) The EDMA_ERL provides a bit map for the 16 channels signaling the presence of an error for each channel. EDMA_ERL maps to channels 15-0. The eDMA engine signals the occurrence of a error condition by setting the appropriate bit in this register.
Page 398: Table 190. Edma_Hrsl Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0046 Figure 191. EDMA Hardware Request Status Register Low (EDMA_HRSL) Address: Base + 0x0034 Access: User read/write Reset R HRS Reset Table 190. EDMA_HRSL field descriptions Field Description DMA Hardware Request Status 0 A hardware service request for channel n is not present. 16–31 1 A hardware service request for channel n is present.
Page 399: Table 191. Edma_Cprn Field Descriptions
RM0046 Enhanced Direct Memory Access (eDMA) Figure 192. eDMA Channel n Priority Register (EDMA_CPRn) Address: Base + 0x100 + n Access: User read/write CHPRI Reset — 1. The reset value for the channel priority fields, GRPPRI[0–1] and CHPRI[0–3] is the channel number for the priority register;...
Page 400 Enhanced Direct Memory Access (eDMA) RM0046 Table 192. TCDn 32-bit memory structure (continued) TCDn eDMA Bit Offset TCDn Field Name Word # Length Abbreviation Channel-to-channel Linking on Minor 0x1000 + (32 × n) + 160 CITER.E_LINK Loop Complete Current Major Iteration Count or CITER or 0x1000 + (32 ×...
Page 401: Table 193. Tcdn Field Descriptions
RM0046 Enhanced Direct Memory Access (eDMA) Figure 193. TCD structure Word 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Offset SADDR SMOD SSIZE DMOD DSIZE SOFF NBYTES SLAST...
Page 402 Enhanced Direct Memory Access (eDMA) RM0046 Table 193. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] Source data transfer size. 000 8-bit 001 16-bit 010 32-bit 37–39 SSIZE 011 64-bit 100 32-bit 0x4 [5:7] [0:2] 101 32-byte burst (64-bit x 4) 110 Reserved 111 Reserved The attempted specification of a ‘reserved’...
Page 403 RM0046 Enhanced Direct Memory Access (eDMA) Table 193. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] Current “major” iteration count or link channel number. If channel-to-channel linking is disabled (TCD.CITER.E_LINK = 0), then CITER – No channel-to-channel linking (or chaining) is performed after the inner minor [0:5] 161–166 loop is exhausted.
Page 404 Enhanced Direct Memory Access (eDMA) RM0046 Table 193. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] Enables channel-to-channel linking on minor loop complete. As the channel completes the inner minor loop, this flag enables the linking to another channel, defined by BITER.LINKCH[0:5].
Page 405 RM0046 Enhanced Direct Memory Access (eDMA) Table 193. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] Link channel number. If channel-to-channel linking on major loop complete is disabled (TCD.MAJOR.E_LINK = 0) then: – No channel-to-channel linking (or chaining) is performed after the outer major MAJOR.LINKC 242–247 loop counter is exhausted.
Page 406: Functional Description
Enhanced Direct Memory Access (eDMA) RM0046 Table 193. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the bit in the EDMA_ERQL when the current major iteration count reaches the halfway point.
Page 407: Edma Basic Data Flow
RM0046 Enhanced Direct Memory Access (eDMA) back into the local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn.CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation.
Page 408: Figure 194. Edma Operation, Part 1
Enhanced Direct Memory Access (eDMA) RM0046 basic flow as an eDMA peripheral request. The eDMA peripheral request input signal is registered internally and then routed through the eDMA engine, first through the control module, then into the program model/channel arbitration module. In the next cycle, the channel arbitration is performed, either using the fixed-priority or round-robin algorithm.
Page 409: Figure 195. Edma Operation, Part 2
RM0046 Enhanced Direct Memory Access (eDMA) eDMA SRAM Transfer Control Descriptor (TCD) Slave Write Address Slave Write Data SRAM TCD0 TCDn – 1* eDMA Engine Bus Read Data Program Model/ Channel Arbitration Address Control Data Path Path Slave Read Data Bus Write Data Bus Address *n = 16 channels...
Page 410: Edma Performance
Enhanced Direct Memory Access (eDMA) RM0046 eDMA SRAM Transfer Control Descriptor (TCD) Slave Write Address Slave Write Data SRAM TCD0 TCDn – 1* eDMA Engine Bus Read Data Program Model/ Channel Arbitration Address Control Data Path Slave Read Data Path Bus Write Data Bus Address *n = 16 channels...
Page 411: Table 194. Edma Peak Transfer Rates (Mb/Sec)
RM0046 Enhanced Direct Memory Access (eDMA) Table 194. eDMA peak transfer rates (MB/Sec) Internal SRAM-to- Internal SRAM-to- System Speed, Internal SRAM-to- 32-bit Slave-to- 32-bit Slave 32-bit Slave Transfer Size Internal SRAM Internal SRAM (buffering disabled) (buffering enabled) 66.7 MHz, 32-bit 66.7 66.7 53.3...
Page 412: Table 195. Edma Peak Request Rate (Mreq/Sec)
Enhanced Direct Memory Access (eDMA) RM0046 particular, this metric also reflects the time required to activate the channel. The eDMA design supports the following hardware service request sequence: ● Cycle 1: eDMA peripheral request is asserted. ● Cycle 2: The eDMA peripheral request is registered locally in the eDMA module and qualified.
Page 413 RM0046 Enhanced Direct Memory Access (eDMA) Table 195. eDMA peak request Rate (MReq/sec) (continued) Request Rate System Frequency Request Rate (MHz) (Zero Wait States) (with Wait States) 133.3 14.8 11.6 150.0 16.6 13.0 A general formula to compute the peak request rate (with overlapping requests) is: Equation 13 PEAKreq = freq / [entry + (1 + read_ws) + (1 + write_ws) + exit] where:...
Page 414: Initialization / Application Information
Enhanced Direct Memory Access (eDMA) RM0046 request rate calculations above, the arbitration and request registering is absorbed in or overlap the previous executing channel. Note: When channel linking or scatter/gather is enabled, a two-cycle delay is imposed on the next channel selection and startup.
Page 415: Figure 197. Example Of Multiple Loop Iterations
RM0046 Enhanced Direct Memory Access (eDMA) Table 196. TCD primary control and status fields (continued) TCD Field Description Name INT_HALF Control bit to enable interrupt when major loop is half complete INT_MAJ Control bit to enable interrupt when major loop completes Figure 197 shows how each DMA request initiates one minor loop transfer (iteration) without CPU intervention.
Page 416: Dma Programming Errors
Enhanced Direct Memory Access (eDMA) RM0046 xADDR: xSIZE: Minor Loop Offset (xOFF): Number of (Starting Address) (Size of one data (NBYTES in bytes added to current transfer) Minor Loop, often address after each transfer the same value (Often the same value •...
Page 417: Dma Arbitration Mode Considerations
RM0046 Enhanced Direct Memory Access (eDMA) Table 197. DMA request summary for eDMA (continued) DMA Request Source Description DMA_MUX_CHCONFIG6_SOURCE DMA_MUX.CHCONFIG6[SOURCE] DMA MUX channel 6 source DMA_MUX_CHCONFIG7_SOURCE DMA_MUX.CHCONFIG7[SOURCE] DMA MUX channel 7 source DMA_MUX_CHCONFIG8_SOURCE DMA_MUX.CHCONFIG8[SOURCE] DMA MUX channel 8 source DMA_MUX_CHCONFIG9_SOURCE DMA_MUX.CHCONFIG9[SOURCE] DMA MUX channel 9 source DMA_MUX_CHCONFIG10_SOURCE...
Page 418 Enhanced Direct Memory Access (eDMA) RM0046 to match the size of the transfer; one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. TCD.CITER = TCD.BITER = 1 TCD.NBYTES = 16 TCD.SADDR = 0x1000 TCD.SOFF = 1...
Page 419 RM0046 Enhanced Direct Memory Access (eDMA) EDMA_ERQR, channel service requests are initiated by the slave device (set ERQR after TCD; TCD.START = 0). TCD.CITER = TCD.BITER = 2 TCD.NBYTES = 16 TCD.SADDR = 0x1000 TCD.SOFF = 1 TCD.SSIZE = 0 TCD.SLAST = –32 TCD.DADDR = 0x2000 TCD.DOFF = 4...
Page 420: Table 198. Modulo Feature Example
Enhanced Direct Memory Access (eDMA) RM0046 The eDMA goes idle or services the next channel. Second hardware (eDMA peripheral request) requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1. 12.
Page 421: Tcd Status
RM0046 Enhanced Direct Memory Access (eDMA) 18.7.6 TCD status Minor loop complete There are two methods to test for minor loop completion when using software initiated service requests. The first method is to read the TCD.CITER field and test for a change. Another method can be extracted from the following sequence.
Page 422: Channel Linking
Enhanced Direct Memory Access (eDMA) RM0046 and/or group priorities are treated as equal (or more exactly, constantly rotating) when round-robin arbitration mode is selected. The TCD.ACTIVE bit for the preempted channel remains asserted throughout the preemption. The preempted channel is temporarily suspended while the preempting channel executes one iteration of the major loop.
Page 423: Table 199. Channel Linking Parameters
RM0046 Enhanced Direct Memory Access (eDMA) Table 199. Channel linking parameters Desired Link TCD Control Field Name Description Behavior Enable channel-to-channel linking on minor loop citer.e_link completion (current iteration) Link at end of Minor Loop Link channel number when linking at end of minor citer.linkch loop (current iteration) Enable channel-to-channel linking on major loop...
Page 424: Figure 199. Dma Mux Block Diagram
DMA Channel Mux (DMA_MUX) RM0046 DMA Channel Mux (DMA_MUX) 19.1 Introduction 19.1.1 Overview The DMA Mux allows to route a configurable amount of DMA sources (slots) to a configurable amount of DMA channels. This is illustrated in Figure 199. DMA Channel #0 DMA_CH_MUX Source #1 DMA Channel #1...
Page 425: Table 200. Dma_Mux Memory Map
RM0046 DMA Channel Mux (DMA_MUX) 19.1.3 Modes of operation The following operation modes are available: ● Disabled Mode In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA Channel Mux.
Page 426 DMA Channel Mux (DMA_MUX) RM0046 Table 200. DMA_MUX memory map (continued) Offset from DMA_MUX_BASE Register Location (0xFFFD_C000) 0x0005 Channel #5 Configuration (CHCONFIG5) on page 19-427 0x0006 Channel #6 Configuration (CHCONFIG6) on page 19-427 0x0007 Channel #7 Configuration (CHCONFIG7) on page 19-427 0x0008 Channel #8 Configuration (CHCONFIG8) on page 19-427...
Page 427: Table 201. Chconfig#X Field Descriptions
RM0046 DMA Channel Mux (DMA_MUX) 19.3.2 Register descriptions Channel Configuration Registers Each of the DMA channels can be independently enabled/disabled and associated with one of the #SRC + #ALE total DMA sources in the system. Figure 200. Channel Configuration Registers (CHCONFIG#n) Address: Base + #n Access: User read/write ENBL...
Page 428: Table 203. Dma Channel Mapping
DMA Channel Mux (DMA_MUX) RM0046 19.4 DMA request mapping Table 203. DMA channel mapping DMA_CH_MUX DMA requesting Module DMA Mux input # channel module DSPI_0 DSPI_0 TX DMA MUX Source #1 DSPI_0 DSPI_0 RX DMA MUX Source #2 DSPI_1 DSPI_1 TX DMA MUX Source #3 DSPI_1 DSPI_1 RX...
Page 429: Functional Description
RM0046 DMA Channel Mux (DMA_MUX) 19.5 Functional description This section provides a complete functional description of the DMA Mux. The primary purpose of the DMA Mux is to provide flexibility in the system’s use of the available DMA channels. As such, configuration of the DMA Mux is intended to be a static procedure done during execution of the system boot code.
Page 430: Figure 201. Dma Mux Triggered Channels Diagram
DMA Channel Mux (DMA_MUX) RM0046 Source #1 Source #2 Source #3 DMA Channel #0 Trigger #1 Trigger #2 Source #21 DMA Channel #3 Trigger #4 Always #1 Always #9 Figure 201. DMA mux triggered channels diagram The DMA channel triggering capability allows the system to “schedule” regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor.
Page 431: Figure 203. Dma Mux Channel Triggering: Ignored Trigger
RM0046 DMA Channel Mux (DMA_MUX) Peripheral Request Trigger DMA Request Figure 203. DMA mux channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: ●...
Page 432: Figure 204. Dma Mux Channel 4-15 Block Diagram
DMA Channel Mux (DMA_MUX) RM0046 19.5.2 DMA channels with no triggering capability Channels 4–15 of the DMA Mux provide the normal routing functionality as described in Section 19.1.3, “Modes of operation. Source #1 Source #2 Source #3 DMA Channel #4 Source #21 DMA Channel #15 Always #1...
Page 433 RM0046 DMA Channel Mux (DMA_MUX) Determine with which DMA channel the source will be associated. Remember that only the first four DMA channels have periodic triggering capability. Clear the ENBL and TRIG bits of the DMA channel. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.
Page 434 DMA Channel Mux (DMA_MUX) RM0046 #include "registers.h" *CHCONFIG2 = 0x00; *CHCONFIG2 = 0xC5; Enabling a source without periodic triggering: Determine with which DMA channel the source will be associated. Remember that only DMA channels 0–7 have periodic triggering capability. Clear the ENBL and TRIG bits of the DMA channel. Ensure that the DMA channel is properly configured in the DMA.
Page 435 RM0046 DMA Channel Mux (DMA_MUX) volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCONFIG2 = 0x00; *CHCONFIG2 = 0x85; Disabling a source: A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCONFIG registers.
Page 436 DMA Channel Mux (DMA_MUX) RM0046 volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D);...
Page 437: Figure 205. Dspi Block Diagram
RM0046 Deserial Serial Peripheral Interface (DSPI) Deserial Serial Peripheral Interface (DSPI) 20.1 Introduction This chapter describes the deserial serial peripheral interface (DSPI), which provides a synchronous serial bus for communication between the MCU and an external peripheral device. The SPC560P40/34 implements the modules DSPI0, 1 and 2. The “x” appended to signal names signifies the module to which the signal applies.
Page 438: Figure 206. Dspi With Queues And Edma
Deserial Serial Peripheral Interface (DSPI) RM0046 20.3 Overview The register content is transmitted using an SPI protocol. There are three DSPI modules (DSPI_0, DSPI_1, and DSPI_2) on the device. The modules are identical except that DSPI_0 has four additional chip select (CS) lines. For queued operations, the SPI queues reside in internal SRAM that is external to the DSPI.
Page 439: Modes Of Operation
RM0046 Deserial Serial Peripheral Interface (DSPI) The DSPI supports these SPI features: ● Full-duplex, three-wire synchronous transfers ● Master and slave modes ● Buffered transmit and receive operation using the TX and RX FIFOs, with depths of 5 entries ● Visibility into TX and RX FIFOs for ease of debugging ●...
Page 440: Master Mode
Deserial Serial Peripheral Interface (DSPI) RM0046 The module-specific modes are entered by host software writing to a register. The MCU- specific mode is controlled by signals external to the DSPI. The MCU-specific mode is a mode that the entire device may enter, in parallel to the DSPI being in one of its module- specific modes.
Page 441: Table 204. Signal Properties
RM0046 Deserial Serial Peripheral Interface (DSPI) Table 204. Signal properties Function Name I/O type Master mode Slave mode CS0_x Output / input Peripheral chip select 0 Slave select CS1:3_x Output Peripheral chip select 1–3 Unused (DSPI 0: CS1:3_0, CS5_0) CS4_x Output Peripheral chip select 4 Master trigger...
Page 442: Table 205. Dspi Memory Map
Deserial Serial Peripheral Interface (DSPI) RM0046 CS5 is not used in slave mode. On DSPI_0, this is CS7. Serial Input (SIN_x) SIN_x is a serial data input signal. Serial Output (SOUT_x) SOUT_x is a serial data output signal. Serial Clock (SCK_x) SCK_x is a serial communication clock signal.
Page 443: Registers Description
RM0046 Deserial Serial Peripheral Interface (DSPI) Table 205. DSPI memory map (continued) Offset from DSPI_BASE 0xFFF9_0000 (DSPI_0) Register Location 0xFFF9_4000 (DSPI_1) 0xFFF9_8000 (DSPI_2) DSPI_RSER—DSPI DMA/interrupt request select and 0x0030 on page 20-455 enable register 0x0034 DSPI_PUSHR—DSPI push TX FIFO register on page 20-456 0x0038 DSPI_POPR—DSPI pop RX FIFO register...
Page 444: Table 206. Dspix_Mcr Field Descriptions
Deserial Serial Peripheral Interface (DSPI) RM0046 Figure 207. DSPI Module Configuration Register (DSPIx_MCR) Address: Base + 0x0000 Access: User read/write Reset HALT Reset Table 206. DSPIx_MCR field descriptions Field Description Master/slave mode select Configures the DSPI for master mode or slave mode. MSTR 0 DSPI is in slave mode.
Page 445 RM0046 Deserial Serial Peripheral Interface (DSPI) Table 206. DSPIx_MCR field descriptions (continued) Field Description Modified timing format enable Enables a modified transfer format to be used. Refer to Section , “Modified SPI transfer format (MTFE = 1, CPHA = 1) for more information.
Page 446 Deserial Serial Peripheral Interface (DSPI) RM0046 Table 206. DSPIx_MCR field descriptions (continued) Field Description Clear TX FIFO Flushes the TX FIFO. Write a 1 to the CLR_TXF bit to clear the TX FIFO counter. The CLR_TXF bit is always read as 0. CLR_TXF 0 Do not clear the TX FIFO counter.
Page 447: Table 207. Dspix_Tcr Field Descriptions
RM0046 Deserial Serial Peripheral Interface (DSPI) Figure 208. DSPI Transfer Count Register (DSPIx_TCR) Address: Base + 0x0008 Access: User read/write SPI_TCNT[0:15] Reset Reset Table 207. DSPIx_TCR field descriptions Field Description SPI transfer counter Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is incremented every time 0–15 the last bit of an SPI frame is transmitted.
Page 448: Table 208. Dspix_Ctarn Field Descriptions
Deserial Serial Peripheral Interface (DSPI) RM0046 Figure 209. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) Base + 0x000C (DSPIx_CTAR0) Base + 0x001C (DSPIx_CTAR4) Base + 0x0010 (DSPIx_CTAR1) Base + 0x0020 (DSPIx_CTAR5) Address: Access: User read/write Base + 0x0014 (DSPIx_CTAR2) Base + 0x0024 (DSPIx_CTAR6) Base + 0x0018 (DSPIx_CTAR3) Base + 0x0028 (DSPIx_CTAR7)
Page 449 RM0046 Deserial Serial Peripheral Interface (DSPI) Table 208. DSPIx_CTARn field descriptions (continued) Field Descriptions LSB First The LSBFE bit selects if the LSB or MSB of the frame is transferred first. This bit is only used in Master Mode. LSBFE 0 Data is transferred MSB first.
Page 450 Deserial Serial Peripheral Interface (DSPI) RM0046 Table 208. DSPIx_CTARn field descriptions (continued) Field Descriptions Baud Rate Prescale The PBR field selects the prescaler value for the baud rate. This field is only used in Master Mode. The baud rate is the frequency of the Serial Communications Clock (SCK). The system clock is divided by the prescaler value before the baud rate selection takes place.
Page 451: Table 209. Dspi Sck Duty Cycle
RM0046 Deserial Serial Peripheral Interface (DSPI) Table 208. DSPIx_CTARn field descriptions (continued) Field Descriptions Baud Rate Scaler The BR field selects the scaler value for the baud rate. This field is only used in Master Mode. The pre-scaled system clock is divided by the baud rate scaler to generate the frequency of the SCK.
Page 452: Table 211. Dspi Pcs To Sck Delay Scaler
Deserial Serial Peripheral Interface (DSPI) RM0046 Table 211. DSPI PCS to SCK delay scaler CSSCK PCS to SCK delay scaler value CSSCK PCS to sck delay scaler value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 0100 1100 8192 0101...
Page 453: Table 214. Dspi Baud Rate Scaler
RM0046 Deserial Serial Peripheral Interface (DSPI) Table 214. DSPI baud rate scaler Baud rate scaler value Baud rate scaler value 0000 1000 0001 1001 0010 1010 1024 0011 1011 2048 0100 1100 4096 0101 1101 8192 0110 1110 16384 0111 1111 32768 DSPI Status Register (DSPIx_SR)
Page 454 Deserial Serial Peripheral Interface (DSPI) RM0046 Table 215. DSPIx_SR field descriptions (continued) Field Description Reserved End of queue flag Indicates that transmission in progress is the last entry in a queue. The EOQF bit is set when the TX FIFO entry has the EOQ bit set in the command halfword and after the last incoming databit is sampled, but before the tASC delay starts.
Page 455: Table 216. Dspix_Rser Field Descriptions
RM0046 Deserial Serial Peripheral Interface (DSPI) Table 215. DSPIx_SR field descriptions (continued) Field Description TX FIFO counter 16–19 Indicates the number of valid entries in the TX FIFO. The TXCTR is incremented every time the TXCTR DSPI _PUSHR is written. The TXCTR is decremented every time an SPI command is executed [0:3] and the SPI data is transferred to the shift register.
Page 456 Deserial Serial Peripheral Interface (DSPI) RM0046 Table 216. DSPIx_RSER field descriptions (continued) Field Description DSPI finished request enable Enables the EOQF flag in the DSPIx_SR to generate an interrupt request. EOQF_RE 0 EOQF interrupt requests are disabled. 1 EOQF interrupt requests are enabled. Transmit FIFO underflow request enable The TFUF_RE bit enables the TFUF flag in the DSPIx_SR to generate an interrupt request.
Page 457: Table 217. Dspix_Pushr Field Descriptions
RM0046 Deserial Serial Peripheral Interface (DSPI) Note: TXDATA is used in master and slave modes. Figure 212. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) Address Base + 0x0034 Access: User read/write CONT CTAS Reset TXDATA Reset Table 217. DSPIx_PUSHR field descriptions Field Description Continuous peripheral chip select enable...
Page 458 Deserial Serial Peripheral Interface (DSPI) RM0046 Table 217. DSPIx_PUSHR field descriptions (continued) Field Description End of queue Provides a means for host software to signal to the DSPI that the current SPI transfer is the last in a queue. At the end of the transfer the EOQF bit in the DSPIx_SR is set. 0 The SPI data is not the last data to transfer.
Page 459: Table 218. Dspix_Popr Field Descriptions
RM0046 Deserial Serial Peripheral Interface (DSPI) Figure 213. DSPI POP RX FIFO Register (DSPIx_POPR) Address: Base + 0x0038 Access: User read-only Reset RXDATA Reset Table 218. DSPIx_POPR field descriptions Field Description 0–15 Reserved, must be cleared. 16–31 Received data RXDATA The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data pointer (POPNXTPTR).
Page 460: Table 219. Dspix_Txfrn Field Descriptions
Deserial Serial Peripheral Interface (DSPI) RM0046 Table 219. DSPIx_TXFRn field descriptions Field Description 0–15 Transmit command TXCMD Contains the command that sets the transfer attributes for the SPI data. Refer to Section , “DSPI PUSH TX FIFO Register (DSPIx_PUSHR) for details on the command field. [0:15] 16–31 Transmit data...
Page 461: Figure 216. Spi Serial Protocol Overview
RM0046 Deserial Serial Peripheral Interface (DSPI) The DCONF field in the DSPIx_MCR register determines the DSPI configuration. Refer to Table 206 for the DSPI configuration values. The DSPIx_CTAR0–DSPIx_CTAR7 registers hold clock and transfer attributes.The SPI configuration can select which CTAR to use on a frame by frame basis by setting the CTAS field in the DSPIx_PUSHR.
Page 462: Start And Stop Of Dspi Transfers
Deserial Serial Peripheral Interface (DSPI) RM0046 Master mode In master mode the DSPI can initiate communications with peripheral devices. The DSPI operates as bus master when the MSTR bit in the DSPIx_MCR is set. The serial communications clock (SCK) is controlled by the master DSPI. All three DSPI configurations are valid in master mode.
Page 463: Table 221. State Transitions For Start And Stop Of Dspi Transfers
RM0046 Deserial Serial Peripheral Interface (DSPI) RESET RUNNING TXRXS = 1 Power-on-Reset STOPPED TXRXS = 0 Figure 217. DSPI start and stop state diagram The transitions are described in Table 221. Table 221. State transitions for start and stop of DSPI transfers Transition # Current State Next State...
Page 464 Deserial Serial Peripheral Interface (DSPI) RM0046 The SPI configuration supports two module-specific modes; master mode and slave mode. The FIFO operations are similar for the master mode and slave mode. The main difference is that in master mode the DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO entry.
Page 465 RM0046 Deserial Serial Peripheral Interface (DSPI) FIFO by being shifted out or by flushing the TX FIFO. The TX FIFO counter field (TXCTR) in the DSPI status register (DSPIx_SR) indicates the number of valid entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data is transferred into the shift register from the TX FIFO.
Page 466: Figure 218. Communications Clock Prescalers And Scalers
Deserial Serial Peripheral Interface (DSPI) RM0046 DSPIx_RXFR0. For example, POPNXTPTR equal to two means that the DSPIx_RXFR2 contains the received SPI data that is returned when DSPIx_POPR is read. The POPNXTPTR field is incremented every time the DSPIx_POPR is read. POPNXTPTR rolls over every four frames on the MCU.
Page 467: Table 222. Baud Rate Computation Example
RM0046 Deserial Serial Peripheral Interface (DSPI) Equation 21  --------------------------------------------------------- - -------------------------------------------- SCK baud rate PBRPrescalerValue BRScalerValue Table 222 shows an example of a computed baud rate. Table 222. Baud rate computation example Prescaler value Scaler value DBR value Baud rate 100 MHz 0b00 0b0000...
Page 468: Table 225. Delay After Transfer Computation Example
Deserial Serial Peripheral Interface (DSPI) RM0046 Delay after transfer (t The delay after transfer is the length of time between negation of the CSx signal for a frame and the assertion of the CSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registers select the delay after transfer.
Page 469: Table 226. Peripheral Chip Select Strobe Assert Computation Example
RM0046 Deserial Serial Peripheral Interface (DSPI) Equation 26  PASC PASC Table 226 shows an example of the computed t delay. PCSSCK Table 226. Peripheral Chip Select strobe assert computation example PCSSCK Prescaler Delay before transfer 0b11 100 MHz 70.0 ns Table 227 shows an example of the computed the t delay.
Page 470: Figure 220. Dspi Transfer Timing Diagram (Mtfe = 0, Cpha = 0, Fmsz = 8)
Deserial Serial Peripheral Interface (DSPI) RM0046 Classic SPI transfer format (CPHA = 0) The transfer format shown in Figure 220 is used to communicate with peripheral SPI slave devices where the first data bit is available on the first clock edge. In this format, the master and slave sample their SIN_x pins on the odd-numbered SCK_x edges and change the data on their SOUT_x pins on the even-numbered SCK_x edges.
Page 471: Figure 221. Dspi Transfer Timing Diagram (Mtfe = 0, Cpha = 1, Fmsz = 8)
RM0046 Deserial Serial Peripheral Interface (DSPI) Classic SPI transfer format (CPHA = 1) The transfer format shown in Figure 221 is used to communicate with peripheral SPI slave devices that require the first SCK_x edge before the first data bit becomes available on the slave SOUT_x pin.
Page 472: Table 228. Delayed Master Sample Point
Deserial Serial Peripheral Interface (DSPI) RM0046 Modified SPI transfer format (MTFE = 1, CPHA = 0) In this modified transfer format both the master and the slave sample later in the SCK period than in classic SPI mode to allow for delays in device pads and board traces. These delays become a more significant fraction of the SCK period as the SCK period decreases with increasing baud rates.
Page 473: Figure 222. Dspi Modified Transfer Format (Mtfe = 1, Cpha = 0, F Sck = F Sys / 4)
RM0046 Deserial Serial Peripheral Interface (DSPI) System clock Slave sample Master sample Slave SOUT Master SOUT System clock System clock = CS to SCK delay. = After SCK delay. Figure 222. DSPI modified transfer format (MTFE = 1, CPHA = 0, f / 4) Modified SPI transfer format (MTFE = 1, CPHA = 1) At the start of a transfer the DSPI asserts the CS signal to the slave device.
Page 474: Figure 223. Dspi Modified Transfer Format (Mtfe = 1, Cpha = 1, F Sck = F Sys / 4)
Deserial Serial Peripheral Interface (DSPI) RM0046 System clock Slave sample Master sample Master SOUT Slave SOUT = CS to SCK delay. = After SCK delay. Figure 223. DSPI modified transfer format (MTFE = 1, CPHA = 1, f / 4) Continuous selection format Some peripherals must be deselected between every transfer.
Page 475: Figure 225. Example Of Continuous Transfer (Cpha = 1, Cont = 1)
RM0046 Deserial Serial Peripheral Interface (DSPI) When the CONT = 1 and the CS signal for the next transfer is the same as for the current transfer, the CS signal remains asserted for the duration of the two transfers. The delay between transfers (t ) is not inserted between the transfers.
Page 476: Figure 226. Polarity Switching Between Frames
Deserial Serial Peripheral Interface (DSPI) RM0046 System clock Frame 0 Frame 1 CPOL = 0 CPOL = 1 Figure 226. Polarity switching between frames 20.8.6 Continuous Serial communications clock The DSPI provides the option of generating a continuous SCK signal for slave peripherals that require a continuous clock.
Page 477: Figure 227. Continuous Sck Timing Diagram (Cont = 0)
RM0046 Deserial Serial Peripheral Interface (DSPI) (CPOL = 0) (CPOL = 1) Master SOUT Master SIN = 1 SCK. Figure 227. Continuous SCK timing diagram (CONT = 0) If the CONT bit in the TX FIFO entry is set, CS remains asserted between the transfers when the CS signal for the next transfer is the same as for the current transfer.
Page 478: Table 229. Interrupt And Dma Request Conditions
Deserial Serial Peripheral Interface (DSPI) RM0046 20.8.7 Interrupts/DMA requests The DSPI has conditions that can generate interrupt requests only, and conditions that can generate interrupts or DMA requests. Table 229 lists these conditions. Table 229. Interrupt and DMA request conditions Condition Flag Interrupt...
Page 479: Power Saving Features
RM0046 Deserial Serial Peripheral Interface (DSPI) operating in slave mode and SPI configuration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while the TFUF_RE bit in the DSPIx_RSER is set, an interrupt request is generated.
Page 480: Initialization And Application Information
Deserial Serial Peripheral Interface (DSPI) RM0046 20.9 Initialization and application information 20.9.1 Managing queues DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue management. Queues are primarily supported in SPI configuration. This section presents an example of how to manage queues for the DSPI.
Page 481: Table 230. Baud Rate Values
RM0046 Deserial Serial Peripheral Interface (DSPI) Table 230. Baud rate values Baud Rate divider prescaler values (DSPI_CTAR[PBR]) 25.0 MHz 16.7 MHz 10.0 MHz 7.14 MHz 12.5 MHz 8.33 MHz 5.00 MHz 3.57 MHz 8.33 MHz 5.56 MHz 3.33 MHz 2.38 MHz 6.25 MHz 4.17 MHz 2.50 MHz...
Page 482: Table 231. Delay Values
Deserial Serial Peripheral Interface (DSPI) RM0046 20.9.3 Delay settings Table 231 shows the values for the delay after transfer (t ) and CS to SCK delay (t ) that can be generated based on the prescaler values and the scaler values set in the DSPIx_CTARs.
Page 483: Figure 229. Tx Fifo Pointers And Counter
RM0046 Deserial Serial Peripheral Interface (DSPI) Figure 229 illustrates the concept of first-in and last-in FIFO entries along with the FIFO counter. Transmit next TX FIFO base data pointer – (TXNXTPTR) – Push TX FIFO register Entry A (first in) Entry B Entry C Entry D (last in)
Page 484 Deserial Serial Peripheral Interface (DSPI) RM0046 Equation 29 First-in entry address = RXFIFO base + 4 × (POPNXTPTR) The memory address of the last-in entry in the RX FIFO is computed by the following equation: Equation 30 Last-in entry address = RXFIFO base + 4 × [(RXCTR + POPNXTPTR – 1) modulo RXFIFO depth] where: RXFIFO base = base address of receive FIFO RXCTR = receive FIFO counter...
Page 485: Introduction
RM0046 LIN Controller (LINFlex) LIN Controller (LINFlex) 21.1 Introduction The LINFlex (Local Interconnect Network Flexible) controller interfaces the LIN network and supports the LIN protocol versions 1.3; 2.0 2.1; and J2602 in both Master and Slave modes. LINFlex includes a LIN mode that provides additional features (compared to standard UART) to ease LIN implementation, improve system robustness, minimize CPU load and allow slave node resynchronization.
Page 486: Features Common To Lin And Uart
LIN Controller (LINFlex) RM0046 21.2.3 Features common to LIN and UART ● Fractional baud rate generator ● 3 operating modes for power saving and configuration registers lock: – Initialization – Normal – Sleep ● 2 test modes: – Loop Back –...
Page 487: Figure 230. Lin Topology Network
RM0046 LIN Controller (LINFlex) Application LINFlex Controller Transceiver LIN Bus Figure 230. LIN topology network REGISTER MODEL / APPLICATION INTERFACE Message Buffer Interface CONFIGURATION CONTROL STATUS LIN control LIN status Baud rate SLAVE MESSAGE HANDLER Filter configuration MASTER MESSAGE HANDLER Identifier Filters LIN PROTOCOL HANDLER 1.
Page 488: Table 232. Error Calculation For Programmed Baud Rates
LIN Controller (LINFlex) RM0046 Equation 31 periph_set_1_clk Tx/ Rx baud = (16 × LFDIV) LFDIV is an unsigned fixed point number. The 12-bit mantissa is coded in the LINIBRR and the fraction is coded in the LINFBRR. The following examples show how to derive LFDIV from LINIBRR and LINFBRR register values: Example 11Deriving LFDIV from LINIBRR and LINFBRR register values If LINIBRR = 27d and LINFBRR = 12d, then...
Page 489: Figure 232. Linflex Operating Modes
RM0046 LIN Controller (LINFlex) 21.5 Operating modes LINFlex has three main operating modes: Initialization, Normal and Sleep. After a hardware reset, LINFlex is in Sleep mode to reduce power consumption. The software instructs LINFlex to enter Initialization mode or Sleep mode by setting the INIT bit or SLEEP bit in the LINCR1.
Page 490: Figure 233. Linflex In Loop Back Mode
LIN Controller (LINFlex) RM0046 On LIN bus activity detection, hardware automatically performs the wake-up sequence by clearing the SLEEP bit if the AWUM bit in the LINCR1 is set. To exit from Sleep mode if the AWUM bit is cleared, software clears the SLEEP bit when a wake-up event occurs. 21.6 Test modes Two test modes are available to the user: Loop Back mode and Self Test mode.
Page 491: Table 233. Linflex Memory Map
RM0046 LIN Controller (LINFlex) LINFlex LINTX LINRX Figure 234. LINFlex in self test mode 21.7 Memory map and registers description 21.7.1 Memory map See the “Memory map” chapter of this reference manual for the base addresses for the LINFlex modules. Table 233 shows the LINFlex memory map.
Page 492: Figure 235. Lin Control Register 1 (Lincr1)
LIN Controller (LINFlex) RM0046 Table 233. LINFlex memory map (continued) Address offset Register Location 0x0044 Identifier filter match index (IFMI) on page 21-514 0x0048 Identifier filter mode register (IFMR) on page 21-514 0x004C Identifier filter control register 0 (IFCR0) on page 21-516 0x0050 Identifier filter control register 1 (IFCR1) on page 21-517...
Page 493: Table 234. Lincr1 Field Descriptions
RM0046 LIN Controller (LINFlex) Table 234. LINCR1 field descriptions Field Description Checksum calculation disable This bit disables the checksum calculation (see Table 235). 0 Checksum calculation is done by hardware. When this bit is 0, the LINCFR is read-only. 1 Checksum calculation is disabled. When this bit is set the LINCFR is read/write. User can program this register to send a software-calculated CRC (provided CFD is 0).
Page 494: Table 235. Checksum Bits Configuration
LIN Controller (LINFlex) RM0046 Table 234. LINCR1 field descriptions (continued) Field Description Loop Back Mode This bit controls the Loop Back mode. For more details see Section 21.6.1, Loop Back mode. 0 Loop Back mode disable. LBKM 1 Loop Back mode enable. Note: This bit can be written in Initialization mode only.
Page 495: Table 237. Operating Mode Selection
RM0046 LIN Controller (LINFlex) Table 236. LIN master break length selection (continued) Length 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit...
Page 496: Table 238. Linier Field Descriptions
LIN Controller (LINFlex) RM0046 Table 238. LINIER field descriptions Field Description Stuck at Zero Interrupt Enable SZIE 0 No interrupt when SZF bit in LINESR or UARTSR is set. 1 Interrupt generated when SZF bit in LINESR or UARTSR is set. Output Compare Interrupt Enable OCIE 0 No interrupt when OCF bit in LINESR or UARTSR is set.
Page 497: Figure 237. Lin Status Register (Linsr)
RM0046 LIN Controller (LINFlex) Table 238. LINIER field descriptions (continued) Field Description Header Received Interrupt Enable HRIE 0 No interrupt when a valid LIN header has been received. 1 Interrupt generated when a valid LIN header has been received, that is, HRF bit in LINSR is set. LIN status register (LINSR) Figure 237.
Page 498: Table 239. Linsr Field Descriptions
LIN Controller (LINFlex) RM0046 Table 239. LINSR field descriptions Field Description LIN modes / normal mode states 0000: Sleep mode LINFlex is in Sleep mode to save power consumption. 0001: Initialization mode LINFlex is in Initialization mode. Normal mode states 0010: Idle This state is entered on several events: –...
Page 499 RM0046 LIN Controller (LINFlex) Table 239. LINSR field descriptions (continued) Field Description Release Message Buffer 0 Buffer is free. 1 Buffer ready to be read by software. This bit must be cleared by software after reading data received in the buffer. This bit is cleared by hardware in Initialization mode.
Page 500: Table 240. Linesr Field Descriptions
LIN Controller (LINFlex) RM0046 Table 239. LINSR field descriptions (continued) Field Description Header Reception Flag This bit is set by hardware and indicates a valid header reception is completed. This bit must be cleared by software. This bit is reset by hardware in Initialization mode and at end of completed or aborted frame. Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is to say:–All filters are inactive and BF bit in LINCR1 is set...
Page 501: Figure 239. Uart Mode Control Register (Uartcr)
RM0046 LIN Controller (LINFlex) Table 240. LINESR field descriptions (continued) Field Description Checksum Error Flag This bit is set by hardware and indicates that the received checksum does not match the hardware calculated checksum. This bit is cleared by software. Note: This bit is never set if CCD or CFD bit in LINCR1 is set.
Page 502: Table 241. Uartcr Field Descriptions
LIN Controller (LINFlex) RM0046 Table 241. UARTCR field descriptions Field Description Transmitter Data Field length This field sets the number of bytes to be transmitted in UART mode. It can be programmed only when the UART bit is set. TDFL[0:1] = Transmit buffer size – 1. TDFL 00 Transmit buffer size = 1.
Page 503: Table 242. Uartsr Field Descriptions
RM0046 LIN Controller (LINFlex) UART mode status register (UARTSR) Figure 240. UART mode status register (UARTSR) Offset: 0x0014 Access: User read/write Reset R SZF OCF PE3 PE0 RMB FEF BOF RPS WUF DRF DTF W w1c Reset Table 242. UARTSR field descriptions Field Description Stuck at Zero Flag...
Page 504 LIN Controller (LINFlex) RM0046 Table 242. UARTSR field descriptions (continued) Field Description Release Message Buffer 0 Buffer is free. 1 Buffer ready to be read by software. This bit must be cleared by software after reading data received in the buffer. This bit is cleared by hardware in Initialization mode.
Page 505: Table 243. Lintcsr Field Descriptions
RM0046 LIN Controller (LINFlex) LIN timeout control status register (LINTCSR) Figure 241. LIN timeout control status register (LINTCSR) Offset: 0x0018 Access: User read/write Reset LTOM IOT TOCE Reset Table 243. LINTCSR field descriptions Field Description LIN timeout mode 0 LIN timeout mode (header, response and frame timeout detection). LTOM 1 Output compare mode.
Page 506: Table 244. Linocr Field Descriptions
LIN Controller (LINFlex) RM0046 LIN output compare register (LINOCR) Figure 242. LIN output compare register (LINOCR) Offset: 0x001C Access: User read/write Reset Reset 1. If LINTCSR[LTOM] = 0, this field is read-only. Table 244. LINOCR field descriptions Field Description Output compare 2 value These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR.
Page 507: Table 245. Lintocr Field Descriptions
RM0046 LIN Controller (LINFlex) Table 245. LINTOCR field descriptions Field Description Response timeout value This field contains the response timeout duration (in bit time) for 1 byte. The reset value is 0xE = 14, corresponding to T = 1.4 × T Response_Maximum Response_Nominal Header timeout value...
Page 508: Table 247. Linibrr Field Descriptions
LIN Controller (LINFlex) RM0046 LIN integer baud rate register (LINIBRR) Figure 245. LIN integer baud rate register (LINIBRR) Offset: 0x0028 Access: User read/write Reset DIV_M Reset Table 247. LINIBRR field descriptions Field Description LFDIV mantissa DIV_M This field defines the LINFlex divider (LFDIV) mantissa value (see Table 248).
Page 509: Table 249. Lincfr Field Descriptions
RM0046 LIN Controller (LINFlex) LIN checksum field register (LINCFR) Figure 246. LIN checksum field register (LINCFR) Offset: 0x002C Access: User read/write Reset Reset Table 249. LINCFR field descriptions Field Description Checksum bits When LINCR1[CCD] = 0, this field is read-only. When LINCR1[CCD] = 1, this field is read/write. Table 235.
Page 510: Table 250. Lincr2 Field Descriptions
LIN Controller (LINFlex) RM0046 Table 250. LINCR2 field descriptions Field Description Idle on Bit Error 0 Bit error does not reset LIN state machine. IOBE 1 Bit error reset LIN state machine. This bit can be set/cleared in Initialization mode only. Idle on Identifier Parity Error 0 Identifier Parity error does not reset LIN state machine.
Page 511: Table 251. Bidr Field Descriptions
RM0046 LIN Controller (LINFlex) Buffer identifier register (BIDR) Figure 248. Buffer identifier register (BIDR) Offset: 0x0034 Access: User read/write Reset DIR CCS Reset Table 251. BIDR field descriptions Field Description Data Field Length This field defines the number of data bytes in the response part of the frame. DFL = Number of data bytes –...
Page 512: Table 252. Bdrl Field Descriptions
LIN Controller (LINFlex) RM0046 Buffer data register LSB (BDRL) Figure 249. Buffer data register LSB (BDRL) Offset: 0x0038 Access: User read/write DATA3 DATA2 Reset DATA1 DATA0 Reset Table 252. BDRL field descriptions Field Description Data Byte 3 DATA3 Data byte 3 of the data field. Data Byte 2 DATA2 Data byte 2 of the data field.
Page 513: Table 253. Bdrm Field Descriptions
RM0046 LIN Controller (LINFlex) Table 253. BDRM field descriptions Field Description Data Byte 7 DATA7 Data byte 7 of the data field. Data Byte 6 DATA6 Data byte 6 of the data field. Data Byte 5 DATA5 Data byte 5 of the data field. Data Byte 4 DATA4 Data byte 4 of the data field.
Page 514: Table 255. Ifmi Field Descriptions
LIN Controller (LINFlex) RM0046 Identifier filter match index (IFMI) Figure 252. Identifier filter match index (IFMI) Address: Base + 0x0044 Access: User read-only Reset IFMI[0:4] Reset Table 255. IFMI field descriptions Field Description 0:26 Reserved Filter match index IFMI[0:4] This register contains the index corresponding to the received identifier. It can be used to directly write or read the data in SRAM (see Section , Slave mode for more details).
Page 515: Table 256. Ifmr Field Descriptions
RM0046 LIN Controller (LINFlex) Table 256. IFMR field descriptions Field Description Filter mode (see Table 257). 0 Filters 2n and 2n + 1 are in identifier list mode. 1 Filters 2n and 2n + 1 are in mask mode (filter 2n + 1 is the mask for the filter 2n). Table 257.
Page 516: Table 258. Ifcr2N Field Descriptions
LIN Controller (LINFlex) RM0046 Identifier filter control register (IFCR2n) Figure 254. Identifier filter control register (IFCR2n) Offsets: 0x004C–0x0084 (8 registers) Access: User read/write Reset Reset Note: Register bit can be read in any mode, written only in Initialization mode Table 258. IFCR2n field descriptions Field Description Data Field Length...
Page 517: Table 259. Ifcr2N + 1 Field Descriptions
RM0046 LIN Controller (LINFlex) Identifier filter control register (IFCR2n + 1) Figure 255. Identifier filter control register (IFCR2n + 1) Offsets: 0x0050–0x0088 (8 registers) Access: User read/write Reset Reset Note: Register bit can be read in any mode, written only in Initialization mode Table 259.
Page 518: Figure 256. Uart Mode 8-Bit Data Frame
LIN Controller (LINFlex) RM0046 21.8 Functional description 21.8.1 UART mode The main features in the UART mode are ● Full duplex communication ● 8- or 9-bit data with parity ● 4-byte buffer for reception, 4-byte buffer for transmission ● 8-bit counter for timeout management 8-bit data frames: The 8th bit can be a data or a parity bit.
Page 519: Table 260. Message Buffer
RM0046 LIN Controller (LINFlex) Table 260. Message buffer Buffer data LIN mode UART mode register DATA0[0:7] DATA1[0:7] BDRL[0:31] Transmit buffer DATA2[0:7] DATA3[0:7] Transmit/Receive buffer DATA4[0:7] DATA5[0:7] BDRM[0:31] Receive buffer DATA6[0:7] DATA7[0:7] UART transmitter In order to start transmission in UART mode, you must program the UART bit and the transmitter enable (TXEN) bit in the UARTCR to 1.
Page 520: Lin Mode
LIN Controller (LINFlex) RM0046 Clock gating The LINFlex clock can be gated from the Mode Entry module (MC_ME). In UART mode, the LINFlex controller acknowledges a clock gating request once the data transmission and data reception are completed, that is, once the Transmit buffer is empty and the Receive buffer is full.
Page 521 RM0046 LIN Controller (LINFlex) Data reception (transceiver as subscriber) To receive data from a slave node, the master sends a header with the corresponding identifier. LINFlex stores the data received from the slave in the message buffer and stores the message status in the LINSR. If the response has been received successfully, the LINSR[DRF] is set.
Page 522 LIN Controller (LINFlex) RM0046 the BOF bit in the LINESR. Which message is lost depends on the buffer lock function control bit RBLM. ● If the buffer lock function control bit is cleared (LINCR1[RBLM] = 0) the old message in the buffer is overwritten by the most recent message.
Page 523 RM0046 LIN Controller (LINFlex) Typically, the application has to copy the data from the BDR to SRAM locations. To copy the data to the right location, the application has to identify the data by means of the identifier. To avoid this and to ease the access to the SRAM locations, the LINFlex controller provides a Filter Match Index.
Page 524 LIN Controller (LINFlex) RM0046 If a valid Break Field and Break Delimiter come before the end of the current header or at any time during a data field, the current header or data is discarded and the state machine synchronizes on this new break. Valid message A received or transmitted message is considered as valid when the data has been received or transmitted without error according to the LIN protocol.
Page 525: Table 261. Filter To Interrupt Vector Correlation
RM0046 LIN Controller (LINFlex) Identifier Filter Register Organization Identifier IFCRn Bit Mapping Identifier Filter Configuration Identifier Filter Mode Identifier List Mode Identifier IFCR2n IFM = 0 IFCR2n + 1 Identifier Mask Mode Identifier IFCR2n IFM = 1 IFCR2n + 1 Mask Figure 258.
Page 526: Figure 259. Identifier Match Index
LIN Controller (LINFlex) RM0046 Table 261. Filter to interrupt vector correlation Number of Number of active filters Number of active filters Interrupt vector active filters configured as TX configured as RX — TX interrupt on identifiers matching the filters, — RX interrupt on all other (a >...
Page 527: Figure 260. Lin Synch Field Measurement
RM0046 LIN Controller (LINFlex) measurement, the LINFlex state machine is stopped and no data is transferred to the data register. = Clock period periph_set_1_clk = 16.LFDIV.T = baud rate period periph_set_1_clk SM = Synch Measurement Register (19 bits) LIN Synch Field LIN Break Next Start...
Page 528: Bit Timeout Counter
LIN Controller (LINFlex) RM0046 Note that the LINFlex does not need to check if the next edge occurs slower than expected. This is covered by the check for deviation error on the full synch byte. Clock gating The LINFlex clock can be gated from the Mode Entry module (MC_ME). In LIN mode, the LINFlex controller acknowledges a clock gating request once the frame transmission or reception is completed.
Page 529: Table 262. Linflex Interrupt Control
RM0046 LIN Controller (LINFlex) OC1 checks T and T and OC2 checks T (see Figure 261). Header Response Frame When LINFlex moves from Break state to Break Delimiter state (see Section , LIN status register (LINSR)): ● OC1 is updated with the value of OC = CNT + HTO), Header Header...
Page 530 LIN Controller (LINFlex) RM0046 Table 262. LINFlex interrupt control (continued) Interrupt event Event flag bit Enable control bit Interrupt vector Wake-up interrupt WUPF WUPIE LIN State interrupt LSIE Buffer Overrun interrupt BOIE Framing Error interrupt FEIE Header Error interrupt HEIE Checksum Error interrupt CEIE Bit Error interrupt...
Page 531: Figure 262. Flexcan Block Diagram
RM0046 FlexCAN FlexCAN 22.1 Introduction The FlexCAN module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification. A general block diagram is shown in Figure 262, which describes the main subblocks implemented in the FlexCAN module, including two embedded memories, one for storing Message Buffers (MB) and another one for storing Rx Individual Mask Registers.
Page 532: Flexcan Module Features
FlexCAN RM0046 in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. 32 Message Buffers are supported.
Page 533: Modes Of Operation
RM0046 FlexCAN ● Independent of the transmission medium (an external transceiver is assumed) ● Short latency time due to an arbitration scheme for high-priority messages ● Low power modes, with programmable wake up 22.1.3 Modes of operation The FlexCAN module has four functional modes: Normal mode (User and Supervisor), Freeze mode, Listen-Only Mode, and Loop-Back mode.
Page 534: Table 263. Flexcan Signals
FlexCAN RM0046 22.2 External signal description 22.2.1 Overview The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are summarized in Table 263 and described in more detail in the next subsections. Table 263. FlexCAN signals Signal name Direction Description...
Page 535: Table 264. Flexcan Module Memory Map
RM0046 FlexCAN BCC bit in the MCR is negated, then the whole Rx Individual Mask Registers address range (0x0880–0x097F) is considered reserved space. Note: The individual Rx Mask per Message Buffer feature may not be available in low cost MCUs. Please consult the specific MCU documentation to find out if this feature is supported.
Page 536: Table 266. Message Buffer Mb0 Memory Mapping
FlexCAN RM0046 Table 265. FlexCAN register reset status (continued) Affected by hard Affected by soft Register reset reset Reserved Rx Global Mask (RXGMASK) Rx Buffer 14 Mask (RX14MASK) Rx Buffer 15 Mask (RX15MASK) Error Counter Register (ECR) Error and Status Register (ESR) Interrupt Masks 1 (IMASK1) Interrupt Flags 1 (IFLAG1) Serial Message Buffers (SMB0–SMB1) –...
Page 537: Table 267. Message Buffer Structure Field Description
RM0046 FlexCAN Figure 263. Message buffer structure 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CODE LENGTH TIME STAMP PRIO ID (Standard/Extended) ID (Extended) Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3...
Page 538: Table 268. Message Buffer Code For Rx Buffers
FlexCAN RM0046 Table 267. Message Buffer structure field description (continued) Field Description Local priority This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx PRIO buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
Page 539: Table 269. Message Buffer Code For Tx Buffers
RM0046 FlexCAN Table 268. Message buffer code for Rx buffers (continued) Rx Code Rx Code BEFORE AFTER Description Comment Rx New Frame Rx New Frame An EMPTY buffer was written with a new BUSY: Flexcan is updating 0010 frame (XY was 01). the contents of the MB.
Page 540: Rx Fifo Structure
FlexCAN RM0046 Table 270. MB0–MB31 addresses (continued) Address Register Address Register Base + 0x00D0 Base + 0x01D0 MB21 Base + 0x00E0 Base + 0x01E0 MB22 Base + 0x00F0 Base + 0x01F0 MB23 Base + 0x0100 Base + 0x0200 MB24 Base + 0x0110 Base + 0x0210 MB25 Base + 0x0120...
Page 541: Table 271. Id Table 0 - 7
RM0046 FlexCAN Figure 264. Rx FIFO structure 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LENGTH TIME STAMP ID (Standard/Extended) ID (Extended) Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4...
Page 542: Table 272. Rx Fifo Structure Field Description
FlexCAN RM0046 Table 272. Rx FIFO Structure field description Field Description Remote Frame This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID. 0 Remote Frames are rejected and data frames can be accepted. 1 Remote Frames can be accepted and data frames are rejected.
Page 543: Table 273. Mcr Field Descriptions
RM0046 FlexCAN Figure 265. Module Configuration Register (MCR) Address: Base + 0x0000 Access: User read/write NOT_ FRZ_ LPM_ RDY WAK SOFT ACK SUPV MDIS FRZ FEN HALT _MSK _RST _DIS Reset LPRI IDAM MAXMB O_EN Reset Table 273. MCR field descriptions Field Description Module Disable...
Page 544 FlexCAN RM0046 Table 273. MCR field descriptions (continued) Field Description Wake Up Interrupt Mask This bit enables the Wake Up Interrupt generation. WAK_MSK 0 Wake Up Interrupt is disabled. 1 Wake Up Interrupt is enabled. Soft Reset When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers.
Page 545 RM0046 FlexCAN Table 273. MCR field descriptions (continued) Field Description Warning Interrupt Enable When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated.
Page 546: Table 274. Idam Coding
FlexCAN RM0046 Table 273. MCR field descriptions (continued) Field Description ID Acceptance Mode 22–23 This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown in IDAM Table 274. Note that all elements of the table are configured at the same time by this field (they are all the same format).
Page 547: Table 275. Ctrl Field Descriptions
RM0046 FlexCAN Table 275. CTRL field descriptions Field Description Prescaler Division Factor This 8-bit field defines the ratio between the CPI clock frequency and the Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value, 0–7 the Sclock frequency is equal to the CPI clock frequency.
Page 548 FlexCAN RM0046 Table 275. CTRL field descriptions (continued) Field Description Tx Warning Interrupt Mask This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is negated.
Page 549 RM0046 FlexCAN Table 275. CTRL field descriptions (continued) Field Description Lowest Buffer Transmitted First This bit defines the ordering mechanism for Message Buffer transmission. When asserted, the LPRIO_EN bit does not affect the priority arbitration. LBUF 0 Buffer with highest priority is transmitted first. 1 Lowest number buffer is transmitted first.
Page 550: Table 276. Timer Field Descriptions
FlexCAN RM0046 Figure 267. Free Running Timer (TIMER) Address: Base + 0x0008 Access: User read/write Reset TIMER Reset Table 276. TIMER field descriptions Field Description TIMER Holds the value for this timer. Rx Global Mask register (RXGMASK) This register is provided for legacy support and for low cost MCUs that do not have the individual masking per Message Buffer feature.
Page 551: Table 277. Rxgmask Field Description
RM0046 FlexCAN Table 277. RXGMASK field description Field Description Mask Bits For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the 0–31 mask bits affect all bits programmed in the filter table (ID, IDE, RTR). MI31–MI0 0 The corresponding bit in the filter is “don’t care.”...
Page 552: Table 279. Rx15Mask Field Description
FlexCAN RM0046 When the BCC bit is negated, RX15MASK is used as acceptance mask for the Identifier in Message Buffer 15. When the FEN bit in the MCR is set (FIFO enabled), the RX15MASK also applies to element 7 of the ID filter table. This register has the same structure as the Rx Global Mask Register.
Page 553: Figure 271. Error Counter Register (Ecr)
RM0046 FlexCAN influence on the bus when in ‘Bus Off’ state. The following are the basic rules for FlexCAN bus state transitions. ● If the value of Tx_Err_Counter or Rx_Err_Counter increases to be greater than or equal to 128, the FLT_CONF field in the Error and Status Register is updated to reflect ‘Error Passive’...
Page 554: Table 280. Error And Status Register (Esr) Field Description
FlexCAN RM0046 Most bits in this register are read only, except TWRN_INT, RWRN_INT, BOFF_INT, and ERR_INT, that are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect). See Section 22.4.10, “Interrupts for more details. Figure 272.
Page 555 RM0046 FlexCAN Table 280. Error and Status Register (ESR) field description (continued) Field Description Acknowledge Error This bit indicates that an Acknowledge Error has been detected by the transmitter node, that is, a dominant bit has not been detected during the ACK SLOT. ACK_ERR 0 No such occurrence.
Page 556: Table 281. Fault Confinement State
FlexCAN RM0046 Table 280. Error and Status Register (ESR) field description (continued) Field Description Bus Off Interrupt This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control Register (BOFF_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
Page 557: Table 282. Imask1 Field Descriptions
RM0046 FlexCAN Table 282. IMASK1 field descriptions Field Description BUF31M–BUF0M — Buffer MB Mask Each bit enables or disables the respective FlexCAN Message Buffer (MB0 to MB31) Interrupt. 0–31 0 The corresponding buffer Interrupt is disabled. BUF31M – 1The corresponding buffer Interrupt is enabled. BUF0M Note: Setting or clearing a bit in the IMASK1 Register can assert or negate an interrupt...
Page 558: Figure 275. Rx Individual Mask Registers (Rximr0-Rximr31)
FlexCAN RM0046 Table 283. IFLAG1 field descriptions (continued) Field Description Buffer MB6 Interrupt or “FIFO Warning” If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag indicates that 4 out of 6 buffers of the FIFO are already occupied (FIFO almost full). BUF6I 0 No such occurrence.
Page 559: Table 284. Rximr0-Rximr31 Field Descriptions
RM0046 FlexCAN Table 284. RXIMR0–RXIMR31 field descriptions Field Description Mask Bits For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, 0–31 the mask bits affect all bits programmed in the filter table (ID, IDE, RTR). MI31–MI0 0 The corresponding bit in the filter is “don’t care.”...
Page 560: Functional Description
FlexCAN RM0046 22.4 Functional description 22.4.1 Overview The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and receiving CAN frames. The mailbox system is composed by a set of as many as 32 Message Buffers (MB) that store configuration and control data, time stamp, message ID and data (see Section 22.3.2, “Message buffer structure).
Page 561: Arbitration Process
RM0046 FlexCAN update it until the Interrupt Flag be negated by CPU. It means that the CPU must clear the corresponding IFLAG before starting to prepare this MB for a new transmission or reception. 22.4.3 Arbitration process The arbitration process is an algorithm executed by the MBM that scans the whole MB memory looking for the highest priority message to be transmitted.
Page 562 FlexCAN RM0046 (see Section , “Transmission abort mechanism). If backwards compatibility is desired (AEN in MCR negated), just write ‘1000’ to the Code field to inactivate the MB, but then the pending frame may be transmitted without notification (see Section , “Message Buffer deactivation).
Page 563: Matching Process
RM0046 FlexCAN available interrupt from FIFO, the CPU should service the received frame using the following procedure: Read the Control and Status word (optional – needed only if a mask was used for IDE and RTR bits) Read the ID field (optional – needed only if a mask was used) Read the Data field Clear the frames available interrupt (mandatory –...
Page 564: Data Coherence
FlexCAN RM0046 The matching algorithm described above can be changed to be the same one used in previous versions of the FlexCAN module. When the BCC bit in the MCR is negated, the matching algorithm stops at the first MB with a matching ID that it founds, whether this MB is free or not.
Page 565 RM0046 FlexCAN If the CPU writes the abort code before the transmission begins internally, then the write operation is not blocked, therefore the MB is updated and no interrupt flag is set. In this way the CPU just needs to read the abort code to make sure the active MB was deactivated. Although the AEN bit is asserted and the CPU wrote the abort code, in this case the MB is deactivated and not aborted, because the transmission did not start yet.
Page 566: Rx Fifo
FlexCAN RM0046 Message Buffer lock mechanism Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive process. When the CPU reads the Control and Status word of an “active not empty” Rx MB, FlexCAN assumes that the CPU wants to read the whole MB in an atomic operation, and thus it sets an internal lock flag for that MB.
Page 567: Can Protocol Related Features
RM0046 FlexCAN with the next frame in the queue, and then issue another interrupt to the CPU. If the FIFO is full and more frames continue to be received, an OVERFLOW interrupt is issued to the CPU and subsequent frames are not accepted until the CPU creates space in the FIFO by reading one or more frames.
Page 568: Figure 276. Can Engine Clocking Scheme
FlexCAN RM0046 Overload frames FlexCAN does transmit overload frames due to detection of following conditions on CAN bus: ● Detection of a dominant bit in the first/second bit of Intermission ● Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames) ●...
Page 569: Figure 277. Segments Within The Bit Time
RM0046 FlexCAN The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose period defines the ‘time quantum’ used to compose the CAN waveform. A time quantum is the atomic unit of time handled by the CAN engine. Equation 32 CANCLK --------------------------------------------------------...
Page 570: Table 286. Time Segment Syntax
FlexCAN RM0046 Table 286. Time segment syntax Syntax Description SYNC_SEG System expects transitions to occur on the bus during this period. Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. A node samples the bus at this point. If the three samples per bit option is Sample Point selected, then this point marks the position of the third sample.
Page 571: Table 288. Minimum Ratio Between Peripheral Clock Frequency And Can Bit Rate
RM0046 FlexCAN When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer memory during the available time slot. In order to have sufficient time to do that, the following requirements must be observed: ● A valid CAN bit timing must be programmed, as indicated in Table 287 ●...
Page 572: Interrupts
FlexCAN RM0046 Once out of Freeze Mode, FlexCAN tries to resynchronize to the CAN bus by waiting for 11 consecutive recessive bits. Module disable mode This low power mode is entered when the MDIS bit in the MCR is asserted. If the module is disabled during Freeze Mode, it shuts down the clocks to the CPI and MBM sub-modules, sets the LPM_ACK bit and negates the FRZ_ACK bit.
Page 573: Bus Interface
RM0046 FlexCAN Note: It must be guaranteed that the CPU only clears the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags that are set after entering the current interrupt service routine.
Page 574: Flexcan Initialization Sequence
FlexCAN RM0046 22.5.1 FlexCAN initialization sequence The FlexCAN module may be reset in three ways: ● MCU level hard reset, which resets all memory mapped registers asynchronously ● MCU level soft reset, which resets some of the memory mapped registers synchronously (refer to Table 264 to see which registers are affected by soft reset)
Page 575: Overview
RM0046 Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) 23.1 Overview 23.1.1 Device-specific features ● 1 ADC unit ● 10-bit resolution ● 16 input channels – 15 channels on 100-pin LQFP; 11 channels on 64-pin LQFP – Channel 15 dedicated to the internal 1.2 V rail ●...
Page 576: Figure 279. Adc Implementation Diagram
Analog-to-Digital Converter (ADC) RM0046 the same frequency of MC_PLL_CLK or is half of MC_PLL_CLK, depending on the value of the bit ADCLKSEL. ● CTUEN field in the MCR: Enables or disables CTU control mode ● Registers CDR[16..95] not used ● ADC channel 15 is internally connected to the core voltage 23.1.3 Device-specific implementation...
Page 577: Table 289. Configurations For Starting Normal Conversion
RM0046 Analog-to-Digital Converter (ADC) 23.3 Functional description 23.3.1 Analog channel conversion Two conversion modes are available within the ADC: ● Normal conversion ● Injected conversion Normal conversion This is the normal conversion that the user programs by configuring the normal conversion mask registers (NCMR).
Page 578: Figure 280. Normal Conversion Flow
Analog-to-Digital Converter (ADC) RM0046 Normal conversion operating modes Two operating modes are available for the normal conversion: ● One Shot ● Scan To enter one of these modes, it is necessary to program the MCR[MODE] bit. The first phase of the conversion process involves sampling the analog channel and the next phase involves the conversion phase when the sampled analog value is converted to digital as shown in Figure...
Page 579: Figure 281. Injected Sample/Conversion Sequence
RM0046 Analog-to-Digital Converter (ADC) Injected channel conversion A conversion chain can be injected into the ongoing normal conversion by configuring the Injected Conversion Mask Registers (JCMR). As with normal conversion, each channel can be selected individually. This injected conversion (which can occur only in One Shot mode) interrupts the normal conversion (which can be in One Shot or Scan mode).
Page 580: Analog Clock Generator And Conversion Timings
Analog-to-Digital Converter (ADC) RM0046 Abort conversion Two different abort functions are provided. ● The user can abort the ongoing conversion by setting the MCR[ABORT] bit. The current conversion is aborted and the conversion of the next channel of the chain is immediately started.
Page 581: Figure 282. Prescaler Simplified Block Diagram
RM0046 Analog-to-Digital Converter (ADC) MC_PLL_CLK MC_PLL_CLK Clock ADCClk MC_PLL_CLK/2 Prescaler CTU trigger signal ADCLKSEL ACKO ADCLKSEL = ‘0’ ADCLKSEL = ‘0’ (clock stretched) MC_PLL_CLK MC_PLL_CLK ADCClk ADCClk CTU trigger signal CTU trigger signal Figure 282. Prescaler simplified block diagram The clock stretching is implemented if and only if ADCLKSEL = 0 (and clock is half of the MC_PLL_CLK).
Page 582: Table 290. Adc Sampling And Conversion Timing At 5 V / 3.3 V For Adc0
Analog-to-Digital Converter (ADC) RM0046 0.5 cycles 2.5 cycles 10 cycles Sampling phase Successive approximation / evaluation phase Latching phase: The capacitors field input End of conversion switch is opened Note: Operating conditions — INPLATCH = 0, INPSAMP = 3, INPCMP = 1 and Fadc clk = 20 MHz Figure 283.
Page 583: Table 291. Max/Min Adc_Clk Frequency And Related Configuration Settings At 5 V / 3.3 V For Adc0
RM0046 Analog-to-Digital Converter (ADC) Table 290. ADC sampling and conversion timing at 5 V / 3.3 V for ADC0 (continued) Clock Ndelay sample eval conv conv INPSAMPLE INPCMP INPLATCH sample (MHz) (s) (s) (s) 0.063 0.500 8.000 0.625 1.188 19.000 0.031 0.500 16.000...
Page 584: Table 292. Values Of Wdgxh And Wdgxl Fields
Analog-to-Digital Converter (ADC) RM0046 23.3.5 Programmable analog watchdog Introduction The analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in Figure 284) specified by an upper and a lower threshold value named THRH and THRL respectively.
Page 585: Table 293. Example For Analog Watchdog Operation
RM0046 Analog-to-Digital Converter (ADC) WDGxH for high threshold violation is set. Thus, the user should avoid that situation as it could lead to misinterpretation of the watchdog interrupts. Analog watchdog functionality For each input channel the result of the comparison is reflected in the THROP bit in TRC register based on the converted analog values received by the analog watchdogs: ●...
Page 586: Power-Down Mode
Analog-to-Digital Converter (ADC) RM0046 The analog watchdog interrupts are handled by two registers WTISR (Watchdog Threshold Interrupt Status Register) and WTIMR (Watchdog Threshold Interrupt Mask Register) in order to check and enable the interrupt request to the INTC module. The Watchdog interrupt source sets two pending bits WDGxH and WDGxL in the WTISR for each of the channels being monitored.
Page 587: Table 294. Adc Digital Registers
RM0046 Analog-to-Digital Converter (ADC) Table 294. ADC digital registers Offset from base address Register name Location 0xFFE0_0000 0x0000 Main Configuration Register (MCR) on page 23-588 0x0004 Main Status Register (MSR) on page 23-590 0x0008–0x000F Reserved 0x0010 Interrupt Status Register (ISR) on page 23-591 0x0014–0x001F Reserved...
Page 588: Figure 285. Main Configuration Register (Mcr)
Analog-to-Digital Converter (ADC) RM0046 Table 294. ADC digital registers Offset from base address Register name Location 0xFFE0_0000 0x010C Channel 3 Data Register (CDR3) on page 23-601 0x0110 Channel 4 Data Register (CDR4) on page 23-601 0x0114 Channel 5 Data Register (CDR5) on page 23-601 0x0118 Channel 6 Data Register (CDR6)
Page 589: Table 295. Mcr Field Descriptions
RM0046 Analog-to-Digital Converter (ADC) Table 295. MCR field descriptions Field Description Overwrite enable This bit enables or disables the functionality to overwrite unread converted data. OWREN 0 Prevents overwrite of unread converted data; new result is discarded 1 Enables converted data to be overwritten by a new conversion Write left/right-aligned 0 The conversion data is written right-aligned.
Page 590: Table 296. Msr Field Descriptions
Analog-to-Digital Converter (ADC) RM0046 Table 295. MCR field descriptions (continued) Field Description Abort Conversion When this bit is set, the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked. If it is set during a scan chain, ABORT only the ongoing conversion is aborted and the next conversion is performed as planned.
Page 591: Figure 287. Interrupt Status Register (Isr)
RM0046 Analog-to-Digital Converter (ADC) Table 296. MSR field descriptions (continued) Field Description CTUSTART This status bit is used to signal that a CTU conversion is ongoing. Current conversion channel address CHADDR This status field indicates current conversion channel address. Auto-clock-off enable ACKO This status bit is used to signal if the Auto-clock-off feature is on.
Page 592: Table 297. Isr Field Descriptions
Analog-to-Digital Converter (ADC) RM0046 Table 297. ISR field descriptions Field Description End of CTU Conversion interrupt flag EOCTU When this bit is set, an EOCTU interrupt has occurred. End of Injected Channel Conversion interrupt flag JEOC When this bit is set, a JEOC interrupt has occurred. End of Injected Chain Conversion interrupt flag JECH When this bit is set, a JECH interrupt has occurred.
Page 593: Table 299. Wtisr Field Descriptions
RM0046 Analog-to-Digital Converter (ADC) Watchdog Threshold Interrupt Status Register (WTISR) Figure 289. Channel Interrupt Mask Register 0 (CIMR0) Address: Base + 0x0024 Access: User read/write Reset R CIM Reset Figure 290. Watchdog Threshold Interrupt Status Register (WTISR) Address: Base + 0x0030 Access: User read/write Reset Reset...
Page 594: Table 300. Wtimr Field Descriptions
Analog-to-Digital Converter (ADC) RM0046 Watchdog Threshold Interrupt Mask Register (WTIMR) Figure 291. Watchdog Threshold Interrupt Mask Register (WTIMR) Address: Base + 0x0034 Access: User read/write Reset Reset Table 300. WTIMR field descriptions Field Description This corresponds to the mask bit for the interrupt generated on the converted value being higher MSKWDGxH than the programmed higher threshold (for [x = 0..3]).
Page 595: Table 301. Dmae Field Descriptions
RM0046 Analog-to-Digital Converter (ADC) 23.4.4 DMA registers DMA Enable (DMAE) register The DMA Enable (DMAE) register sets up the DMA for use with the ADC. Figure 292. DMA Enable (DMAE) register Address: Base + 0x0040 Access: User read/write Reset Reset Table 301.
Page 596: Table 302. Dmarx Field Descriptions
Analog-to-Digital Converter (ADC) RM0046 DMA Channel Select Register (DMAR[0]) DMAR0 = Enable bits for channel 0 to 15 (precision channels) Figure 293. DMA Channel Select Register 0 (DMAR0) Address: Base + 0x0044 Access: User read/write Reset R DMA Reset Table 302. DMARx field descriptions Field Description DMA enable...
Page 597: Table 303. Trcx Field Descriptions
RM0046 Analog-to-Digital Converter (ADC) 23.4.5 Threshold registers Introduction The Threshold registers store the user programmable lower and upper thresholds’ values. The inverter bit and the mask bit for mask the interrupt are stored in the TRC registers. Threshold Control Register (TRCx, x = [0..3]) Figure 294.
Page 598: Table 304. Thrhlrx Field Descriptions
Analog-to-Digital Converter (ADC) RM0046 Threshold Register (THRHLR[0:3]) The four THRHLRn registers store the user-programmable thresholds’ 10-bit values. Figure 295. Threshold Register (THRHLR[0:3]) Base + 0x0060 (THRHLR0) Base + 0x0064 (THRHLR1) Address: Base + 0x0068 (THRHLR2) Base + 0x006C (THRHLR3) Access: User read/write THRH Reset THRL...
Page 599: Table 305. Ctr Field Descriptions
RM0046 Analog-to-Digital Converter (ADC) CTR[0] 23.4.6 Conversion Timing Registers CTR0 = associated to internal precision channels (from 0 to 15) Figure 296. Conversion Timing Registers CTR[0] Address: Base + 0x0094 (CTR0) Access: User read/write Reset OFFSHIFT INPCMP INPSAMP Reset Table 305. CTR field descriptions Field Description INPLATCH...
Page 600: Table 306. Ncmr Field Descriptions
Analog-to-Digital Converter (ADC) RM0046 Figure 297. Normal Conversion Mask Register 0 (NCMR0) Address: Base + 0x00A4 Access: User read/write Reset CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Reset Table 306. NCMR field descriptions Field Description Sampling enable...
Page 601: Table 308. Pdedr Field Descriptions
RM0046 Analog-to-Digital Converter (ADC) 23.4.8 Delay registers Power-Down Exit Delay Register (PDEDR) Figure 299. Power-Down Exit Delay Register (PDEDR) Address: Base + 0x00C8 Access: User read/write Reset PDED Reset Table 308. PDEDR field descriptions Field Description Delay between the power-down bit reset and the start of conversion. The delay is to allow time for the ADC power supply to settle before commencing conversions.
Page 602: Table 309. Cdr Field Descriptions
Analog-to-Digital Converter (ADC) RM0046 Figure 300. Channel Data Registers (CDR[0..26]) Address: See Table 294 Access: User read/write RESULT Reset CDATA[0:9] (MCR[WLSIDE] = 0) Reset CDATA[0:9] (MCR[WLSIDE] = 1) Reset Table 309. CDR field descriptions Field Description Used to notify when the data is valid (a new value has been written). It is automatically cleared when VALID data is read.
Page 603: Introduction
RM0046 Cross Triggering Unit (CTU) Cross Triggering Unit (CTU) 24.1 Introduction In PWM driven systems it is important to schedule the acquisition of the state variables with respect to PWM cycle. State variables are obtained through the following peripherals: ADC, position counter (for example, quadrature decoder, resolver and sine-cos sensor) and PWM duty cycle decoder.
Page 604: Figure 301. Cross Triggering Unit Diagram
Cross Triggering Unit (CTU) RM0046 CTU Clock (as PWM) Prescaler TRIGGER_0 PWM_REL ADC_CMD_0 PWM_ODD_x NEXT_CMD_0 FIFO_0 Trigger Scheduler PWM_EVEN_x Generator TRIGGER_1 Subunit Subunit ADC_CMD_1 NEXT_CMD_1 RPWM_x FIFO_1 ETIMER0_IN ETIMER0_TRG ETIMER1_TRG EXT_IN EXT_TRG Figure 301. Cross triggering unit diagram The CTU consists of two subunits: ●...
Page 605: Figure 302. Tgs In Triggered Mode
RM0046 Cross Triggering Unit (CTU) 24.3.2 Trigger generator subunit (TGS) The trigger generator subunit has the following two modes: ● Triggered mode—Each event source for the incoming signals can generate as many as eight trigger event outputs. For the ADC, a commands list is entered by the CPU, and each event source can generate as many as eight commands or streams of commands.
Page 606: Figure 303. Example Timing For Tgs In Triggered Mode
Cross Triggering Unit (CTU) RM0046 double-buffered register (TGSCRR), during the control cycle n – 1 and reloads all the double-buffered registers (such as Trigger Compare registers, TGSCR, TGSCRR itself). The triggers list registers consist of eight compare registers. Each triggers list register is associated with a comparator.
Page 607: Figure 304. Tgs In Sequential Mode
RM0046 Cross Triggering Unit (CTU) CTU Clock (as PWM) TGS Counter Compare Register TGS Counter Comparator PWM_REL TGS Counter STOP Signal PWM_ODD_x Prescaler (1, 2, 3, 4) TGS Counter PWM_EVEN_x Event Signal TGS Counter Reload Register RPWM_x ETIMER0_IN Triggers Compare Registers EXT_IN Comparators (double-buffered)
Page 608: Figure 306. Tgs Counter Cases
Cross Triggering Unit (CTU) RM0046 operation to stop the TGS counter is not enabled during the first counting cycle, in order to allow the counting, if the value of the TGSCRR is the same as the value of the TGSCCR. TGS Counter—Case 1 Value in TGSCCR TGS Counter...
Page 609 RM0046 Cross Triggering Unit (CTU) If two events at the same time are linked to the same output only one output is generated and an error is provided. The output is generated using the trigger with the lowest index. For example, if trigger 0 and trigger 1 are linked to the ADC output and they occur together, an error is generated and the output linked with the trigger 0 is generated.
Page 610: Figure 307. Scheduler Subunit
Cross Triggering Unit (CTU) RM0046 CTU Clock TRIGGER_0 Prescaler ADC_CMD_0 (1, 2, 3, 4) ADC Command NEXT_CMD_0 Generator TRIGGER_1 ADC_CMD_1 NEXT_CMD_1 ADC Commands List Registers Subunit Clock (double-buffered) Ready Trigger Trigger 0..7 FIFO_0 0..7 FIFOs FIFO_1 Subunit Clock ADC Commands List Control Registers (double-buffered) ETIMER0_TRG eT1 Trigger...
Page 611: Table 310. Adc Commands Translation
RM0046 Cross Triggering Unit (CTU) conversions are performed at the same time while the storage of the results is performed in series. In Dual Conversion Mode, 4 bits select each channel number, and the conversion mode selection bit selects the Dual Conversion Mode. If the Single Conversion Mode is selected, 5 of the 8 bits reserved to select the channels in Dual Conversion Mode are re- used to select the channel (4 bits) and the ADC unit (1 bit).
Page 612: Adc Results
Cross Triggering Unit (CTU) RM0046 Table 310. ADC commands translation (continued) Input command Output command Single sampling ADC_0 channel 11 Single sampling ADC_0 channel 11 Single sampling ADC_0 channel 12 Single sampling ADC_0 channel 12 Single sampling ADC_0 channel 13 Single sampling ADC_0 channel 13 Single sampling ADC_0 channel 14 Single sampling ADC_0 channel 14...
Page 613: Reload Mechanism
RM0046 Cross Triggering Unit (CTU) in the upper 16 bits indicate the ADC unit (1 bit) and the channel number (4 bits). The result registers (only for the FIFOs) can be read from two different addresses in the ADC memory map.
Page 614: Figure 308. Reload Error Scenario
Cross Triggering Unit (CTU) RM0046 set and (if enabled) an interrupt for an error is performed (in this case at least one register was written but the update has not ended before the MRS occurrence). If FGRE is 0 it is not necessary to perform a reload because all the double-buffered registers are unchanged (see Figure...
Page 615: Interrupts And Dma Requests
RM0046 Cross Triggering Unit (CTU) 24.7 Interrupts and DMA requests 24.7.1 DMA support The DMA can be used to configure the CTU registers. One DMA channel is reserved for performing a block transfer, and the MRS can be used as an optional DMA request signal (MRS_DMAE bit in the CTU Interrupt/DMA Register).
Page 616: Table 311. Ctu Interrupts
Cross Triggering Unit (CTU) RM0046 The outgoing trigger event (all line are ORed) resets this flag to 0. TGS Overrun in the sequential mode shall be generated under the following conditions: – TGS is in sequential mode – there is an incoming EV while the busy flag is high. the TGS_OSM bit is set. The faults/errors flags in the CTU error flag register and in the CTU interrupt flag register can be cleared by writing a 1 while writing a 0 has no effect.
Page 617: Table 312. Ctu Memory Map
RM0046 Cross Triggering Unit (CTU) Table 311. CTU interrupts (continued) Category Interrupt Interrupt function FIFO_FULL1 This bit is set to 1 if the FIFO 1 is full. FIFO_EMPTY1 This bit is set to 1 if the FIFO 1 is empty. ORed onto FIFO_OVERFLOW This bit is set to 1 if the number of words exceeds the value set in the...
Page 618 Cross Triggering Unit (CTU) RM0046 Table 312. CTU memory map (continued) Offset from CTU_BASE Register Location (0xFFE0_C000) 0x0008 T1CR — Trigger 1 Compare Register on page 24-624 0x000A T2CR — Trigger 2 Compare Register on page 24-624 0x000C T3CR — Trigger 3 Compare Register on page 24-624 0x000E T4CR —...
Page 619 RM0046 Cross Triggering Unit (CTU) Table 312. CTU memory map (continued) Offset from CTU_BASE Register Location (0xFFE0_C000) 0x0052 CLR20—Commands List Register 20 on page 24-631 0x0054 CLR21—Commands List Register 21 on page 24-631 0x0056 CLR22—Commands List Register 22 on page 24-631 0x0058 CLR23—Commands List Register 23 on page 24-631...
Page 620: Table 313. Tgs Registers
Cross Triggering Unit (CTU) RM0046 Table 313. TGS registers Double- Offset from Synchronizatio Register buffere Reset value CTU_BASE TGSISR — Trigger Generator Subunit Input Selection 0x0000_000 0x0000 TGSISR_RE Register TGSCRR — Trigger Generator Subunit Control 0x0004 0x0000 Register 0x0006 T0CR — Trigger 0 Compare Register 0x0000 0x0008 T1CR —...
Page 621: Table 316. Fifo Registers
RM0046 Cross Triggering Unit (CTU) Table 315. CTU registers (continued) Offset from Double- Reset Register Synchronization CTU_BASE buffered value 0x00CA CTUDF — Cross Triggering Unit Digital Filter 0x0000 CTUPCR — Cross Triggering Unit Power Control 0x00CC — 0x0000 Register Table 316. FIFO registers Offset from Double- Register...
Page 622: Table 317. Tgsisr Field Descriptions
Cross Triggering Unit (CTU) RM0046 Table 317. TGSISR field descriptions Field Description Input 15 — ext_signals Falling edge Enable I15_FE 0 Disabled 1 Enabled Input 15 — ext_signals Rising edge Enable I15_RE 0 Disabled 1 Enabled Input 13 — eTimer0 [ETC2] Falling edge Enable I13_FE 0 Disabled 1 Enabled...
Page 623 RM0046 Cross Triggering Unit (CTU) Table 317. TGSISR field descriptions (continued) Field Description Input 7 — PWM OUT_TRIG 1 [2] Falling edge Enable I7_FE 0 Disabled 1 Enabled Input 7 — PWM OUT_TRIG 1 [2] Rising edge Enable I7_RE 0 Disabled 1 Enabled Input 6 —...
Page 624: Table 318. Tgscr Field Descriptions
Cross Triggering Unit (CTU) RM0046 Table 317. TGSISR field descriptions (continued) Field Description Input 0 — PWM Reload Falling edge Enable I0_FE 0 Disabled 1 Enabled Input 0 — PWM Reload Rising edge Enable I0_RE 0 Disabled 1 Enabled 24.8.2 Trigger Generator Sub-unit Control Register (TGSCR) Figure 310.
Page 625: Table 319. Txcr Field Descriptions
RM0046 Cross Triggering Unit (CTU) Table 319. TxCR field descriptions Field Description TxCRV Trigger x Compare Register Value 24.8.4 TGS Counter Compare Register (TGSCCR) Figure 312. TGS Counter Compare Register (TGSCCR) Address: Base + 0x0016 Access: User read/write TGSCCV Reset Table 320.
Page 626: Table 322. Clcr1 Field Descriptions
Cross Triggering Unit (CTU) RM0046 24.8.6 Commands list control register 1 (CLCR1) Figure 314. Commands list control register 1 (CLCR1) Address: Base + 0x001C Access: User read/write T3_INDEX T2_INDEX Reset T1_INDEX T0_INDEX Reset Table 322. CLCR1 field descriptions Field Description T3_INDEX Trigger 3 Commands List first command address T2_INDEX...
Page 627: Table 324. Thcr1 Field Descriptions
RM0046 Cross Triggering Unit (CTU) 24.8.8 Trigger handler control register 1 (THCR1) Figure 316. Trigger handler control register 1 (THCR1) Address: Base + 0x0024 Access: User read/write T3_E T2_E ADCE ADCE Reset T1_E T0_E ADCE ADCE Reset Table 324. THCR1 field descriptions Field Description Trigger 3 enable...
Page 628 Cross Triggering Unit (CTU) RM0046 Table 324. THCR1 field descriptions (continued) Field Description Trigger 2 ADC command output enable T2_ADCE 0 Disabled 1 Enabled Trigger 1 enable T1_E 0 Disabled 1 Enabled Trigger 1 External Trigger output enable T1_ETE 0 Disabled 1 Enabled Trigger 1 Timer 1 output enable T1_T1E...
Page 629: Table 325. Thcr2 Field Descriptions
RM0046 Cross Triggering Unit (CTU) 24.8.9 Trigger handler control register 2 (THCR2) Figure 317. Trigger handler control register 2 (THCR2) Address: Base + 0x0028 Access: User read/write T7_E T6_E ADCE ADCE Reset T5_E T4_E ADCE ADCE Reset Table 325. THCR2 field descriptions Field Description Trigger 7 enable...
Page 630 Cross Triggering Unit (CTU) RM0046 Table 325. THCR2 field descriptions (continued) Field Description Trigger 6 ADC command output enable T6_ADCE 0 Disabled 1 Enabled Trigger 5 enable T5_E 0 Disabled 1 Enabled Trigger 5 External Trigger output enable T5_ETE 0 Disabled 1 Enabled Trigger 5 Timer 1 output enable T5_T1E...
Page 631: Table 326. Clrx (Cms = 0) Field Descriptions
RM0046 Cross Triggering Unit (CTU) 24.8.10 Commands list register x (x = 1,...,24) (CLRx) Figure 318 Table 326 show the register configured for ADC command format in single conversion mode (CMS = 0) (CLRx). Figure 318. Commands list register x (x = 1,...,24) (CMS = 0) Base + 0x002C,...,0x005A Address: Access: User read/write...
Page 632: Table 327. Clrx (Cms = 1) Field Descriptions
Cross Triggering Unit (CTU) RM0046 Table 327. CLRx (CMS = 1) field descriptions Field Description Command Interrupt Request bit 0 Disabled 1 Enabled First command bit 0 Not first command 1 First command Conversion mode selection 0 Single conversion mode 1 Dual conversion mode FIFO FIFO for ADC unit A/B...
Page 633: Table 329. Fcr Field Descriptions
RM0046 Cross Triggering Unit (CTU) 24.8.12 FIFO control register (FCR) Figure 321. FIFO control register (FCR) Address: Base + 0x0070 Access: User read/write Reset Reset Table 329. FCR field descriptions Field Description FIFO 3 Overrun interrupt enable OR_EN3 0 Disabled 1 Enabled FIFO 3 threshold Overflow interrupt enable OF_EN3...
Page 634: Table 330. Fth Field Descriptions
Cross Triggering Unit (CTU) RM0046 Table 329. FCR field descriptions (continued) Field Description FIFO 1 threshold Overflow interrupt enable OF_EN1 0 Disabled 1 Enabled FIFO 1 Empty interrupt enable EMPTY_EN1 0 Disabled 1 Enabled FIFO 1 Full interrupt enable FULL_EN1 0 Disabled 1 Enabled FIFO 0 Overrun interrupt enable...
Page 635: Table 331. Fst Field Descriptions
RM0046 Cross Triggering Unit (CTU) Table 330. FTH field descriptions (continued) Field Description FIFO 1 Threshold FIFO 0 Threshold 24.8.14 FIFO status register (FST) Figure 323. FIFO status register (FST) Address: Base + 0x007C Access: User read/write Reset R OR3 OF3 EMP3 FULL3 OR2 OF2 EMP2 FULL2 OR1 OF1 EMP1 FULL1 OR0 OF0 EMP0 FULL0 W r1c Reset Table 331.
Page 636: Figure 324. Fifo Right Aligned Data X (X = 0
Cross Triggering Unit (CTU) RM0046 Table 331. FST field descriptions (continued) Field Description FIFO 2 Full interrupt flag FULL2 0 Interrupt has not occurred. 1 Interrupt has occurred. FIFO 1 Overrun interrupt flag A read of this bit clears it. 0Interrupt has not occurred.
Page 637: Table 332. Frx Field Descriptions
RM0046 Cross Triggering Unit (CTU) Table 332. FRx field descriptions Field Description Number of stored channel N_CH[4:0] 0xxxx: Result comes from an ADC_1 channel 1xxxx: Result comes from an ADC_0 channel DATA Data of stored channel 24.8.16 FIFO signed Left aligned data x (x = 0,...,3) (FLx) Figure 325.
Page 638: Table 334. Ctuefr Field Descriptions
Cross Triggering Unit (CTU) RM0046 Table 334. CTUEFR field descriptions Field Description External Trigger generation Overrun Error ET_OE 0 Error has not occurred. 1 Error has occurred. Timer 1 trigger generation Overrun Error T1_OE 0 Error has not occurred. 1 Error has occurred. Timer 0 trigger generation Overrun Error T0_OE 0 Error has not occurred.
Page 639: Table 335. Ctuifr Field Descriptions
RM0046 Cross Triggering Unit (CTU) Table 335. CTUIFR field descriptions Field Description ADC command interrupt flag ADC_I 0 Interrupt has not occurred. 1 Interrupt has occurred. Trigger 7 interrupt flag T7_I 0 Interrupt has not occurred. 1 Interrupt has occurred. Trigger 6 interrupt flag T6_I 0 Interrupt has not occurred.
Page 640: Table 336. Ctuir Field Descriptions
Cross Triggering Unit (CTU) RM0046 Table 336. CTUIR field descriptions Field Description Trigger 7 Interrupt Enable T7_IE 0 Interrupt disabled 1 Interrupt enabled Trigger 6 Interrupt Enable T6_IE 0 Interrupt disabled 1 Interrupt enabled Trigger 5 Interrupt Enable T5_IE 0 Interrupt disabled 1 Interrupt enabled Trigger 4 Interrupt Enable T4_IE...
Page 641: Table 337. Cotr Field Descriptions
RM0046 Cross Triggering Unit (CTU) Table 337. COTR field descriptions Field Description COTR Control ON-Time and Guard Time for external trigger 24.8.21 Cross triggering unit control register (CTUCR) Figure 330. Cross triggering unit control register (CTUCR) Address: Base + 0x00C8 Access: User read/write Reset Table 338.
Page 642: Table 339. Ctudf Field Descriptions
Cross Triggering Unit (CTU) RM0046 Table 338. CTUCR field descriptions (continued) Field Description Digital Filter Enable CGRE Clear GRE FGRE Flag GRE MRS_SG MRS Software Generated General Reload Enable TGSISR_RE TGS Input Selection Register Reload Enable 24.8.22 Cross triggering unit digital filter (CTUDF) Figure 331.
Page 643: Overview
RM0046 FlexPWM FlexPWM 25.1 Overview The pulse width modulator module (PWM) contains four PWM submodules, each of which capable of controlling a single half-bridge power stage and two fault input channels. This PWM is capable of controlling most motor types: AC induction motors (ACIM), Permanent Magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.
Page 644: Table 341. Modes When Pwm Operation Is Restricted
FlexPWM RM0046 25.3 Modes of operation Care must be exercised when using this module in certain device operating modes. Some motors (such 3-phase AC motors) require regular software updates for proper operation. Failure to do so could result in destroying the motor or inverter. Because of this, PWM outputs are placed in their inactive states in STOP mode, and optionally under WAIT/HALT and debug modes.
Page 645: Figure 333. Pwm Block Diagram
RM0046 FlexPWM 25.4 Block diagrams 25.4.1 Module level EXT_SYNC EXT_FORCE PWMA0 PWMB0 Submodule 0 PWMX0 FAULT0–1 Fault Channel 0 PWMA1 PWMB1 Submodule 1 PWMX1 PWMA2 PWMB2 Submodule 2 PWMX2 PWMA3 PWMB3 Submodule 3 PWMX3 Figure 333. PWM block diagram Doc ID 16912 Rev 5 645/936...
Page 646: Figure 334. Pwm Submodule Block Diagram
FlexPWM RM0046 25.4.2 PWM submodule Figure 334. PWM submodule block diagram 646/936 Doc ID 16912 Rev 5...
Page 647: External Signal Descriptions
RM0046 FlexPWM 25.5 External signal descriptions The PWM module has external pins named PWMA[n], PWMB[n], PWMX[n], FAULT[n], EXT_SYNC. The PWM module also has on-chip inputs called EXT_CLK, EXT_FORCE and on-chip outputs called OUT_TRIG[n]. 25.5.1 PWMA[n] and PWMB[n] — external PWM pair These pins are the output pins of the PWM channels.
Page 648: Table 342. Flexpwm Memory Map
FlexPWM RM0046 25.6 Memory map and registers 25.6.1 FlexPWM module memory map Table 342. FlexPWM memory map Offset from Reset FlexPWM_BASE Register Access Location value (0xFFE2_4000) 0x0000 CNT—Counter Register (Submodule 0) 0x0000 on page 25-651 0x0002 INIT—Initial Count Register (Submodule 0) 0x0000 on page 25-651 0x0004...
Page 649 RM0046 FlexPWM Table 342. FlexPWM memory map (continued) Offset from Reset FlexPWM_BASE Register Access Location value (0xFFE2_4000) 0x0062 VAL5—Value Register 5 (Submodule 1) 0x0000 on page 25-659 0x0064–0x0067 Reserved 0x0068 OCTRL—Output Control Register (Submodule 1) 0x0000 on page 25-659 0x006A STS—Status Register (Submodule 1) 0x0000 on page 25-660...
Page 650: Register Descriptions
FlexPWM RM0046 Table 342. FlexPWM memory map (continued) Offset from Reset FlexPWM_BASE Register Access Location value (0xFFE2_4000) 0x00F2 INIT—Initial Count Register (Submodule 3) 0x0000 on page 25-651 0x00F4 CTRL2—Control 2 Register (Submodule 3) 0x0000 on page 25-652 0x00F6 CTRL1—Control 1 Register (Submodule 3) 0x0000 on page 25-654 0x00F8...
Page 651: Figure 335. Counter Register (Cnt)
RM0046 FlexPWM There are a set of registers for each PWM submodule, for the configuration logic, and for each Fault channel. 25.6.3 Submodule registers These registers are repeated for each PWM submodule. Counter Register (CNT) Figure 335. Counter Register (CNT) Base + 0x0000 (Submodule 0) Base + 0x0050 (Submodule 1) Address:...
Page 652: Table 343. Ctrl2 Field Descriptions
FlexPWM RM0046 Control 2 Register (CTRL2) Figure 337. Control 2 Register (CTRL2) Base + 0x0004 (Submodule 0) Base + 0x0054 (Submodule 1) Address: Base + 0x00A4 (Submodule 2) Base + 0x00F4 (Submodule 3) Access: User read/write INIT_SEL FORCE_SEL CLK_SEL Reset Table 343.
Page 653 RM0046 FlexPWM Table 343. CTRL2 field descriptions (continued) Field Description PWMB Initial Value This read/write bit determines the initial value for PWMB and the value to which it is forced when PWMB_INIT FORCE_INIT is asserted. PWMX Initial Value This read/write bit determines the initial value for PWMX and the value to which it is forced when PWMX_INIT FORCE_INIT is asserted.
Page 654: Table 344. Ctrl1 Field Descriptions
FlexPWM RM0046 Table 343. CTRL2 field descriptions (continued) Field Description Reload Source Select This read/write bit determines the source of the RELOAD signal for this submodule. When this bit is set, the LDOK bit in submodule 0 should be used since the local LDOK bit will be ignored. RELOAD_SEL 0 The local RELOAD signal is used to reload registers.
Page 655: Table 345. Pwm Reload Frequency
RM0046 FlexPWM Table 344. CTRL1 field descriptions (continued) Field Description Full Cycle Reload This read/write bit enables full-cycle reloads. A full cycle is defined by when the submodule counter matches the VAL1 register. Either the HALF or FULL bit must be set in order to move the buffered data into the registers used by the PWM generators.
Page 656: Table 346. Pwm Prescaler
FlexPWM RM0046 Table 346. PWM prescaler PRSC PWM clock frequency /128 Note: Reading the PRSCx bits reads the buffered values and not necessarily the values currently in effect. The PRSCx bits take effect at the beginning of the next PWM cycle and only when the load okay bit, LDOK, is set.
Page 657: Figure 340. Value Register 1 (Val1)
RM0046 FlexPWM Value register 1 (VAL1) Figure 340. Value Register 1 (VAL1) Base + 0x000A (Submodule 0) Base + 0x005A (Submodule 1) Address: Base + 0x00AA (Submodule 2) Base + 0x00FA (Submodule 3) Access: User read/write VAL1 Reset The 16-bit signed value written to this register defines the modulo count value (maximum count) for the submodule counter.
Page 658: Figure 342. Value Register 3 (Val3)
FlexPWM RM0046 Value register 3 (VAL3) Figure 342. Value register 3 (VAL3) Base + 0x000E (Submodule 0) Base + 0x005E (Submodule 1) Address: Base + 0x00AE (Submodule 2) Base + 0x00FE (Submodule 3) Access: User read/write VAL3 Reset The 16-bit signed value in this register defines the count value to set PWMA low (Figure 334).
Page 659: Table 347. Octrl Field Descriptions
RM0046 FlexPWM Value register 5 (VAL5) Figure 344. Value register 5 (VAL5) Base + 0x0012 (Submodule 0) Base + 0x0062 (Submodule 1) Address: Base + 0x00B2 (Submodule 2) Base + 0x0102 (Submodule 3) Access: User read/write VAL5 Reset The 16-bit signed value in this register defines the count value to set PWMB low (Figure 334).
Page 660: Figure 346. Status Register (Sts)
FlexPWM RM0046 Table 347. OCTRL field descriptions (continued) Field Description PWMB Output Polarity This bit inverts the PWMB output polarity. POLB 0 PWMB output not inverted. A high level on the PWMB pin represents the “on” or “active” state. 1 PWMB output inverted. A low level on the PWMB pin represents the “on” or “active” state. PWMX Output Polarity This bit inverts the PWMX output polarity.
Page 661: Table 348. Sts Field Descriptions
RM0046 FlexPWM Table 348. STS field descriptions Field Description Registers Updated Flag This read only flag is set when one of the INIT, VALx, or PRSC fields has been written resulting in non- coherent data in the set of double buffered registers. Clear RUF by a proper reload sequence consisting of a reload signal while LDOK = 1.
Page 662: Table 349. Inten Field Descriptions
FlexPWM RM0046 Table 349. INTEN field descriptions Field Description Reload Error Interrupt Enable This read/write bit enables the reload error flag (REF) to generate CPU interrupt requests. Reset clears RIE. REIE 0 REF CPU interrupt requests disabled. 1 REF CPU interrupt requests enabled. Reload Interrupt Enable This read/write bit enables the reload flag (RF) to generate CPU interrupt requests.
Page 663: Table 351. Tctrl Field Descriptions
RM0046 FlexPWM Output Trigger Control register (TCTRL) Figure 349. Output Trigger Control register (TCTRL) Base + 0x0020 (Submodule 0) Base + 0x0070 (Submodule 1) Address: Access: User read/write Base + 0x00C0 (Submodule 2) Base + 0x0110 (Submodule 3) OUT_TRIG_EN[5:0] Reset Table 351.
Page 664: Table 352. Dismap Field Descriptions
FlexPWM RM0046 Fault Disable Mapping register (DISMAP) This register determines which PWM pins are disabled by the fault protection inputs, illustrated in Table 350 Section 25.8.12, “Fault protection. Reset sets all of the bits in the fault disable mapping register. Figure 350.
Page 665: Figure 351. Deadtime Count Register 0 (Dtcnt0)
RM0046 FlexPWM Figure 351. Deadtime Count Register 0 (DTCNT0) Base + 0x0024 (Submodule 0) Base + 0x0074 (Submodule 1) Address: Base + 0x00C4 (Submodule 2) Base + 0x0114 (Submodule 3) Access: User read/write DTCNT0 Reset Figure 352. Deadtime Count register 1 (DTCNT1) Base + 0x0026 (Submodule 0) Base + 0x0076 (Submodule 1) Address:...
Page 666: Table 353. Outen Field Descriptions
FlexPWM RM0046 Table 353. OUTEN field descriptions Field Description PWMA Output Enables These bits enable the PWMA outputs of each submodule. PWMA_EN[3:0] 0 PWMA output disabled. 1 PWMA output enabled. PWMB Output Enables 8:11 These bits enable the PWMB outputs of each submodule. PWMB_EN[3:0] 0 PWMB output disabled.
Page 667: Table 355. Swcout Field Descriptions
RM0046 FlexPWM Table 354. MASK field descriptions (continued) Field Description PWMB Masks These bits mask the PWMB outputs of each submodule forcing the output to logic 0 prior to 8:11 consideration of the output polarity. MASKB[3:0] 0 PWMB output normal. 1 PWMB output masked.
Page 668: Figure 356. Deadtime Source Select Register (Dtsrcsel)
FlexPWM RM0046 Table 355. SWCOUT field descriptions (continued) Field Description Software Controlled Output B_2 This bit is only used when SELB for submodule 2 is set to 0b10. It allows software control of which signal is supplied to the deadtime generator of that submodule. OUTB_2 0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWMB.
Page 669: Table 356. Dtsrcsel Field Descriptions
RM0046 FlexPWM Table 356. DTSRCSEL field descriptions Field Description PWMA_3 Control Select This field selects possible over-rides to the generated PWMA signal in submodule 3 that will be passed to the deadtime logic upon the occurrence of a “Force Out” event in that submodule. 00 Generated PWMA_3 signal is used by the deadtime logic.
Page 670: Figure 357. Master Control Register (Mctrl)
FlexPWM RM0046 Table 356. DTSRCSEL field descriptions (continued) Field Description PWMA_0 Control Select This field selects possible over-rides to the generated PWMA signal in submodule 0 that will be passed to the deadtime logic upon the occurrence of a “Force Out” event in that submodule. 12:13 00 Generated PWMA_0 signal is used by the deadtime logic.
Page 671: Table 357. Mctrl Field Descriptions
RM0046 FlexPWM Table 357. MCTRL field descriptions Field Description Current Polarity This buffered read/write bit selects between PWMA and PWMB as the source for the generation of the complementary PWM pair output. IPOL is ignored in independent mode. PWMB (Figure 334) generates complementary PWM pairs.
Page 672: Table 358. Fctrl Field Descriptions
FlexPWM RM0046 Table 358. FCTRL field descriptions Field Description Fault Level These read/write bits select the active logic level of the individual fault inputs. A reset clears FLVL. FLVL 0 A logic 0 on the fault input indicates a fault condition. 1 A logic 1 on the fault input indicates a fault condition.
Page 673: Table 359. Fsts Field Descriptions
RM0046 FlexPWM Table 359. FSTS field descriptions Field Description Fault Test These read/write bits simulate a fault condition. Setting this bit will cause a simulated fault to be sent into all of the fault filters. The condition will propagate to the fault flags and possibly the PWM outputs depending on the DISMAP settings.
Page 674 FlexPWM RM0046 Input filter considerations The FILT_PER value should be set such that the sampling period is larger than the period of the expected noise. This way a noise spike will only corrupt one sample. The FILT_CNT value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized.
Page 675: Figure 361. Center-Aligned Example
RM0046 FlexPWM 25.7 Functional description 25.7.1 Center-aligned PWMs Each submodule has its own timer that is capable of generating PWM signals on two output pins. The edges of each of these signals are controlled independently as shown in Figure 361. VAL1 (0x0100) VAL3 VAL5...
Page 676: Figure 362. Edge-Aligned Example (Init = Val2 = Val4)
FlexPWM RM0046 to each other, which is the goal. Of course, center alignment between the signals is not restricted to symmetry around the zero count value, as any other number would also work. However, centering on zero provides the greatest range in signed mode and also simplifies the calculations.
Page 677: Figure 363. Phase-Shifted Outputs Example
RM0046 FlexPWM are applied to the turn on and turn off edges of different PWM signal, the signals will be phase shifted with respect to each other, as illustrated in Figure 363. This results in certain advantages when applied to a power stage. For example, when operating a multi-phase inverter at a low modulation index, all of the PWM switching edges from the different phases occur at nearly the same time.
Page 678: Figure 364. Phase-Shifted Pwms Applied To A Transformer Primary
FlexPWM RM0046 Top Left Submodule 0 Bottom Left Top Right Submodule 1 Bottom Right Left Side Right Side Transformer Figure 364. Phase-shifted PWMs applied to a transformer primary 25.7.4 Double switching PWMs Double switching PWM output is supported to aid in single shunt current measurement and three phase reconstruction.
Page 679: Figure 365. Double Switching Output Example
RM0046 FlexPWM VAL1 (0x0100) VAL3 VAL5 VAL0 (0x0000) VAL4 VAL2 INIT (0xFF00) PWMA PWMB DBLPWM Figure 365. Double switching output example 25.7.5 ADC triggering In cases where the timing of the ADC triggering is critical, it must be scheduled as a hardware event instead of software activated.
Page 680: Figure 366. Multiple Output Trigger Generation In Hardware
FlexPWM RM0046 VAL1 (0x0100) VAL3 VAL5 VAL4 VAL2 INIT (0xFF00) Output Triggers Figure 366. Multiple output trigger generation in hardware Since each submodule has its own timer, it is possible for each submodule to run at a different frequency. One of the options possible with this PWM module is to have one or more submodules running at a lower frequency, but still synchronized to the timer in submodule 0.
Page 681: Figure 367. Multiple Output Triggers Over Several Pwm Cycles
RM0046 FlexPWM Submodule 0 counter (PWM generation) Submodule1 counter VAL5 VAL4 VAL3 VAL2 VAL1 VAL0 Output Triggers Figure 367. Multiple output triggers over several PWM cycles 25.7.6 Synchronous switching of multiple outputs Before the PWM signals are routed to the output pins, they are processed by a hardware block that permits all submodule outputs to be switched synchronously.
Page 682: Figure 368. Sensorless Bldc Commutation Using The Force Out Function
FlexPWM RM0046 simplistic representation of these back EMF signals. Timer compare events (represented by the long vertical lines in the diagram) are scheduled based on the zero crossings of the back-EMF waveforms. The PWM module is configured via software ahead of time with the next state of the PWM pins in anticipation of the compare event.
Page 683: Figure 369. Clocking Block Diagram For Each Pwm Submodule
RM0046 FlexPWM 25.8.1 PWM clocking Figure 369 shows the logic used to generate the main counter clock. Each submodule can select between three clock signals: the IPBus clock, EXT_CLK, and AUX_CLK. The EXT_CLK is generated by an on-chip resource such as a Timer module and goes to all of the submodules.
Page 684: Figure 370. Register Reload Logic
FlexPWM RM0046 RELOAD_SEL Reload opportunity LDOK Reload (to on-chip trigger unit) Logic Local Reload Mod Compare (counts Register Reload Half Compare cycles) Master Reload (from submod0 only) Master Reload Figure 370. Register reload logic 25.8.3 Counter synchronization Referring to Figure 371, the 16-bit counter will count up until its output equals VAL1, which specifies the counter modulus value.
Page 685: Pwm Generation
RM0046 FlexPWM The EXT_SYNC signal originates either on- or off-chip, depending on the system architecture. This signal may be selected as the source for counter initialization so that an external source can control the period of all submodules. If the Master Reload signal is selected as the source for counter initialization, then the period of the counter will be locked to the register reload frequency of submodule 0.
Page 686: Figure 372. Pwm Generation Hardware
FlexPWM RM0046 VAL0 PWM on 16-bit Half Comp comparator 16-bit counter PWMX SYNC_INIT FORCE_OUT Force Init (inverted Local Sync) FORCE_EN VAL1 16-bit Mod Comp comparator PWM off VAL2 16-bit PWM on comparator PWMA_INIT PWMA VAL3 16-bit comparator PWM off to Force Out logic VAL4 16-bit...
Page 687: Output Compare Capabilities
RM0046 FlexPWM The 16-bit comparators shown in Figure 372 are “equal to or greater than” not just “equal to” comparators. In addition, if both the set and reset of the flip-flop are both asserted, then the flop output goes to 0. 25.8.5 Output compare capabilities By using the VALx registers in conjunction with the submodule timer and 16-bit...
Page 688: Figure 373. Force Out Logic
FlexPWM RM0046 Master Force (from submod0 only) PWMA from generation h/w PWMA OUTA to Deadtime logic Local Force SELA Master Force Local Reload DBLPWM Master Reload from generation h/w FORCE_OUT Local Sync PWMB Master Sync EXT_FORCE PWMB OUTB Reserved FORCE_SEL SELB Figure 373.
Page 689: Figure 374. Complementary Channel Pair
RM0046 FlexPWM VAL2 VAL3 PWMA Generation PWMA PWMB Generation PWMB VAL4 VAL5 IPOL Figure 374. Complementary channel pair The complementary channel operation is for driving top and bottom transistors in a motor drive circuit, such as the one in Figure 375.
Page 690: Figure 376. Deadtime Insertion And Fine Control Logic
FlexPWM RM0046 DTCNT0 PWMA INDEP from Force Out logic rising start down edge counter PWMA zero detect DBLPWM to Output DBLEN logic zero falling start down PWMB edge counter detect IPOL INDEP PWMB DTCNT1 INDEP Figure 376. Deadtime insertion and fine control logic While in the complementary mode, a PWM pair can be used to drive top/bottom transistors, as shown in Figure...
Page 691: Figure 377. Deadtime Insertion
RM0046 FlexPWM VAL1 (0x0100) VAL3 VAL0 (0x0000) VAL2 INIT (0xFF00) PWMA no deadtime PWMB PWMA with deadtime DTCNT1 DTCNT0 PWMB Figure 377. Deadtime insertion 25.8.9 Top/bottom correction In complementary mode, either the top or the bottom transistor controls the output voltage. However, deadtime has to be inserted to avoid overlap of conducting interval between the top and bottom transistor.
Page 692: Figure 378. Deadtime Distortion
FlexPWM RM0046 Desired load voltage Deadtime PWM to top transistor Positive current Negative current PWM to bottom transistor Positive current load voltage Negative current load voltage Figure 378. Deadtime distortion During deadtime, load inductance distorts output voltage by keeping current flowing through the diodes.
Page 693: Figure 379. Current-Status Sense Scheme For Deadtime Correction
RM0046 FlexPWM To correct deadtime distortion, software can decrease or increase the value in the appropriate VALx register. ● In edge-aligned operation, decreasing or increasing the PWM value by a correction value equal to the deadtime typically compensates for deadtime distortion. ●...
Page 694: Figure 380. Output Voltage Waveforms
FlexPWM RM0046 Deadtime PWM to top transistor Positive current Negative current PWM to bottom transistor Load voltage with high positive current Load voltage with low positive current Load voltage with high negative current Load voltage with low negative current T = Deadtime interval before assertion of top PWM B = Deadtime interval before assertion of bottom PWM Figure 380.
Page 695: Figure 381. Output Logic Section
RM0046 FlexPWM PWMAFS[1] PWMA Disable PWMA_EN PWMAFS[0] PWMA output PWMA POLA from Deadtime logic POLB PWMB PWMB output PWMBFS[0] PWMB_EN PWMB Disable PWMBFS[1] Figure 381. Output logic section 25.8.12 Fault protection Fault protection can control any combination of PWM output pins. Faults are generated by a logic one on any of the FAULTx pins.
Page 696: Table 361. Fault Mapping
FlexPWM RM0046 DISA1 DISA0 FAULT0 FAULT1 Disable Wait/Halt Mode PWMA WAITEN Debug Mode DBGEN Stop Mode Figure 382. Fault decoder for PWMA Table 361. Fault mapping PWM pin Controlling register bits PWMA DISA[1:0] PWMB DISB[1:0] PWMX DISX[1:0] 25.8.13 Fault pin filter Each fault pin has a programmable filter that can be bypassed.
Page 697: Figure 383. Automatic Fault Clearing
RM0046 FlexPWM 25.8.14 Automatic fault clearing Setting an automatic clearing mode bit, FAUTOx, configures faults from the FAULTx pin for automatic clearing. When FAUTOx is set, disabled PWM pins are enabled when the FAULTx pin returns to logic one and a new PWM either full or half cycle begins. See Figure 383.
Page 698: Figure 384. Manual Fault Clearing (Fsafe = 0)
FlexPWM RM0046 COUNT FFPINx BIT ENABLED OUTPUTS ENABLED DISABLED FFLAGx CLEARED Figure 384. Manual fault clearing (FSAFE = 0) COUNT FFPINx BIT ENABLED ENABLED DISABLED OUTPUTS FFLAGx CLEARED Figure 385. Manual fault clearing (FSAFE = 1) Note: Fault protection also applies during software output control when the SELA and SELB fields are set to select OUTA and OUTB bits.
Page 699: Figure 386. Full Cycle Reload Frequency Change
RM0046 FlexPWM LDOK allows software to finish calculating all of these PWM parameters so they can be synchronously updated. The PSRC, INIT, and VALx registers are loaded by software into a set of outer buffers. When LDOK is set, these values are transferred to an inner set of registers at the beginning of the next PWM reload cycle to be used by the PWM generator.
Page 700: Figure 388. Full And Half Cycle Reload Frequency Change
FlexPWM RM0046 Counter Reload Change Every two to every four to every to every two Reload opportunities opportunities opportunity opportunities Frequency Figure 388. Full and half cycle reload frequency change 25.9.3 Reload flag At every reload opportunity the PWM Reload Flag (RF) in the CTRL1 register is set. Setting RF happens even if an actual reload is prevented by the LDOK bit.
Page 701: Table 362. Interrupt Summary
RM0046 FlexPWM The PWM generator uses the last values loaded if RUN is cleared and then set while LDOK equals zero. When the RUN bit is cleared: ● The RF flag and pending CPU interrupt requests are not cleared ● All fault circuitry remains active ●...
Page 702: Table 363. Dma Summary
FlexPWM RM0046 25.12 Each submodule can request a DMA write request for its double buffered VALx registers. Table 363. DMA summary DMA request DMA enable Name Description Submodule 0 write request VALDE_0 VALx write request VALx registers need to be updated Submodule 1 write request VALDE_1 VALx write request...
Page 703: Etimer
RM0046 eTimer eTimer 26.1 Introduction The eTimer module contains six identical counter/timer channels and one watchdog timer function. Each 16-bit counter/timer channel contains a prescaler, a counter, a load register, a hold register, two queued capture registers, two compare registers, two compare preload registers, and four control registers.
Page 704: Features
eTimer RM0046 26.2 Features The eTimer module design includes these features: ● Six 16-bit counters/timers ● Count up/down ● Cascadeable counters ● Enhanced programmable up/down modulo counting ● Max count rate equals peripheral clock/2 for external clocks ● Max count rate equals peripheral clock for internal clocks ●...
Page 705: Figure 390. Etimer Block Diagram
RM0046 eTimer 26.3 Module block diagram The eTimer block diagram is shown in Figure 390. IPBus Clock Reset Count OFLAG 0 Inp 0 Channel 0 Filter Aux Inp 0 Filter OFLAG 1 Inp 1 Watchdog Filter Channel 1 Timer Aux Inp 1 Filter Inp 2 OFLAG 2...
Page 706: Figure 391. Etimer Channel Block Diagram
eTimer RM0046 26.4 Channel block diagram Each of the timer/counter channels within the eTimer are shown in Figure 391. Peripheral Output Clock Prescaler OFLAG Control Output Disable WD Count Edge Switch Detect UP/DN Primary Matrix/ Input Input Polarity Filter Secondary Select Input Comparator...
Page 707: Table 364. Etimer Memory Map
RM0046 eTimer Table 364. eTimer memory map Offset from eTIMER0_BASE Register Location (FFE1_8000) eTimer Channel 0 0x0000 COMP1—Compare Register 1 on page 26-710 0x0002 COMP2—Compare Register 2 on page 26-711 0x0004 CAPT1—Capture Register 1 on page 26-711 0x0006 CAPT2—Capture Register 2 on page 26-712 0x0008 LOAD—Load Register...
Page 708 eTimer RM0046 Table 364. eTimer memory map (continued) Offset from eTIMER0_BASE Register Location (FFE1_8000) 0x003E FILT—Input Filter Register on page 26-725 eTimer Channel 2 0x0040 COMP1—Compare Register 1 on page 26-710 0x0042 COMP2—Compare Register 2 on page 26-711 0x0044 CAPT1—Capture Register 1 on page 26-711 0x0046 CAPT2—Capture Register 2...
Page 709 RM0046 eTimer Table 364. eTimer memory map (continued) Offset from eTIMER0_BASE Register Location (FFE1_8000) 0x007C CCCTRL—Compare and Capture Control Register on page 26-723 0x007E FILT—Input Filter Register on page 26-725 eTimer Channel 4 0x0080 COMP1—Compare Register 1 on page 26-710 0x0082 COMP2—Compare Register 2 on page 26-711...
Page 710: Figure 392. Compare Register 1 (Comp1)
eTimer RM0046 Table 364. eTimer memory map (continued) Offset from eTIMER0_BASE Register Location (FFE1_8000) 0x00BA CMPLD2—Comparator Load Register 2 on page 26-722 0x00BC CCCTRL—Compare and Capture Control Register on page 26-723 0x00BE FILT—Input Filter Register on page 26-725 0x00C0–0x00FF Reserved 0x0100 WDTOL—Watchdog Time-out Low Register on page 26-726...
Page 711: Table 365. Comp1 Field Descriptions
RM0046 eTimer Table 365. COMP1 field descriptions Field Description Compare 1 Stores the value used for comparison with the counter value. COMP1[15:0] This register is not byte accessible. Compare register 2 (COMP2) The COMP2 register stores the value used for comparison with the counter value. More explanation on the use of COMP2 can be found in Section , “Usage of compare registers.
Page 712: Table 367. Capt1 Field Descriptions
eTimer RM0046 Table 367. CAPT1 field descriptions Field Description Capture 1 Stores the value captured from the counter. CAPT1[15:0] This register is not byte accessible. Capture register 2 (CAPT2) This read only register stores the value captured from the counter. Exactly when a capture occurs is defined by the CPT2MODE bits.
Page 713: Table 369. Load Field Descriptions
RM0046 eTimer Table 369. LOAD field descriptions Field Description Load Stores the value used to initialize the counter. LOAD[15:0] This register is not byte accessible. Hold register (HOLD) This read-only register stores the counter’s value whenever any of the other counters within a module are read.
Page 714: Table 371. Cntr Field Descriptions
eTimer RM0046 Table 371. CNTR field descriptions Field Description Contains the count value for this channel of the eTimer module. CNTR[15:0] This register is not byte accessible. Control register 1 (CTRL1) Figure 399. Control register 1 (CTRL1) Base + 0x000E(eTimer0) Base + 0x006E (eTimer3) Address: Base + 0x002E (eTimer1)
Page 715: Table 373. Count Source Values
RM0046 eTimer Table 372. CTRL1 field descriptions (continued) Field Description Count Length This bit determines whether the counter counts to the compare value and then reinitializes itself to the value specified in the LOAD, CMPLD1, or CMPLD2 registers, or the counter continues counting past the compare value, to the binary roll over.
Page 716: Table 374. Ctrl2 Field Descriptions
eTimer RM0046 Table 373. Count source values (continued) Value Meaning Value Meaning 01100 Reserved 11100 IP Bus clock divide by 16 prescaler 01101 Reserved 11101 IP Bus clock divide by 32 prescaler 01110 Reserved 11110 IP Bus clock divide by 64 prescaler 01111 Reserved 11111...
Page 717 RM0046 eTimer Table 374. CTRL2 field descriptions (continued) Field Description Force the OFLAG output This write only bit forces the current value of the VAL bit to be written to the OFLAG output. This bit FORCE always reads as a zero. The VAL and FORCE bits can be written simultaneously in a single write operation.
Page 718: Figure 401. Control Register 3 (Ctrl3)
eTimer RM0046 Table 374. CTRL2 field descriptions (continued) Field Description Master Mode This bit enables the compare function’s output to be broadcast to the other channels in the module. The compare signal then can be used to reinitialize the other counters and/or force their OFLAG MSTR signal outputs.
Page 719: Table 375. Ctrl3 Field Descriptions
RM0046 eTimer Table 375. CTRL3 field descriptions Field Description Stop Actions Enable This bit allows the tristating of the timer output during stop mode. STPEN 0 Output enable is unaffected by stop mode. 1 Output enable is disabled during stop mode. Reload on Capture These bits enable the capture function to cause the counter to be reloaded from the LOAD register.
Page 720: Table 376. Sts Field Descriptions
eTimer RM0046 Table 376. STS field descriptions Field Description Watchdog Time-out Flag This bit is set when the watchdog times out by counting down to zero. The watchdog must be enabled for time-out to occur and channel 0 must be in quadrature decode count mode (CNTMODE = 100).
Page 721: Table 377. Intdma Field Descriptions
RM0046 eTimer Interrupt and DMA enable register (INTDMA) Figure 403. Interrupt and DMA enable register (INTDMA) Base + 0x0016 (eTimer0) Base + 0x0076 (eTimer3) Address: Base + 0x0036 (eTimer1) Base + 0x0096 (eTimer4) Access: User read/write Base + 0x0056 (eTimer2) Base + 0x00B6 (eTimer5) Reset Table 377.
Page 722: Table 378. Cmpld1 Field Descriptions
eTimer RM0046 Table 377. INTDMA field descriptions (continued) Field Description Timer Compare 2 Flag Interrupt Enable TCF2IE Setting this bit enables interrupts when the TCF2 bit is set. Timer Compare 1 Flag Interrupt Enable TCF1IE Setting this bit enables interrupts when the TCF1 bit is set. Timer Compare Flag Interrupt Enable TCFIE Setting this bit enables interrupts when the TCF bit is set.
Page 723: Table 379. Cmpld2 Field Descriptions
RM0046 eTimer Table 379. CMPLD2 field descriptions Field Description CMPLD2[15:0] Specifies the preload value for the COMP2 register. Compare and Capture Control register (CCCTRL) Figure 406. Compare and Capture Control register (CCCTRL) Base + 0x001C (eTimer0) Base + 0x007C (eTimer3) Address: Base + 0x003C (eTimer1) Base + 0x009C (eTimer4)
Page 724 eTimer RM0046 Table 380. CCCTRL field descriptions (continued) Field Description Capture 2 Mode Control These bits control the operation of the CAPT2 register as well as the operation of the ICF2 flag by defining which input edges cause a capture event. The input source is the secondary count source. CPT2MODE 00 Disabled.
Page 725: Table 381. Filt Field Descriptions
RM0046 eTimer Input Filter Register (FILT) Figure 407. Input Filter register (FILT) Base + 0x001E (eTimer0) Base + 0x007E (eTimer3) Address: Base + 0x003E (eTimer1) Base + 0x009E (eTimer4) Access: User read/write Base + 0x005E (eTimer2) Base + 0x00BE (eTimer5) FILT_CNT[2:0] FILT_PER[7:0] Reset...
Page 726: Table 382. Wdtol, Wdtoh Field Descriptions
eTimer RM0046 Watchdog Time-Out registers (WDTOL and WDTOH) Figure 408. Watchdog Time-out Low Word register (WDTOL) Address: Base + 0x0100 Access: User read/write WDTOL Reset Figure 409. Watchdog Time-Out High Word register (WDTOH) Address: Base + 0x0102 Access: User read/write WDTOH Reset Table 382.
Page 727: Table 383. Enbl Field Descriptions
RM0046 eTimer Table 383. ENBL field descriptions Field Description Timer Channel Enable These bits enable the prescaler (if it is being used) and counter in each channel. Multiple ENBL bits can be set at the same time to synchronize the start of separate channels. If an ENBL bit is ENBL set, then the corresponding channel will start counting as soon as the CNTMODE field has a value other than 000.
Page 728: Table 384. Dreqn Field Descriptions
eTimer RM0046 Table 384. DREQn field descriptions Field Description DMA Request Enable Use these bits to enable each of the four module level DMA request outputs. Program the DREQ fields prior to setting the corresponding enable bit. Clearing this enable bit will remove the request DREQn_EN but wíll not clear the flag that is causing the request.
Page 729: Functional Description
RM0046 eTimer 26.7 Functional description 26.7.1 General Each channel has two basic modes of operation: it can count internal or external events, or it can count an internal clock source while an external input signal is asserted, thus timing the width of the external input signal. ●...
Page 730: Figure 413. Quadrature Incremental Position Encoder
eTimer RM0046 STOP mode When the CNTMODE field is set to 000, the counter is inert. No counting will occur. Stop mode will also disable the interrupts caused by input transitions on a selected input pin. COUNT mode When the CNTMODE field is set to 001, the counter will count the rising edges of the selected clock source.
Page 731: Figure 414. Triggered Count Mode (Length = 1)
RM0046 eTimer TRIGGERED-COUNT mode When the CNTMODE field is set to 110, the counter will begin counting the primary clock source after a positive transition (negative if SIPS = 1) of the secondary input occurs. The counting will continue until a compare event occurs or another positive input transition is detected.
Page 732: Figure 416. Pulse Output Mode
eTimer RM0046 Whenever any counter is read within a counter module, all of the counters’ values within the module are captured in their respective HOLD registers. This action supports the reading of a cascaded counter chain. First read any counter of a cascaded counter chain, then read the HOLD registers of the other counters in the chain.
Page 733: Figure 417. Variable Pwm Waveform
RM0046 eTimer generation has the advantage of allowing almost any desired PWM frequency and/or constant on or off periods. This mode of operation is often used to drive PWM amplifiers used to power motors and inverters. The CMPLD1 and CMPLD2 registers are especially useful for this mode, as they allow the programmer time to calculate values for the next PWM cycle while the PWM current cycle is underway.
Page 734: Other Features
eTimer RM0046 time the compare register is updated by the interrupt service routine. The counter would then continue counting until it rolled over and reached the new compare value. To address this, the compare registers are updated in hardware in the same way the counter register is reinitialized to the value stored in the LOAD register.
Page 735: Clocks
RM0046 eTimer The arming logic controls the operation of the capture circuits to allow captures to be performed in a free-running (continuous) or one-shot fashion. In free-running mode, the capture sequences will be performed indefinitely. If both capture circuits are enabled, they will work together in a ping-pong style where a capture event from one circuit leads to the arming of the other and vice versa.
Page 736: Table 385. Interrupt Summary
eTimer RM0046 26.9 Interrupts Each of the channels within the eTimer can generate an interrupt from several sources. The watchdog also generate interrupts. The interrupt service routine (ISR) must check the related interrupt enables and interrupt flags to determine the actual cause of the interrupt. Table 385.
Page 737: Figure 418. Register Protection Module Block Diagram
RM0046 Functional Safety Functional Safety 27.1 Introduction This chapter describes the following modules that help add reliability to the SPC560P40/34. ● Register protection module ● Software watchdog timer (SWT) 27.2 Register protection module 27.2.1 Overview The register protection module offers a mechanism to protect defined memory-mapped address locations in a module under protection from being written.
Page 738: Figure 419. Register Protection Memory Diagram
Functional Safety RM0046 27.2.2 Features The register protection module includes these features: ● Restrict write accesses for the module under protection to supervisor mode only ● Lock registers for first 6 KB of memory-mapped address space ● Address mirror automatically sets corresponding lock bit ●...
Page 739: Table 387. Register Protection Memory Map
RM0046 Functional Safety Area 3 is 6 KB, starting at address 0x2000 and is a mirror of area 1. A read/write access to these 0x2000 + X addresses will read/write the register at address X. As a side effect, a write access to address 0x2000 + X will set the optional Soft Lock Bits for this address X in the same cycle as the register at address X is written.
Page 740: Table 388. Slbrn Field Descriptions
Functional Safety RM0046 Module registers (MR0–6143) This is the lower 6 KB module memory space that holds all the functional registers of the module that is protected by the register protection module. Module Register and Set Soft Lock Bit (LMR0–6143) This is memory area #3 that provides mirrored access to the MR0–6143 registers with the side effect of setting Soft Lock Bits in case of a write access to a MR that is defined as protectable by the locking mechanism.
Page 741: Table 389. Soft Lock Bits Vs. Protected Address
RM0046 Functional Safety Table 389. Soft Lock Bits vs. Protected Address Soft Lock Bit Protected address SLBR0[SLB0] SLBR0[SLB1] SLBR0[SLB2] SLBR0[SLB3] SLBR1[SLB0] SLBR1[SLB1] SLBR1[SLB2] SLBR1[SLB3] SLBR2[SLB0] Global Configuration Register (GCR) The Global Configuration Register (GCR) controls global configurations related to register protection.
Page 742: Figure 422. Change Lock Settings Directly Via Area #4
Functional Safety RM0046 Note: The GCR[UAA] bit has no effect on the allowed access modes for the registers in the Register protection module. 27.2.6 Functional description General This module provides a generic register (address) write-protection mechanism. The protection size can be: ●...
Page 743: Figure 423. Change Lock Settings For 16-Bit Protected Addresses
RM0046 Functional Safety Figure 422 showed four registers that can be protected 8-bit wise. In Figure 423 registers with 16-bit protection and in Figure 424 registers with 32-bit protection are shown. write data write data to SLB0 to SLB1 to SLB2 to SLB3 to SLB0 to SLB1 to SLB2 to SLB3 SLBRn[WE[3:0]]...
Page 744: Figure 425. Change Lock Settings For Mixed Protection
Functional Safety RM0046 write data to SLB0 to SLB1 to SLB2 to SLB3 SLBRn[WE[3:0]] update lock bits SLB0 SLB1 SLB3 SLBR Figure 425. Change lock settings for mixed protection The data written to SLBRn[SLB0] is mirrored to SLBRn[SLB1] as the corresponding register is 16-bit protected.
Page 745: Reset
RM0046 Functional Safety In the example in Figure 427, addresses 0x0C and 0x0D are unprotected. Therefore their corresponding lock bits SLBR3.SLB[1:0] are always 0b0 (shown in bold). When doing a 32- bit write access to address 0x200C only lock bits SLBR3.SLB[3:2] are set while bits SLBR3.SLB[1:0] stay 0b0.
Page 746: Features
Functional Safety RM0046 The SWT provides a window functionality. When this functionality is programmed, the servicing action should take place within the defined window. When occurring outside the defined period, the SWT will generate a reset. 27.3.2 Features The SWT has the following features: ●...
Page 747: Table 391. Swt Memory Map
RM0046 Functional Safety Table 391. SWT memory map Offset from SWT_BASE Register Location 0xFFF3_8000 (SWT_0) 0x8FF3_8000 (SWT_1) 0x0000 SWT_CR—SWT Control Register on page 27-747 0x0004 SWT_IR—SWT Interrupt Register on page 27-749 0x0008 SWT_TO—SWT Time-Out register on page 27-749 0x000C SWT_WN—SWT Window Register on page 27-750 0x0010 SWT_SR—SWT Service Register...
Page 748 Functional Safety RM0046 Table 392. SWT_CR field descriptions (continued) Field Description Keyed Service Mode 0 Fixed Service Sequence, the fixed sequence 0xA602, 0xB480 is used to service the watchdog. 1 Keyed Service Mode, two pseudorandom key values are used to service the watchdog. Reset on Invalid Access 0 Invalid access to the SWT generates a bus error.
Page 749: Table 393. Swt_Ir Field Descriptions
RM0046 Functional Safety SWT Interrupt Register (SWT_IR) The SWT_IR contains the time-out interrupt flag. Figure 429. SWT Interrupt Register (SWT_IR) Address: Base + 0x0004 Access: User read/write Reset Reset Table 393. SWT_IR field descriptions Field Description Time-out Interrupt Flag The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect. 0 No interrupt request.
Page 750: Table 394. Swt_To Field Descriptions
Functional Safety RM0046 Table 394. SWT_TO field descriptions Field Description Watchdog time-out period in clock cycles An internal 32-bit down counter is loaded with this value or 0x0100, whichever is greater when the service sequence is written or when the SWT is enabled. SWT Window Register (SWT_WN) The SWT Window (SWT_WN) register contains the 32-bit window start value.
Page 751: Table 396. Swt_Sr Field Descriptions
RM0046 Functional Safety SWT Service Register (SWT_SR) The SWT Time-Out (SWT_SR) service register is the target for service sequence writes used to reset the watchdog timer. Figure 432. SWT Service Register (SWT_SR) Address: Base + 0x0010 Access: User read/write Reset Reset Table 396.
Page 752: Table 397. Swt_Co Field Descriptions
Functional Safety RM0046 Table 397. SWT_CO field descriptions Field Description Watchdog Count When the watchdog is disabled (SWT_CR.[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled the value of this field is 0x0000_0000. Values in this field can lag behind the internal counter value for as many as 6 system plus 8 counter clock cycles.
Page 753 RM0046 Functional Safety loaded into an internal 32-bit down counter when the SWT is enabled and a valid service sequence is written. The SWT_CR[CSL] bit selects which clock (system or oscillator) drives the down counter. The configuration of the SWT can be locked through use of either a soft lock or a hard lock. In either case, when locked the SWT_CR, SWT_TO and SWT_WN registers are read only.
Page 754: Fault Collection Unit (Fcu)
Fault Collection Unit (FCU) RM0046 Fault Collection Unit (FCU) 28.1 Introduction The Fault Collection Unit (FCU) module provides functional safety to the device. 28.1.1 Overview The FCU provides a central capability to collect faults reported by the individual modules of the device.
Page 755: Figure 435. Fault Collection Unit (Fcu) Block Diagram
RM0046 Fault Collection Unit (FCU) Fault Collection Unit Destructive reset FCU[0] Functional reset Input Output Control Unit Fault sources (finite state machine) Unit Unit FCU[1] 32-bit Clock/Reset/Power/Mode state 4-bit SYS_CLK IRC_CLK IPBus Figure 435. Fault Collection Unit (FCU) block diagram Figure 436 shows the flow chart of FCU fault handling.
Page 756: Figure 436. Fcu Fault Handling
Fault Collection Unit (FCU) RM0046 FCU detects a fault Fault is collected into FFR Fault enabled? FCU takes no action (FER) FCU goes into Fault Is Timeout state and communi- enabled for this fault? cates fault to the (FCTER) external pin. FCU goes into Alarm state and a timer is started.
Page 757: Features
RM0046 Fault Collection Unit (FCU) 28.1.2 Features The FCU includes the following features: ● Collection of critical faults ● Reporting of selected critical faults to external pins ● Fault flag status kept over non-destructive reset for later analysis (in a “Freeze” register) ●...
Page 758: Table 399. Fcu Memory Map
Fault Collection Unit (FCU) RM0046 28.2.1 Memory map Table 399. FCU memory map Offset from FCU_BASE Register Location (0xFFE6_C000) 0x0000 Module Configuration Register (FCU_MCR) on page 28-760 0x0004 Fault Flag Register (FCU_FFR) on page 28-761 0x0008 Frozen Fault Flag Register (FCU_FFFR) on page 28-763 0x000C Fake Fault Generation Register (FCU_FFGR)
Page 759 RM0046 Fault Collection Unit (FCU) Table 400. Register summary (continued) Name 0x0000_0008 FCU_FFFR 0x0000_000C FCU_FFGR 0x0000_0010 FCU_FER 0x0000_0014 FCU_KR TR[31:16] 0x0000_0018 FCU_TR TR[15:0] 0x0000_001C FCU_TER 0x0000_0020 FCU_MSR Doc ID 16912 Rev 5 759/936...
Page 760: Figure 437. Module Configuration Register (Fcu_Mcr)
Fault Collection Unit (FCU) RM0046 Table 400. Register summary (continued) Name MCPS[3:0] 0x0000_0024 FCU_MCSR MCAS[3:0] FRMCPS[3:0] 0x0000_0028 FCU_FMCSR FRMCAS[3:0] 28.2.3 Register descriptions Module Configuration Register (FCU_MCR) The FCU_MCR does the following: ● Locks the configuration and lets the FCU go into Normal behavior state ●...
Page 761: Table 401. Fcu_Mcr Field Description
RM0046 Fault Collection Unit (FCU) Table 401. FCU_MCR field description Field Description Module Configuration Lock 0: Configuration not locked, FCU remains in Init state 1: Configuration locked, FCU moves to Normal state Test Mode 00: Test Mode not entered 01: Test Mode entered (fake faults can be generated), output pins disabled TM[1:0] 10: Test Mode entered (fake faults can be generated), output pins enabled 11: Test Mode not entered...
Page 762: Table 402. Fcu_Ffr Field Descriptions
Fault Collection Unit (FCU) RM0046 Notice that software recoverable fault flags must be kept high also if the relative signal does not show anymore a fault. Hardware recoverable fault flags are updated in real time. Reset requests are assumed as hardware-recoverable. In order to clear a flag in the FCU_FFR via software, the application should access first time the Key Register (FCU_KR) by writing the value of a key (0x618B_7A50) second time resetting the appropriate flag.
Page 763: Figure 439. Frozen Fault Flag Register (Fcu_Fffr)
RM0046 Fault Collection Unit (FCU) Table 403. Hardware/software fault description (continued) Label Module Fault type HRF5 Not used HRF6 Not used HRF7 Flash Flash Fatal Error HRF8 SW Watchdog reset HRF9 JTAG JTAG reset (TAP controller) HRF10 Comparators HRF11 LVD 4.5 HRF12 LVD 2.7 VREG HRF13...
Page 764: Table 404. Fcu_Fffr Field Descriptions
Fault Collection Unit (FCU) RM0046 Table 404 provides a detailed bit description. Table 403 provides a detailed list of recoverable faults. Table 404. FCU_FFFR field descriptions Field Description Software Recoverable Fault FRSRF0– 0: No error latched FRSRF4 1: Error latched 16:31 Hardware Recoverable Fault FRHRF15...
Page 765: Table 406. Fcu_Fer Field Descriptions
RM0046 Fault Collection Unit (FCU) Fault Enable Register (FCU_FER) When a fault occurs, the FCU goes into either Alarm or Fault state (state is selected in the FCU_TER), if the respective fault enable bit is set in the Fault Enable Register (FCU_FER). This register can be configured only during the Init phase before the configuration is locked.
Page 766: Table 407. Fcu_Tr Field Descriptions
Fault Collection Unit (FCU) RM0046 Figure 442. Key Register (FCU_KR) Address: Base + 0x0014 Access: User read-only, Supervisor read-only Reset Reset Timeout Register (FCU_TR) Once the FCU goes into Alarm state, a fault can be recovered before the timeout elapses. This timeout should be long enough for hardware or software to recover from the fault.
Page 767: Table 408. Fcu_Ter Field Descriptions
RM0046 Fault Collection Unit (FCU) Timeout Enable Register (FCU_TER) Once a specific fault is enabled, the user can select to move to Alarm or Fault state when a fault occurs. A timeout enable has no effect if the related fault enable flag is not set. Figure 444.
Page 768: Table 409. Fcu_Msr Field Descriptions
Fault Collection Unit (FCU) RM0046 Table 409. FCU_MSR field descriptions Field Description When this bit is set, the FCU is in the Fault state. When this bit is set, the FCU is in the Alarm state. When this bit is set, the FCU is in the Normal state. When this bit is set, the FCU is in the Init state.
Page 769: Table 410. Fcu_Mcsr Field Description
RM0046 Fault Collection Unit (FCU) Table 410. FCU_MCSR field description Field Description MC Previous State 0000: RESET 0001: TEST 0010: SAFE 0011: DRUN 0100: RUN0 0101: RUN1 0110: RUN2 12:15 0111: RUN3 MCPS[3:0] 1000: HALT0 1001: Reserved 1010: STOP 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved...
Page 770: Table 411. Fcu_Fmcsr Field Description
Fault Collection Unit (FCU) RM0046 Frozen MC State Register (FCU_FMCSR) The FCU_MCSR is copied into the FCU_FMCSR each time the Fault state is entered. The FCU_FMCSR bit description is the same as that of the FCU_MCSR. Figure 447. Frozen MC State Register (FCU_FMCSR) Address: Base + 0x0028 Access: User read-only, Supervisor read-only FRMCPS[3:0]...
Page 771: Figure 448. Functional Block Diagram
RM0046 Fault Collection Unit (FCU) Table 411. FCU_FMCSR field description Field Description MC Actual State 0000: RESET 0001: TEST 0010: SAFE 0011: DRUN 0100: RUN0 0101: RUN1 28:31 0110: RUN2 FRMCAS 0111: RUN3 [3:0] 1000: HALT0 1001: Reserved 1010: STOP 1011: Reserved 1100: Reserved 1101: Reserved...
Page 772: Figure 449. Finite State Machine
Fault Collection Unit (FCU) RM0046 The register block implements all the FCU registers including input capture logic. The interface implements the read functionality and generated write and register enable signals. The timeout counter implements the counter to calculate timeout to switch from Alarm state to Fault state.
Page 773: Table 412. Dual-Rail Coding
RM0046 Fault Collection Unit (FCU) After a functional reset, the FCU_FFR (not the Frozen Fault Flag Register (FCU_FFFR)) must be cleared and the FCU must return to Normal state. 28.3.2 Output generation protocol The FCU provides two external output signals. The FCU supports different protocols for fault indication to the external device.
Page 774: Figure 450. Dual Rail Coding Example
Fault Collection Unit (FCU) RM0046 Reset Configuration phase Normal behavior Error occurred Reset is asserted FCU[0] FCU[1] During configuration phase fake faults can be injected so outputs may be different Figure 450. Dual rail coding example Time switching protocol FCU[0] is toggled between logic 0 and logic 1 with a defined frequency f = 1 kHz @ 64 MHz (f is approximated, as shown by Equation 34) and duty cycle d = 50%.
Page 775: Table 413. Bi-Stable Coding
RM0046 Fault Collection Unit (FCU) Bi-Stable protocol In this protocol during the Init and the Fault state, faulty state is indicated. In the Normal/Alarm state, non-faulty state is indicated. Table 413 shows bi-stable encoding for FCU[0]. Table 413. Bi-stable coding Logical value Bi-stable encoding faulty...
Page 776: Table 414. Wkpu Memory Map
Wakeup Unit (WKPU) RM0046 Wakeup Unit (WKPU) 29.1 Overview The Wakeup Unit (WKPU) supports one external source that causes non-maskable interrupt requests. 29.2 Features The WKPU provides non-maskable interrupt support with these features: ● 1 NMI source ● 1 analog glitch filter ●...
Page 777: Table 415. Nsr Field Descriptions
RM0046 Wakeup Unit (WKPU) 29.4.2 Registers description This section describes the Wakeup Unit registers. NMI Status Flag Register (NSR) This register holds the non-maskable interrupt status flags. Figure 453. NMI Status Flag Register (NSR) Address: Base + 0x0000 Access: User read/write R NIF NOVF W w1c Reset...
Page 778: Table 416. Ncr Field Descriptions
Wakeup Unit (WKPU) RM0046 NMI Configuration Register (NCR) This register holds the configuration bits for the non-maskable interrupt settings. Figure 454. NMI Configuration Register (NCR) Address: Base + 0x0008 Access: User read/write NDSS Reset Reset Table 416. NCR field descriptions Field Description NMI Configuration Lock Register...
Page 779: Figure 455. Nmi Pad Diagram
RM0046 Wakeup Unit (WKPU) 29.5 Functional description 29.5.1 General This section provides a complete functional description of the Wakeup Unit. 29.5.2 Non-Maskable Interrupts The Wakeup Unit supports one non-maskable interrupt, which is allocated to pin 1. The Wakeup Unit supports the generation of three types of interrupts from the NMI input to the device.
Page 780 Wakeup Unit (WKPU) RM0046 NMI management The NMI can be enabled or disabled using the single NCR register laid out to contain all configuration bits for an NMI in a single byte (see Figure 454). The pad defined as an NMI can be configured by the user to recognize interrupts with an active rising edge, an active falling edge or both edges being active.
Page 781: Figure 456. Pit Block Diagram
RM0046 Periodic Interrupt Timer (PIT) Periodic Interrupt Timer (PIT) 30.1 Introduction The Periodic Interrupt Timer (PIT) block implements several timers that can be used for DMA triggering, general purpose interrupts and system wakeup. Figure 456 shows the PIT block diagram. load_value Timer 0 timeout...
Page 782: Table 417. Pit Memory Map
Periodic Interrupt Timer (PIT) RM0046 30.2 Signal description The PIT module has no external pins. 30.3 Memory map and registers description This section provides a detailed description of all registers accessible in the PIT module. 30.3.1 Memory map Table 417 gives an overview on all PIT registers.
Page 783: Table 418. Pitmcr Field Descriptions
RM0046 Periodic Interrupt Timer (PIT) Note: Reserved registers read as 0. Writes have no effect. 30.3.2 Registers description This section describes in address order all the PIT registers and their individual bits. PIT registers are accessible only when the core is in supervisor mode (see Section 15.4.3, “ECSM_reg_protection).
Page 784: Table 419. Ldvaln Field Descriptions
Periodic Interrupt Timer (PIT) RM0046 Timer Load Value Register n (LDVALn) These registers select the timeout period for the timer interrupts. Figure 458. Timer Load Value Register n (LDVALn) Channel Base + 0x0000 LDVAL0 = PIT_BASE + 0x0100 Address: LDVAL1 = PIT_BASE + 0x0110 Access: User read/write LDVAL2 = PIT_BASE + 0x0120 LDVAL3 = PIT_BASE + 0x0130...
Page 785: Table 420. Cvaln Field Descriptions
RM0046 Periodic Interrupt Timer (PIT) Current Timer Value Register n (CVALn) These registers indicate the current timer position. Figure 459. Current Timer Value register n (CVALn) Channel Base + 0x0004 CVAL0 = PIT_BASE + 0x0104 Address: CVAL1 = PIT_BASE + 0x0114 Access: User read-only CVAL2 = PIT_BASE + 0x0124 CVAL3 = PIT_BASE + 0x0134...
Page 786: Table 421. Tctrln Field Descriptions
Periodic Interrupt Timer (PIT) RM0046 Timer Control Register n (TCTRLn) The TCTRL register contains the control bits for each timer. Figure 460. Timer Control register n (TCTRLn) Channel Base + 0x0008 TCTRL0 = PIT_BASE + 0x0108 Address: TCTRL1 = PIT_BASE + 0x0118 Access: User read/write TCTRL2 = PIT_BASE + 0x0128 TCTRL3 = PIT_BASE + 0x0138...
Page 787: Table 422. Tflgn Field Descriptions
RM0046 Periodic Interrupt Timer (PIT) Timer Flag Register n (TFLGn) These registers contain the PIT interrupt flags. Figure 461. Timer Flag register n (TFLGn) Channel Base + 0x000C TFLG0 = PIT_BASE + 0x010C Address: TFLG1 = PIT_BASE + 0x011C Access: User read/write TFLG2 = PIT_BASE + 0x012C TFLG3 = PIT_BASE + 0x013C Reset...
Page 788: Figure 462. Stopping And Starting A Timer
Periodic Interrupt Timer (PIT) RM0046 The counter period of a running timer can be modified, by first disabling the timer, setting a new load value and then enabling the timer again (see Figure 463). It is also possible to change the counter period without restarting the timer by writing the LDVAL register with the new load value.
Page 789: Interrupts
RM0046 Periodic Interrupt Timer (PIT) 30.4.2 Interrupts All of the timers support interrupt generation. Refer to 9, “Interrupt Controller (INTC) related vector addresses and priorities. Timer interrupts can be disabled by setting the TIE bits to zero. The timer interrupt flags (TIF) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that TIF bit.
Page 790: Table 423. Stm Memory Map
System Timer Module (STM) RM0046 System Timer Module (STM) 31.1 Overview The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256).
Page 791: Figure 465. Stm Control Register (Stm_Cr)
RM0046 System Timer Module (STM) Table 423. STM memory map (continued) Offset from STM_BASE Register Location 0xFFF3_C000 0x0008–0x000F Reserved 0x0010 STM_CCR0—STM Channel 0 Control Register on page 31-793 0x0014 STM_CIR0—STM Channel 0 Interrupt Register on page 31-793 0x0018 STM_CMP0—STM Channel 0 Compare Register on page 31-794 0x001C Reserved...
Page 792: Table 424. Stm_Cr Field Descriptions
System Timer Module (STM) RM0046 Table 424. STM_CR field descriptions Field Description Counter Prescaler Selects the clock divide value for the prescaler (1 - 256). 0x00 Divide system clock by 1. CPS[7:0] 0x01 Divide system clock by 2. 0xFF Divide system clock by 256. Freeze Allows the timer counter to be stopped when the device enters debug mode.
Page 793: Table 426. Stm_Ccrn Field Descriptions
RM0046 System Timer Module (STM) STM Channel Control Register (STM_CCRn) The STM Channel Control Register (STM_CCRn) enables and services channel n of the timer. Figure 467. STM Channel Control Register (STM_CCRn) Base + 0x0010 (STM_CCR0) Address: Base + 0x0020 (STM_CCR1) Access: User read/write Base + 0x0030 (STM_CCR2) Reset...
Page 794: Table 427. Stm_Cirn Field Descriptions
System Timer Module (STM) RM0046 Table 427. STM_CIRn field descriptions Field Description Channel Interrupt Flag The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect. 0 No interrupt request. 1 Interrupt request due to a match on the channel. STM Channel Compare Register (STM_CMPn) The STM Channel Compare Register (STM_CMPn) holds the compare value for channel n.
Page 795: Functional Description
RM0046 System Timer Module (STM) 31.6 Functional description The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The STM has one 32-bit up counter (STM_CNT) that is used as the time base for all channels.
Page 796: Cyclic Redundancy Check (Crc)
Cyclic Redundancy Check (CRC) RM0046 Cyclic Redundancy Check (CRC) 32.1 Introduction The Cyclic Redundancy Check (CRC) computing unit is dedicated to the computation of CRC, thus off-loading the CPU. The SPC560P40/34 CRC supports two contexts. Each context has a separate CRC computation engine in order to allow the concurrent computation of the CRC of multiple data streams.
Page 797: Figure 470. Crc Top Level Diagram
RM0046 Cyclic Redundancy Check (CRC) Config and Data Registers Engine Engine context 1 context 1 context 2 context 2 Figure 470. CRC top level diagram 32.3.1 IPS bus interface The IPS bus interface is a slave bus used for configuration and data streaming (CRC computation) purposes via CPU or DMA.
Page 798: Figure 471. Crc-Ccitt Engine Concept Scheme
Cyclic Redundancy Check (CRC) RM0046 The data stream is generally executed by N concurrent DMA data transfers (mem2mem) where N is less or equal to the number of contexts. Two standard generator polynomials are given in Equation 35 Equation 36 for the CRC computation of each context.
Page 799: Table 429. Crc Memory Map
RM0046 Cyclic Redundancy Check (CRC) context = n context = 1 START CRC configuration (polynomial, swap, inversion) setting the CRC_CFG register CRC seed initialization (CRC_CSTAT register) Data is written in the CRC_INP register (byte/half word/word) by CPU or DMA All the data has been passed to the CRC unit CRC signature available...
Page 800: Table 430. Crc_Cfg Field Descriptions
Cyclic Redundancy Check (CRC) RM0046 Table 429. CRC memory map (continued) Offset from CRC_BASE Register Location 0xFFE6_8000 0x0010 CRC_CFG—CRC Configuration Register, Context 2 on page 32-800 0x0014 CRC_INP—CRC Input Register, Context 2 on page 32-801 0x0018 CRC_CSTAT—CRC Current Status Register, Context 2 on page 32-802 0x001C CRC_OUTP—CRC Output Register,...
Page 801: Table 431. Crc_Inp Field Descriptions
RM0046 Cyclic Redundancy Check (CRC) Table 430. CRC_CFG field descriptions (continued) Field Description SWAP: SWAP selection 0: No swap selection applied on the CRC_OUTP content 1: Swap selection (MSB -> LSB, LSB -> MSB) applied on the CRC_OUTP content. In case of CRC- CCITT polynomial the swap operation is applied on the 16 LSB bits.
Page 802: Table 432. Crc_Cstat Field Descriptions
Cyclic Redundancy Check (CRC) RM0046 32.5.3 CRC Current Status Register (CRC_CSTAT) Figure 475. CRC Current Status Register (CRC_CSTAT) Context 1: Base + 0x0008 Address: Access: User read/write Context 2: Base + 0x0018 CSTAT Reset CSTAT Reset Table 432. CRC_CSTAT field descriptions Field Description CSTAT: Status of the CRC signature...
Page 803: Table 433. Crc_Outp Field Descriptions
RM0046 Cyclic Redundancy Check (CRC) Table 433. CRC_OUTP field descriptions Field Description OUTP: Final CRC signature The OUTP register includes the final signature corresponding to the CRC_CSTAT register value eventually swapped and inverted. 0:31 In case of CRC-CCITT polynomial only the16 LSB bits are significant. The 16 MSB bits are tied at 0b during the computation.
Page 804: Figure 477. Dma-Crc Transmission Sequence
Cyclic Redundancy Check (CRC) RM0046 Transmission Phase 1 Memory CRC (context x) Payload CRC_INP (mem2mem CRC_OUTP channel x) Transmission Phase 2 Memory CRC (context x) CRC_INP Payload CRC_OUTP CRC Checksum Transmission Phase 3 Memory Tx FIFO Payload (mem2periph CRC Checksum channel x) Figure 477.
Page 805: Figure 478. Dma-Crc Reception Sequence
RM0046 Cyclic Redundancy Check (CRC) ● Data block transfer (payload + CRC) transfer from the MEM to the CRC module (CRC_INP register) to calculate the CRC signature (phase 2) by DMA (mem2mem data transfer, channel x) ● CRC signature check from the CRC module (CRC_OUTP register) by CPU (phase 3)1 Reception Phase 1 Memory Rx FIFO...
Page 806: Table 434. Bam Memory Organization
Boot Assist Module (BAM) RM0046 Boot Assist Module (BAM) 33.1 Overview The Boot Assist Module is a block of read-only memory containing VLE code that is executed according to the boot mode of the device. The BAM allows downloading boot code via the FlexCAN or LINFlex interfaces into internal SRAM and then executing it.
Page 807: Figure 479. Boot Mode Selection
RM0046 Boot Assist Module (BAM) 33.5 Functional description 33.5.1 Entering boot modes The SPC560P40/34 detects the boot mode based on external pins and device status. The following sequence applies (see Figure 479): ● To boot either from FlexCAN or LINFlex, the device must be forced into an Alternate Boot Loader Mode via the FAB (Force Alternate Boot Mode), which must be asserted before initiating the reset sequence.
Page 808: Table 435. Hardware Configuration To Select Boot Mode
Boot Assist Module (BAM) RM0046 Boot configuration pins are: ● PAD A[2] - ABS[0], ● PAD A[3] - ABS[1], ● PAD A[4] - FAB Table 435. Hardware configuration to select boot mode Standby-RAM ABS[1:0] Boot ID Boot Mode Boot Flag —...
Page 809: Table 437. Rchw Field Descriptions
RM0046 Boot Assist Module (BAM) 33.5.3 Reset Configuration Half Word (RCHW) The SPC560P40/34 Flash is partitioned into boot sectors as shown in Table 438. Each boot sector contains the Reset Configuration Half-Word (RCHW) at offset 0x00. Figure 480. Reset Configuration Half Word (RCHW) Address: Base + 0x0000 Access: User read-only BOOT_ID[0:7]...
Page 810: Table 438. Flash Boot Sector
Boot Assist Module (BAM) RM0046 128K 0x0002 0000 Boot information 0x0001 8000 Boot information 0x0001 0000 0x0000 C000 Boot information Application 0x0000 000C Application 0x0000 8000 Boot information 0x0000 0008 Application start address 0x0000 0004 RCHW 0x0000 0000 Boot information 0x0000 0000 Internal Flash Figure 481.
Page 811: Boot Through Bam
RM0046 Boot Assist Module (BAM) Then the device executes this startup code. A user application should have a valid instruction at the reset boot vector address. If a valid RCHW is not found, the BAM code is executed. In this case BAM moves the SPC560P40/34 into static mode.
Page 812: Figure 482. Bam Logic Flow
Boot Assist Module (BAM) RM0046 BAM software flow Figure 482 illustrates the BAM logic flow. BAM entry 0xFFFF_C000 Save default configuration The selected boot mode is verified by reading the SSCM_STATUS register (bits BMODE and ABD) Check boot mode Restore Boot mode default STATIC mode...
Page 813: Table 439. Fields Of Sscm Status Register Used By Bam
RM0046 Boot Assist Module (BAM) Table 439. Fields of SSCM STATUS register used by BAM Field Description Device Boot Mode 000 Test Flash/autobaud_scan 001 CAN Serial Boot Loader BMODE 010 SCI Serial Boot Loader [2:0] 011 Single Chip 100–111Reserved This field is updated only during reset. Then, the initial device configuration is restored and the code jumps to the address of downloaded code.
Page 814 Boot Assist Module (BAM) RM0046 Table 440. Serial boot mode without autobaud—baud rates Crystal frequency LINFlex baud rate FlexCAN bit rate (MHz) (baud) (bit/s) 19200 400 K 24000 500 K 48000 Download and execute the new code From a high level perspective, the download protocol follows these steps: Send message and receive acknowledge message for autobaud or autobit rate selection.
Page 815 RM0046 Boot Assist Module (BAM) If public access is not allowed but the flash is not secured, the received password is compared with the value saved on NVPWD0 and NVPWD1 registers. In uncensored devices, it is possible to download code via LINFlex or FlexCAN (serial boot mode) into internal SRAM with any 64-bit private password stored in the flash and provided during the boot sequence.
Page 816: Figure 483. Password Check Flow
Boot Assist Module (BAM) RM0046 SSCM. Comparison with STATUS. FEEDFACE CAFEBEEF SSCM. Comparison with STATUS. password saved on NVPWD[0:1] Write received password to SSCM.PWCMPH-L Wait Verify whether Flash is unsecured Figure 483. Password check flow Download start address, VLE bit and code size The next 8 bytes received by the MCU contain a 32-bit Start Address, the VLE mode bit and a 31-bit code Length as shown in Figure...
Page 817: Figure 484. Start Address, Vle Bit And Download Size In Bytes
RM0046 Boot Assist Module (BAM) START_ADDRESS[31:16] START_ADDRESS[15:0] CODE_LENGTH[30:16] CODE_LENGTH[15:0] Figure 484. Start address, VLE bit and download size in bytes Download data Each byte of data received is stored into device’s SRAM, starting from the address specified in the previous protocol step. The address increments until the number of bytes of data received matches the number of bytes specified in the previous protocol step.
Page 818: Table 441. Uart Boot Mode Download Protocol (Autobaud Disabled)
Boot Assist Module (BAM) RM0046 Byte Field Start Stop Figure 485. LINFlex bit timing in UART mode UART boot mode download protocol Table 441 summarizes the download protocol and BAM action during the UART boot mode. Table 441. UART boot mode download protocol (autobaud disabled) Protocol Host sent BAM response...
Page 819: Table 442. Flexcan Boot Mode Download Protocol (Autobaud Disabled)
RM0046 Boot Assist Module (BAM) NRZ Signal SYNC_SEG Time Segment 1 Time Segment 2 time quanta time quanta time quanta 1 Bit Time Sample Point Transmit Point 1 time Quanta = 4 system clock periods Figure 486. FlexCAN bit timing 33.6 FlexCAN boot mode download protocol Table 442...
Page 820: Table 443. System Clock Frequency Related To External Clock Frequency
Boot Assist Module (BAM) RM0046 Configuration SPC560P40/34 devices implement the autobaud feature via FlexCAN or LINFlex selecting the active serial communication peripheral by means of an autoscan routine. When autobaud configuration is selected by ABS and FAB pins, the autoscan routine starts and listens to the active bus protocol.
Page 821 RM0046 Boot Assist Module (BAM) After setting up the system clock, the BAM autoscan code configures the FlexCAN RX pin (B[1] on all packages) and LINFlex RX pin (B[3] on LQFP100 or B[7] on LQFP64) as GPIO inputs and searches for FlexCAN RX pin level to verify if CAN is connected or not. Then continuously waits in polling on change of RX pins level.The FlexCAN RX pin level takes precedence.
Page 822: Figure 487. Bam Autoscan Code Flow
Boot Assist Module (BAM) RM0046 Figure 487. BAM Autoscan code flow FlexCAN RX and LINFlex RX Both RDX pins have to be at high level. configured as GPIO inputs Avoid to connect them to external pull-down resistor. If CAN is connected, after reset CAN_RX has to be FlexCAN RX at high level == 1...
Page 823: Figure 489. Bam Rate Measurement Flow During Uart Boot
RM0046 Boot Assist Module (BAM) The LINFlex module is configured to work in UART mode with the calculated baud rate. Then an acknowledge byte (0x59, ASCII char “Y”) is sent. From this point, the BAM follows the normal UART mode boot protocol (see Figure 489).
Page 824: Table 444. Maximum And Minimum Recommended Baud Rates
Boot Assist Module (BAM) RM0046 SCI autobaud rate feature operates by polling the LINFlex_RX pin for a low signal. The length of time until the next low to high transition is measured using the System Timer Module (STM) time base. This high-low-high transition is expected to be a zero byte: a start bit (low) followed by eight data bits (low) followed by a stop bit (high).
Page 825: Figure 490. Baud Rate Deviation Between Host And Spc560P40/34
RM0046 Boot Assist Module (BAM) Table 444. Maximum and minimum recommended baud rates (continued) Max baud rate for guaranteed Min baud rate for guaranteed (MHz) xtal < 2.5% deviation < 2.5% deviation 51.2 Kbit/s 120 bit/s (SBR = 20) (SBR = 8192) 64.0 Kbit/s 150 bit/s (SBR = 20)
Page 826: Figure 491. Bit Time Measure
Boot Assist Module (BAM) RM0046 Boot from FlexCAN with autobaud enabled The only difference between booting from FlexCAN with autobaud enabled and booting from FlexCAN with autobaud disabled is that the following initialization FlexCAN frame is sent for baud measurement purposes from the host to the MCU when autobaud is enabled: ●...
Page 827: Figure 492. Bam Rate Measurement Flow During Flexcan Boot
RM0046 Boot Assist Module (BAM) Start CAN_0_RX pin configured as If CAN is connected, GPIO input CAN_RX should be at high level CAN_RX == 1 ERROR CAN_RX == 0 Start STM Wait for the first recessive (HIGH) bit CAN_RX == 1 Read STM.
Page 828: Table 445. Prescaler/Divider And Time Base Values
Boot Assist Module (BAM) RM0046 Choosing the host baud rate The calculation of the FlexCAN baud rate allows the operation of the boot loader with a wide range of baud rates. However, to ensure proper data transfer, the upper and lower limits have to be kept.
Page 829: Table 446. Flexcan Standard Compliant Bit Timing Segment Settings
RM0046 Boot Assist Module (BAM) Table 446. FlexCAN standard compliant bit timing segment settings Time Segment 1 Time Segment 2 5..10 1..2 4..11 1..3 5..12 1..4 6..13 1..4 7..14 1..4 8..15 1..4 9..16 1..4 Timing segment 2 is kept as large as possible to keep sample time within bit time. Table 447.
Page 830: Table 449. Presdiv + 1 > 1 (Yy = Presdiv)
Boot Assist Module (BAM) RM0046 Table 449. PRESDIV + 1 > 1 (YY = PRESDIV) Desired number of time quanta Register contents for CANA_CR 0xYY49_2002 0xYY49_2003 0xYY49_2004 0xYY49_2005 0xYY49_2006 0xYY49_2007 0xYY52_2007 0xYY52_2008 0xYY5B_2008 0xYY5B_2009 0xYY64_2009 0xYY64_200A 0xYY6D_200A 0xYY6D_200B 0xYY76_200B 0xYY76_200C 0xYY7F_200C 0xYY7F_200D Worked examples showing FlexCAN Autobaud rate:...
Page 831: Interrupt
RM0046 Boot Assist Module (BAM) Example 2020 MHz crystal Consider case where using a 20 MHz crystal, user attempts to send 62.5 Kb/s FlexCAN message. – Time base, clocking at crystal frequency, would measure: – 62.5 Kb/s = 320 clocks/bit => 29 * 320 = 9280 clocks –...
Page 832: Table 450. Examples Of Legal And Illegal Passwords
Boot Assist Module (BAM) RM0046 This means that even if censorship was inadvertently enabled by writing to the censorship control registers, there is an opportunity to get back into the microcontroller using the default private password of 0xFEED_FACE_CAFE_BEEF. When configuring the private password, each half word (16-bit) must contain at least one "1" and one "0".
Page 833: Table 451. Censorship Configuration And Truth Table
RM0046 Boot Assist Module (BAM) Table 451 shows all the possible modes of censorship. The red shaded areas are to be avoided as these show the configuration for a device that is permanently locked out. If you wish to enable censorship with a private password there is only one valid configuration — to modify the CW field in both NVSCI0,1 registers so they match but do not equal 0x55AA.
Page 834: Figure 493. Censorship Control In Flash Memory Boot Mode
Boot Assist Module (BAM) RM0046 password has been programmed into the shadow flash memory in the order {NVPWD0, NWPWD1} and has a value of 0x01234567_89ABCDEF. FAB = 0 (Flash boot mode) Censored with no True NVSCI0 != password access NVSCI1 (Locked out) False Both...
Page 835: Figure 494. Censorship Control In Serial Boot Mode
RM0046 Boot Assist Module (BAM) FAB = 1 (Serial boot mode) Censored with no True NVSCI0 != password access NVSCI1 (Locked out) False Both Censored with no True SC and CW != password access 0x55AA (Locked out) False Serial password details: True Public password, Enter public password...
Page 836: Voltage Regulators And Power Supplies
Voltage Regulators and Power Supplies RM0046 Voltage Regulators and Power Supplies 34.1 Voltage regulator The power blocks are used for providing 1.2 V digital supply to the internal logic of the device. The main/input supply is 3.3 V to 5.0 V ±10% and the digital/regulated output supply has a trim target voltage of 1.28 V.
Page 837: Vreg Digital Interface
RM0046 Voltage Regulators and Power Supplies An LVD_DIG in the regulator senses the HPREG output. It provides V MLVDDOK_H as active high signals. MLVDOK_L The reference voltage used for all LVDs is trimmed for LVD_DIG using the bits LP[4:7]. Therefore, during the pre-trimming period, LVD_DIG exhibits higher thresholds, whereas post trimming, the thresholds come in the desired range.
Page 838: Table 452. Vreg_Ctl Field Descriptions
Voltage Regulators and Power Supplies RM0046 34.1.4 Registers Description Voltage Regulator Control Register (VREG_CTL) Figure 495. Voltage Regulator Control register (VREG_CTL) Address: Base + 0x0080 Access: User read/write Reset Reset Table 452. VREG_CTL field descriptions Field Description Mask bit for 5 V LVD from regulator This is a read/write bit and must be unmasked by writing a 1 by software to generate LVD functional reset request to RGM for 5V trip.
Page 839: Table 453. Vreg_Status Field Descriptions
RM0046 Voltage Regulators and Power Supplies Voltage Regulator Status register (VREG_STATUS) Figure 496. Voltage Regulator Status register (VREG_STATUS) Address: Base + 0x0084 Access: User read-only Reset Reset Table 453. VREG_STATUS field descriptions Field Description Status bit for 5 V LVD from regulator 5V_LVD_STATUS 05 V LVD not OK 15 V LVD OK...
Page 840 Voltage Regulators and Power Supplies RM0046 The three dedicated supply domains are further divided within the package in order to reduce EMI and noise as much as possible: ● HV_REG—High voltage regulator supply ● HV_IOn—High voltage PAD supply ● HV_OSC —High voltage external oscillator and regulator supply ●...
Page 841: Figure 497. Jtag Controller Block Diagram
RM0046 IEEE 1149.1 Test Access Port Controller (JTAGC) IEEE 1149.1 Test Access Port Controller (JTAGC) 35.1 Introduction The JTAG port of the device consists of three inputs and one output. These pins include test data input (TDI), test mode select (TMS), test clock input (TCK) and test data output (TDO). TDI, TMS, TCK and TDO are compliant with the IEEE 1149.1-2001 standard and are shared with the NDI through the test access port (TAP) interface.
Page 842: Features
IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046 35.4 Features The JTAGC is compliant with the IEEE 1149.1-2001 standard, and supports the following features: ● IEEE 1149.1-2001 Test Access Port (TAP) interface ● Four pins (TDI, TMS, TCK, and TDO)—see Section 35.6, “External signal description.
Page 843: Table 454. Jtag Signal Properties
RM0046 IEEE 1149.1 Test Access Port Controller (JTAGC) Bypass mode When no test operation is required, the BYPASS instruction can be loaded to place the JTAGC into bypass mode. While in bypass mode, the single-bit bypass shift register provides a minimum-length serial path to shift data between TDI and TDO. TAP sharing mode There are four selectable auxiliary TAP controllers that share the TAP with the JTAGC.
Page 844: Figure 498. 5-Bit Instruction Register
IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046 35.7.1 Instruction register The JTAGC uses a 5-bit instruction register as shown in Figure 498. The instruction register allows instructions to be loaded into the module to select the test to be performed or the test data register to be accessed or both.
Page 845: Table 455. Device Identification Register Field Descriptions
RM0046 IEEE 1149.1 Test Access Port Controller (JTAGC) Table 455. Device identification register field descriptions Field Description 0–3 Part revision number. Contains the revision number of the device. This field changes with each revision of the device or module. 4–9 Design center.
Page 846: Tap Controller State Machine
IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046 35.8.3 TAP controller state machine The TAP controller is a synchronous state machine that interprets the sequence of logical values on the TMS pin. Figure 501 shows the machine’s states. The value shown next to each state is the value of the TMS signal sampled on the rising edge of the TCK signal.
Page 847: Figure 501. Ieee 1149.1-2001 Tap Controller Finite State Machine
RM0046 IEEE 1149.1 Test Access Port Controller (JTAGC) Test logic reset Select-DR-scan Run-test/idle Select-IR-scan Capture-DR Capture-IR Shift-IR Shift-DR Exit1-IR Exit1-DR Pause-DR Pause-IR Exit2-IR Exit2-DR Update-DR Update-IR NOTE: The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK. Figure 501.
Page 848: Table 456. Jtag Instructions
IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046 Selecting an IEEE 1149.1-2001 register Access to the JTAGC data registers is done by loading the instruction register with any of the JTAGC instructions while the JTAGC is enabled. Instructions are shifted in via the select- IR-scan path and loaded in the update-IR state.
Page 849 RM0046 IEEE 1149.1 Test Access Port Controller (JTAGC) Table 456. JTAG instructions (continued) Instruction Code[4:0] Instruction summary 00101 00110 Factory Debug Reserved Intended for factory debug only 01010 All Other Reserved Decoded to select bypass register Codes 1. Intended for factory debug, and not customer use. BYPASS instruction BYPASS selects the bypass register, creating a single-bit shift register path between TDI and TDO.
Page 850: Boundary Scan
IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046 IDCODE instruction IDCODE selects the 32-bit device identification register as the shift path between TDI and TDO. This instruction allows interrogation of the MCU to determine its version number and other part identification data. IDCODE is the instruction placed into the instruction register when the JTAGC is reset.
Page 851: Figure 502. E200Z0 Once Block Diagram
RM0046 IEEE 1149.1 Test Access Port Controller (JTAGC) e200z0_TRST Test Access Port (TAP) From JTAGC Controller e200z0_TMS TDO Mux Control TAP Instruction Register (OnCE OCMD) Bypass Register e200z0_TDO (to JTAGC) External Data Register OnCE Mapped Debug Registers Auxiliary Data Register Figure 502.
Page 852: Table 457. E200Z0 Once Register Addressing
IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046 controlling access to a resource, as well as controlling single-step operation and exit from OnCE mode. Although the OCMD is updated during the update-IR TAP controller state, the corresponding resource is accessed in the DR scan sequence of the TAP controller, and as such, the update-DR state must be transitioned through in order for an access to occur.
Page 853: Initialization/Application Information
RM0046 IEEE 1149.1 Test Access Port Controller (JTAGC) Table 457. e200z0 OnCE register addressing (continued) RS[0:6] Register selected Shared Nexus Control Register (SNC) 110 1111 (only available on the e200z0 core) 111 0000 – 111 1001 General Purpose Register Selects [0:9] 111 1010 –...
Page 854: Nexus Development Interface (Ndi)
Nexus Development Interface (NDI) RM0046 Nexus Development Interface (NDI) 36.1 Introduction The Nexus Development Interface (NDI) block provides development support capabilities for the SPC560P40/34 MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility.
Page 855: Figure 504. Ndi Functional Block Diagram
RM0046 Nexus Development Interface (NDI) 36.3 Block diagram Figure 504 shows a functional block diagram of the NDI. Figure 504. NDI functional block diagram 36.4 Features The NDI module of the SPC560P40/34 is compliant with Class 1 of the IEEE-ISTO 5001- 2003 standard.
Page 856: Modes Of Operation
Nexus Development Interface (NDI) RM0046 Note: If the e200z0 core has executed a wait instruction, then the Nexus1 controller clocks are gated off. While the core is in this state, it is not possible to perform Nexus read/write operations. 36.5 Modes of operation The NDI block is in reset when the TAP controller state machine is in the TEST-LOGIC- RESET state.
Page 857: Memory Map And Registers Description
RM0046 Nexus Development Interface (NDI) 36.7 Memory map and registers description The NDI block contains no memory-mapped registers. Nexus registers are accessed by a development tool via the JTAG port using a client-select value and a register index. OnCE registers are accessed by loading the appropriate value in the RS[0:6] field of the OnCE command register (OCMD) via the JTAG port.
Page 858: Debug Support Overview
Nexus Development Interface (NDI) RM0046 36.9 Debug support overview Internal debug support in the e200z0h core allows for software and hardware debug by providing debug functions, such as instruction and data breakpoints and program trace modes. For software based debugging, debug facilities consisting of a set of software accessible debug registers and interrupt mechanisms are provided.
Page 859: Hardware Debug Facilities
RM0046 Nexus Development Interface (NDI) e200z0h also defines two new debug events (CIRPT, CRET) for debugging around critical interrupts. In addition, e200z0h implements the Debug APU, which when enabled allows Debug Interrupts to utilize a dedicated set of save/restore registers (DSRR0, DSRR1) for saving state information when a Debug Interrupt occurs, and for restoring this state information at the end of a debug interrupt handler by means of the se_rfdi instruction.
Page 860 Nexus Development Interface (NDI) RM0046 all registers and all register fields through the OnCE register access mechanism, and it is up to the debug firmware to properly implement modifications to these registers with read- modify-write operations to implement any control sharing with software. Settings in DBERC0 should be considered by the debug firmware in order to preserve software settings of control and status registers as appropriate when hardware modifications to the debug registers is performed.
Page 861: Figure 505. E200Z0H Debug Resources
RM0046 Nexus Development Interface (NDI) cpu_dbgack dbg_dbgrq Pipeline Breakpoint and Information Trace Logic j_tclk OnCE DATA# Controller j_tdi ADDR# j_tdo, j_tdo_en ATTR# Serial PSTAT# Interface j_tms j_trst_b jd_en_once Debug Registers jd_de_b jd_mclk_on Comparators #-internal signals to/from CPU only p_ude p_devt[1,2] jd_watchpt[0:n] jd_de_en jd_debug_b...
Page 862: Instruction Address Compare Event
Nexus Development Interface (NDI) RM0046 cause debug exceptions and set DBSR bits regardless of the state of MSR . A Debug interrupt will be delayed until MSR is later set to ‘1’. When a Debug Status Register bit is set while MSR =0, and DBCR0 =0 or DBCR0...
Page 863: Data Address Compare Event
RM0046 Nexus Development Interface (NDI) IAC compares perform a 31-bit compare for VLE instructions. Each halfword fetched by the instruction fetch unit will be marked with a set of bits indicating whether an Instruction Address Compare occurred on that halfword. Debug exceptions will occur if enabled and a 16-bit instruction, or the first halfword of a 32-bit instruction, is tagged with an IAC hit.
Page 864: Table 458. Dac Events And Resultant Updates
No ESR update. No debug counter updates for 2nd ld/st instruction. DVC DACx DTLB Error, no DAC Note: in this case the 2nd ld/st exception is masked. This behavior is implementation dependent and may differ on other CPUs. Take Debug exception, DBSR update setting DACx, DAC_OFST not set.
Page 865: Linked Instruction Address And Data Address Compare Event
DVC DACx DVC DACy Note: in this case debug counter updates occur for the 2nd ld/st even though the 1st ld/st has a DVC DAC exception. Note: in this case if x==y, then the resultant state of DBSR and DSRR0 may be indistinguishable from the “no DACy”...
Page 866: Trap Debug Event
Nexus Development Interface (NDI) RM0046 Instruction Address Compare event, a Linked Data Address Compare debug event occurs. This event can occur and be recorded in DBSR regardless of the setting of MSR . The normal DAC1 and DAC2 status bits in the DBSR are used for recording these events. The IAC1 and IAC3 status bits are not set if the corresponding Instruction Address Compare register is linked.
Page 867: Critical Interrupt Taken Debug Event
RM0046 Nexus Development Interface (NDI) an Interrupt Taken debug event. This event can occur and be recorded in DBSR regardless of the setting of MSR . When an Interrupt Taken debug event occurs, the DBSR bit is IRPT set to ‘1’ to record the debug exception. The value saved in DSRR0 will be the address of the non-critical interrupt handler.
Page 868: Unconditional Debug Event
Nexus Development Interface (NDI) RM0046 36.10.12 Unconditional Debug Event An Unconditional debug event (UDE) occurs when the Unconditional Debug Event (p_ude) input transitions to the asserted state, and either DBCR0 =1 or DBCR0 =1. The Unconditional debug event is the only debug event which does not have a corresponding enable bit for the event in DBCR0.
Page 869: Figure 506. Dvc1, Dvc2 Registers
RM0046 Nexus Development Interface (NDI) participate in the comparison, they are implicitly masked. Software must also program the DVC1(2) register byte positions based on the endian mode and alignment of the access. Misaligned accesses are not fully supported, since the data address and data value comparisons are only performed on the initial access in the case of a misaligned access;...
Page 870: Table 459. Dbcr0 Bit Definitions
Nexus Development Interface (NDI) RM0046 Figure 507. DBCR0 Register SPR - 308; Reset Reset 1. DBCR0 is affected by j_trst_b or m_por assertion, and remains reset while in the Test_Logic_Reset state, but is not affected by p_reset_b. All other bits are reset by processor reset p_reset_b if DBCR0 =0, as well as unconditionally by m_por.
Page 871 RM0046 Nexus Development Interface (NDI) Table 459. DBCR0 Bit Definitions (continued) Bit(s) Name Description Reset Control 00 – No function 01 – Reserved 10 – p_resetout_b pin asserted by Debug Reset Control. Allows external device to initiate processor reset. 11 – Reserved Instruction Complete Debug Event Enable ICMP 0 –...
Page 872: Figure 508. Dbcr1 Register
Nexus Development Interface (NDI) RM0046 Table 459. DBCR0 Bit Definitions (continued) Bit(s) Name Description Return Debug Event Enable 0 – RET debug events are disabled 1 – RET debug events are enabled 17:20 — Reserved External Debug Event 1 Enable DEVT1 0 –...
Page 873: Table 460. Dbcr1 Bit Definitions
RM0046 Nexus Development Interface (NDI) Table 460 provides bit definitions for Debug Control Register 1. Table 460. DBCR1 Bit Definitions Bit(s) Name Description Instruction Address Compare 1 User/Supervisor Mode 00 – IAC1 debug events not affected by MSR IAC1US 01 – Reserved 10 –...
Page 874 Nexus Development Interface (NDI) RM0046 Table 460. DBCR1 Bit Definitions (continued) Bit(s) Name Description Instruction Address Compare 3 Effective/Real Mode 00 – IAC3 debug events are based on effective address 18:19 IAC3ER 01 – Unimplemented in e200z0h (Book E real address compare), no match can occur 10 –...
Page 875: Table 461. Dbcr2 Bit Definitions
RM0046 Nexus Development Interface (NDI) Debug Control Register 2 (DBCR2) Debug Control Register 2 is used to configure Data Address Compare and Data Value Compare operation. The DBCR2 register is shown in Figure 509.. Figure 509. DBCR2 Register SPR - 310 DAC1US DAC1ER DAC2US...
Page 876 Nexus Development Interface (NDI) RM0046 Table 461. DBCR2 Bit Definitions (continued) Bit(s) Name Description Data Address Compare 1/2 Mode 00 – Exact address compare. DAC1 debug events can only occur if the address of the data access is equal to the value specified in DAC1. DAC2 debug events can only occur if the address of the data access is equal to the value specified in DAC2.
Page 877 RM0046 Nexus Development Interface (NDI) Table 461. DBCR2 Bit Definitions (continued) Bit(s) Name Description Data Value Compare 1 Mode When DBCR4 DVC1C 00 – DAC1 debug events not affected by data value compares. 01 – DAC1 debug events can only occur when all bytes specified in the DVC1BE field match the corresponding data byte values for active byte lanes of the memory access.
Page 878 Nexus Development Interface (NDI) RM0046 Table 461. DBCR2 Bit Definitions (continued) Bit(s) Name Description Data Value Compare 2 Mode When DBCR4 DVC2C 00 – DAC2 debug events not affected by data value compares. 01 – DAC2 debug events can only occur when all bytes specified in the DVC2BE field match the corresponding data byte values for active byte lanes of the memory access.
Page 879: Table 462. Dbcr4 Bit Definitions
RM0046 Nexus Development Interface (NDI) Debug Control Register 4 (DBCR4) Debug Control Register 4 is used to extend data value compare matching functionality. DBCR4 is shown in Figure 510. Figure 510. DBCR4 Register SPR - 563 Reset Reset 1. DBCR4 is reset by processor reset p_reset_b if DBCR0 =0, as well as unconditionally by m_por.
Page 880: Figure 511. Dbsr Register
Nexus Development Interface (NDI) RM0046 Debug Status Register (DBSR) The Debug Status Register (DBSR) contains status on debug events and the most recent processor reset. The Debug Status Register is set via hardware, and read and cleared via software. Bits in the Debug Status Register can be cleared using mtspr DBSR,RS. Clearing is done by writing to the Debug Status Register with a 1 in any bit position that is to be cleared and 0 in all other bit positions.
Page 881: Table 463. Dbsr Bit Definitions
RM0046 Nexus Development Interface (NDI) Table 463 provides bit definitions for the Debug Status Register. Table 463. DBSR Bit Definitions Bit(s) Name Description Imprecise Debug Event Set to ‘1’ if MSR =0, DBCR0 =1 and a debug event causes its respective Debug Status Register bit to be set to ‘1’.
Page 882: Debug External Resource Control Register (Dberc0)
Nexus Development Interface (NDI) RM0046 Table 463. DBSR Bit Definitions (continued) Bit(s) Name Description Data Address Compare 2 Write Debug Event DAC2W Set to ‘1’ if a write-type DAC2 debug event occurred while DBCR0 =0b01 or DAC2 DBCR0 =0b11 DAC2 Return Debug Event Set to ‘1’...
Page 883: Figure 512. Dberc0 Register
RM0046 Nexus Development Interface (NDI) resource(s) via DBERC0), a set bit in DBSR which is software-owned other than MRR or VLES will cause a debug interrupt to be generated. Debug status bits in DBSR are set by hardware-owned debug events only while External Debug Mode is enabled (DBCR0 =1).
Page 884: Table 464. Dberc0 Bit Definitions
Nexus Development Interface (NDI) RM0046 Table 463 provides bit definitions for the Debug External Resource Control Register. Note that DBERC0 controls are disabled when DBCR0 Table 464. DBERC0 Bit Definitions Bit(s) Name Description — Reserved Internal Debug Mode control 0 – Internal Debug mode may not be enabled by software. DBCR0 is owned exclusively by hardware.
Page 885 RM0046 Nexus Development Interface (NDI) Table 464. DBERC0 Bit Definitions (continued) Bit(s) Name Description Instruction Address Compare 2 Debug Event 0 – Event owned by hardware debug. No mtspr access by software to IAC2 control and status IAC2 fields. 1 – Event owned by software debug. IAC2 control and status fields are software readable/writeable.
Page 886: Table 465. Dberc0 Resource Control
Nexus Development Interface (NDI) RM0046 Table 464. DBERC0 Bit Definitions (continued) Bit(s) Name Description Critical Interrupt Taken Debug Event 0 – Event owned by hardware debug. No mtspr access by software to DBCR0 CIRPT CIRPT DBSR fields. CIRPT 1 – Event owned by software debug. DBCR0 and DBSR are software CIRPT...
Page 887 RM0046 Nexus Development Interface (NDI) Table 465. DBERC0 Resource Control (continued) Software Accessible via mtspr, affected by p_reset_b 1 1 — — — — — — 1 1 — — — — — — — — — — — — — — DBCR1 IAC12M IAC3, DBCR0...
Page 888: External Debug Support
Nexus Development Interface (NDI) RM0046 36.12 External Debug Support External debug support is supplied through the e200z0h OnCE controller serial interface which allows access to internal CPU registers and other system state while the CPU is halted in debug mode. All debug resources including DBCR0–4, DBSR, IAC1–4, DVC1–2, DAC1–2 are accessible through the serial OnCE interface in external debug mode.
Page 889: Figure 513. Once Tap Controller And Registers
RM0046 Nexus Development Interface (NDI) controller. By using public instructions, the external hardware debugger can freeze or halt the CPU, read and write internal state, and resume normal execution. The core does not contain IEEE 1149.1 standard boundary cells on its interface, as it is a building block for further integration.
Page 890: Figure 514. Ieee 1149.1-2001 Tap Controller State Machine
Nexus Development Interface (NDI) RM0046 Test-Logic- Reset Select - IR Run - Test / Select DR- Scan Idle Scan Capture - DR Capture - IR Shift - DR Shift - IR Exit1 - DR Exit1 - IR Pause - DR Pause - IR Exit2 - DR Exit2 - IR...
Page 891: Table 466. Jtag/Once Primary Interface Signals
RM0046 Nexus Development Interface (NDI) command (See Section , “e200z0h OnCE Command Register (OCMD)). The CPU will then temporarily exit the debug state (but not the debug session) to execute the instruction, and will then return to the debug state (again indicated via the OnCE Status Register (OSR)). The debug session remains in force until the final OnCE go+exit command is executed, at which time the CPU will return to the previous state it was in (unless a new debug request is pending).
Page 892: Once Interface Signals
Nexus Development Interface (NDI) RM0046 of the CPU. The CPU core may enter debug mode either through a software or hardware event. CPU Address, Attributes The CPU address and attribute information are used by a Nexus class 2-4 debug unit with information for real-time address trace information.
Page 893: E200Z0H Once Controller And Serial Interface
RM0046 Nexus Development Interface (NDI) has been entered, the jd_de_en output will be asserted for three j_tclk periods to signal an acknowledge. jd_de_en can be used to enable the open-drain pulldown of the system level DE_b pin. For systems which do not implement a system level bidirectional open drain debug event pin DE_b, the jd_de_en and jd_de_b signals may still be used to handshake debug entry.
Page 894: Figure 515. E200Z0H Once Controller And Serial Interface
Nexus Development Interface (NDI) RM0046 TCLK OnCE COMMAND REGISTER UPDATE OnCE DECODER STATUS AND CONTROL REGISTERS REG WRITE REG READ MODE SELECT CPU CONTROL/STATUS Figure 515. e200z0h OnCE Controller and Serial Interface e200z0h OnCE Status Register Status information regarding the state of the e200z0h CPU is latched into the OnCE Status register when the OnCE controller state machine enters the Capture-IR state.
Page 895: Table 467. Once Status Register Bit Definitions
RM0046 Nexus Development Interface (NDI) Table 467 provides bit definitions for the Once Status Register. Table 467. OnCE Status Register Bit Definitions Bit(s) Name Description m_clk Status Bit 0 – Inactive state MCLK 1 – Active state This status bit reflects the logic level on the jd_mclk_on input signal after capture by j_tclk. ERROR This bit is used to indicate that an error condition occurred during attempted execution of the last single-stepped instruction (GO+NoExit with CPUSCR or No Register Selected in OCMD), and that...
Page 896: Table 468. Once Command Register Bit Definitions
Nexus Development Interface (NDI) RM0046 and/or exit functionality to be performed, even though the command appears to have no data resource requirement associated with it. RS[0:6] Reset - 10’b1000000010 on assertion of j_trst_b or m_por, or while in the Test_Logic_Reset state Figure 517.
Page 897: Table 469. E200Z0H Once Register Addressing
RM0046 Nexus Development Interface (NDI) Table 468. OnCE Command Register Bit Definitions (continued) Bit(s) Name Description Exit Command Bit 0 – Remain in debug mode 1 – Leave debug mode If the EX bit is set, the processor will leave the debug mode and resume normal operation until another debug request is generated.
Page 898 Nexus Development Interface (NDI) RM0046 Table 469. e200z0h OnCE Register Addressing (continued) RS[0:6] Register Selected 010 0111 Data Value Compare 2 (DVC2) 010 1000 – 010 1011 Reserved 010 1100 Reserved (DBCNT) 010 1101 – 010 1111 Reserved 011 0000 Debug Status Register (DBSR) 011 0001 Debug Control Register 0 (DBCR0)
Page 899: Table 470. Once Control Register Bit Definitions
RM0046 Nexus Development Interface (NDI) Additionally, the DBCR0 bit is forced to ‘1’ internally while single-stepping to prevent Debug events from generating Debug interrupts. Also, during a debug session, the DBSR is frozen from updates due to debug events regardless of DBCR0 .
Page 900 Nexus Development Interface (NDI) RM0046 Table 470. OnCE Control Register Bit Definitions (continued) Bit(s) Name Description Instruction Side Debug TLB ‘VLE’ Attribute Bit (I_DVLE) I_DVLE This bit is used to provide the ‘VLE’ attribute bit to be used when the MMU is disabled during a debug session.
Page 901: Access To Debug Resources
RM0046 Nexus Development Interface (NDI) Table 470. OnCE Control Register Bit Definitions (continued) Bit(s) Name Description Wakeup Request Bit (WKUP) This control bit may be used to force the e200z0h p_wakeup output signal to be asserted. This control function may be used by debug firmware to request that the chip-level clock WKUP controller restore the m_clk input to normal operation regardless of whether the CPU is in a low power state to ensure that debug resources may be properly accessed by external...
Page 902: Table 471. Once Register Access Requirements
Nexus Development Interface (NDI) RM0046 Table 471 provides a list of access requirements for OnCE registers. Table 471. OnCE Register Access Requirements Access Requirements Requires Requires Requires Register Requires CPU to be CPU to be Requires m_clk active Name halted halted jd_en_once to DBCR0...
Page 903: Methods Of Entering Debug Mode
RM0046 Nexus Development Interface (NDI) 36.12.7 Methods of Entering Debug Mode The OnCE Status Register indicates that the CPU has entered the debug mode via the DEBUG status bit. The following sections describe how e200z0h Debug Mode is entered assuming the OnCE circuitry has been enabled. e200z0h OnCE operation is enabled by the assertion of the jd_en_once input (see Section ).
Page 904: Cpu Status And Control Scan Chain Register (Cpuscr)
Nexus Development Interface (NDI) RM0046 To signal the chip-level clock generator to re-enable m_clk, the p_wakeup output will be asserted whenever the debug block is asserting a debug request to the CPU due to OCR being set, or jd_de_b assertion, and will remain set from then until the debug session ends (jd_debug_b goes from asserted to negated).
Page 905: Figure 519. Cpu Scan Chain Register (Cpuscr)
RM0046 Nexus Development Interface (NDI) WBBR WBBR high Figure 519. CPU Scan Chain Register (CPUSCR) Instruction Register (IR) The Instruction Register (IR) provides a mechanism for controlling the debug session by serving as a means for forcing in selected instructions, and then causing them to be executed in a controlled manner by the debug control block.
Page 906: Figure 520. Control State Register (Ctl)
Nexus Development Interface (NDI) RM0046 Control State Register (CTL) The Control State Register (CTL) is a 32-bit register that stores the value of certain internal CPU state variables before the debug mode is entered. This register is affected by the operations performed during the debug session and should normally be restored by the external command controller when returning to normal mode.
Page 907 RM0046 Nexus Development Interface (NDI) of the original IR value, otherwise the original value of IR should be restored. (But see PCINV which overrides this field) 0000: No correction required. 0001: Subtract 0x04 from PC. 0010: Subtract 0x08 from PC. 0011: Subtract 0x0C from PC.
Page 908 Nexus Development Interface (NDI) RM0046 This control bit indicates an Instruction Address Compare 1 event status for the IR. 0: No Instruction Address Compare 1 event occurred on the fetch of this instruction. 1: An Instruction Address Compare 1 event occurred on the fetch of this instruction. IRStat3 —...
Page 909 RM0046 Nexus Development Interface (NDI) with a go+exit command. During the debug session, the CTL register should be written with the FFRA bit set as appropriate, and all other bits set to ‘0’, and the IR set to the value of the desired instruction to be executed.
Page 910: Table 472. Watchpoint Output Signal Assignments
Nexus Development Interface (NDI) RM0046 update a processor resource, this register is initialized with a data value to be written, and an e_ori instruction is executed which uses this value as a substitute data value. The Control State register FFRA bit forces the value of the WBBR to be substituted for the normal RS source value of the e_ori instruction, thus allowing updates to processor registers to be performed (refer to Section for more detail on the CTL...
Page 911: Basic Steps For Enabling, Using, And Exiting External Debug Mode
RM0046 Nexus Development Interface (NDI) Table 472. Watchpoint Output Signal Assignments (continued) Signal Name Type Description Instruction Address Compare 4 watchpoint jd_watchpt[3] IAC4 Asserted whenever an IAC4 compare occurs regardless of being enabled to set DBSR status Data Address Compare 1 watchpoint jd_watchpt[4] DAC1 Asserted whenever a DAC1 compare occurs regardless of being enabled...
Page 912: Functional Description
Nexus Development Interface (NDI) RM0046 To single-step the CPU: ● The debugger scans in either a new or a previously saved value of the CPUSCR (with appropriate modification of the PC and IR as described in Section , “Control State Register (CTL)), with a Go+Noexit OnCE Command value.
Page 913: Table 473. Jtagc Instruction Opcodes To Enable Nexus Clients
RM0046 Nexus Development Interface (NDI) Table 473. JTAGC Instruction opcodes to enable Nexus clients JTAGC Instruction Opcode Description ACCESS_AUX_TAP_NPC 10000 Enables access to the NPC TAP controller ACCESS_AUX_TAP_ONCE 10001 Enables access to the e200z0 TAP controller Table 474. Nexus client JTAG instructions Instruction Description Opcode...
Page 914: Table 475. Registers Under Protection
Registers Under Protection RM0046 Appendix A Registers Under Protection For SPC560P40/34, the Register Protection module is operable on the registers listed in Table 475. Table 475. Registers under protection Module Register Register size (bits) Register offset Protected bitfields Code Flash—Base address: 0xC3F8_8000 4 registers to protect Code Flash 0x0000...
Page 915 RM0046 Registers Under Protection Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields SIUL PCR14 0x005C bits[0:15] SIUL PCR15 0x005E bits[0:15] SIUL PCR16 0x0060 bits[0:15] SIUL PCR17 0x0062 bits[0:15] SIUL PCR18 0x0064 bits[0:15] SIUL PCR19 0x0066 bits[0:15]...
Page 916 Registers Under Protection RM0046 Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields SIUL PCR60 0x00B8 bits[0:15] SIUL PCR61 0x00BA bits[0:15] SIUL PCR62 0x00BC bits[0:15] SIUL PCR63 0x00BE bits[0:15] SIUL PCR64 0x00C0 bits[0:15] SIUL PCR65 0x00C2 bits[0:15]...
Page 917 RM0046 Registers Under Protection Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields SIUL IFMC11 0x102C bits[0:31] SIUL IFMC12 0x1030 bits[0:31] SIUL IFMC13 0x1034 bits[0:31] SIUL IFMC14 0x1038 bits[0:31] SIUL IFMC15 0x103C bits[0:31] SIUL IFMC16 0x1040 bits[0:31]...
Page 918 Registers Under Protection RM0046 Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields MC ME ME_RUN_PC2 0x0088 bits[0:31] MC ME ME_RUN_PC3 0x008C bits[0:31] MC ME ME_RUN_PC4 0x0090 bits[0:31] MC ME ME_RUN_PC5 0x0094 bits[0:31] MC ME ME_RUN_PC6 0x0098 bits[0:31]...
Page 919 RM0046 Registers Under Protection Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields IRC_OSC—Base address: 0xC3FE_0060 1 register to protect IRC_OSC RC_CTL 0x0000 bits[0:31] FM PLL 0—Base address: 0xC3FE_00A0 2 registers to protect FMPLL 0 0x0000 bits[0:31] FMPLL 0...
Page 920 Registers Under Protection RM0046 Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields ADC 0 CLR1 0x0004 32-bit ADC 0 CLR2 0x0008 32-bit ADC 0 CLR3 0x000C 32-bit ADC 0 CLR4 0x0010 32-bit ADC 0 TRC0 0x0034 32-bit...
Page 921 RM0046 Registers Under Protection Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields eTimer 0 CH5_CTRL3 0x00B2 16-bit eTimer 0 CH5_CCCTRL 0x00BC 16-bit FlexPWM—Base address: 0xFFE2_4000 41 registers to protect FlexPWM SUB0_CTRL2 0x0004 16-bit FlexPWM SUB0_CTRL 0x0006...
Page 922 Registers Under Protection RM0046 Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields FlexPWM SUB3_OCTRL 0x0108 16-bit FlexPWM SUB3_INTEN 0x010C 16-bit FlexPWM SUB3_DMAEN 0x010E 16-bit FlexPWM SUB3_TCTRL 0x0110 16-bit FlexPWM SUB3_DISMAP 0x0112 16-bit FlexPWM SUB3_DTCNT0 0x0114 16-bit...
Page 923 RM0046 Registers Under Protection Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields DSPI 1 DSPI_CTAR4 0x001C 32-bit DSPI 1 DSPI_CTAR5 0x0020 32-bit DSPI 1 DSPI_CTAR6 0x0024 32-bit DSPI 1 DSPI_CTAR7 0x0028 32-bit DSPI 1 DSPI_RSER 0x0030 32-bit...
Page 924 Registers Under Protection RM0046 Table 475. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields Safety port CANx_RX15MASK 0x0018 32-bit Safety port CANx_IMASK2 0x0024 32-bit Safety port CANx_IMASK 0x0028 32-bit 924/936 Doc ID 16912 Rev 5...
Page 925: Table 476. Revision History
RM0046 Document revision history Document revision history Table 476 summarizes revisions to this document. Table 476. Revision history Date Revision Changes 10-Dec-2009 Initial release Preface Organization: – Corrected cross-reference to Nexus chapter – Removed bullet “Appendix B, “Memory Map” Register figure conventions: Minor editorial correction Table ii, “Acronyms and Abbreviated Terms,”...
Page 926 Document revision history RM0046 Table 476. Revision history (continued) Date Revision Changes 12, “e200z0 and e200z0h Core Section 12.2, “Features: Removed bullet “Power saving modes: doze, nap, sleep, and wait” 13, “Peripheral Bridge (PBRIDGE): Unchanged from previous revision 14, “Crossbar Switch (XBAR): Unchanged from previous revision 15, “Error Correction Status Module (ECSM) Replaced occurrences of “AXBS_lite”...
Page 927 RM0046 Document revision history Table 476. Revision history (continued) Date Revision Changes 23, Analog-to-Digital Converter (ADC) ADC digital registers: Removed Channel Pending Registers (CEOCFR[x]) and Decode Signals Delay Register (DSDR) Section 23.3.3, ADC sampling and conversion timing: Corrected instances of bitfield name INPSAMPLE to INPSAMP Section 23.3.7, Interrupts: Removed content concerning register CEOCFR...
Page 928 Document revision history RM0046 Table 476. Revision history (continued) Date Revision Changes 33, “Boot Assist Module (BAM) Minor editorial and formatting changes Section 33.3, “Boot modes: Minor editorial changes Section 33.5.1, “Entering boot modes: Editorial changes Boot mode selection: Added Autobaud Scan boot mode Section 33.5.3, “Reset Configuration Half Word (RCHW): Removed the word “Source”...
Page 929 RM0046 Document revision history Table 476. Revision history (continued) Date Revision Changes “Preface” chapter, entirely rewrote “SPC560P40/34 block diagram”, made arrow going from peripheral bridge to crossbar switch bidirectional “Clock Description” chapter – In the “Functional description” section, replaced all occurences of XTALOUT with EXTAL.
Page 930 Document revision history RM0046 Table 476. Revision history (continued) Date Revision Changes “Deserial Serial Peripheral Interface (DSPI)” chapter In the “DSPI memory map” table, removed access and reset columns. In the “DSPI block diagram” figure, replace arrow labels from “1” to “3”. In the DSPIx_MCR.CONT_SCKE filed description, added a note.
Page 931 RM0046 Document revision history Table 476. Revision history (continued) Date Revision Changes “Nexus Development Interface (NDI)” chapter: Minor editorial and formatting changes Throught the chapter, removed all DOZE occurrences. Replaced several references to Power Architecture™ with references to Power Architecture In the “OnCE Register Access Requirements”...
Page 932 Document revision history RM0046 Table 476. Revision history (continued) Date Revision Changes “Fault Collection and Control Unit (FCCU)” chapter: Changed the chapter title in “Fault Collection and Control Unit (FCCU)” instead of "Fault Collection Unit (FCU)". In the “FCCU memory map” table, removed access and reset columns per new agreement.
Page 933: Figure 57. Peripheral Status Register 0 (Me_Ps0)
RM0046 Document revision history Table 476. Revision history (continued) Date Revision Changes Chapter 2: SPC560P40/34 memory map Table 3 (Memory map): Changed “Data Flash Array 0 Test Sector” size from 16K to 8K Chapter 3: Signal Description: In the Table 6 (Pin muxing):removed Port E[0] Chapter 4: Clock Description:...
Page 934 Document revision history RM0046 Table 476. Revision history (continued) Date Revision Changes Chapter 21: LIN Controller (LINFlex) Figure 237 (LIN status register (LINSR)): changed LINS access from read/write to write only Figure 242 (LIN output compare register (LINOCR)): changed note from LINTCSR[LTOM] = 1 to LINTCSR[LTOM] = 0 Updated Section , Identifier filter enable register...
Page 935 RM0046 Document revision history Table 476. Revision history (continued) Date Revision Changes Chapter 27: Functional Safety: Figure 433 (SWT Counter Output register (SWT_CO)): changed the access permission from read/write to read only Table 394 (SWT_TO field descriptions): updated fied description, was (SWT_CR.WENSWT_CR.=0) is (SWT_CR[WEN]=0).
Page 936 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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