Sony MVS-6530 Installation Manual page 19

S3802 (D-1): SCU DBG SW switch
Not used.
S4101 (B-1): SW switch
For the operation mode setting of SCU NIOS (IC5).
Factory setting: OFF (all)
LED on CPU-DP module
D1 (H-1): 3.3V
Power status indication.
Lit when +3.3V is supplied to the regulator on the CPU-
DP module normally.
D2 (G-2): 2.5V
Power status indication.
Lit when +2.5V is supplied normally.
D3 (H-1): 1.8V_DDR
Power status indication
Lit when +1.8V is supplied to DDR2 on the CPU-DP
module normally.
D4 (G-1): 1.2V
Power status indication
Lit when +1.2 V is supplied normally.
D5 (H-1): 1.1V
Power status indication
Lit when +1.1 V is supplied normally.
D6 (C-6): CD
Lit when the connector on the CPU-DP module is con-
nected to the base board correctly.
D7 (A-4): RUN
Lit when the boot process of the CPU-DP module is per-
formed normally.
D8 (A-4), D9 (H-5), D10 (H-5), D11 (H-6):
STATUS LED 1 to 4
Internal status indication of the CPU-DP module.
Controlled by software.
D12 (A-4): GbE1
Lit when Ethernet 1 on the CPU-DP module is linked.
Compatible with the connection of in-flight communication
on the CA-85 board.
MVS-6520
D13 (A-4): GbE2
Lit when Ethernet 2 on the CPU-DP module is linked.
Not used in the CA-85 board.
D14 (A-4): SGMII1
Lit when SGMII 1 on the CPU-DP module is linked.
Compatible with the Ethernet connection of UTIL (SW)
LAN on the CA-85 board.
D15 (A-4): SGMII2
Lit when SGMII 2 on the CPU-DP module is linked.
Compatible with the connection with SCU on the CA-85
board.
D16 (F-1): 3.3V_LV
Power status indication.
Lit when +3.3V is supplied normally.
D17 (E-1): 1.8V_PHY
Power status indication.
Lit when +1.8V is supplied to PHY on the CPU-DP mod-
ule normally.
Switch on CPU-DP module
SW2 (A-6): CPU-DP MODE
Sets the startup mode of the CPU-DP module.
Factory setting: OFF (all)
1-15 (E)