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Sony 486DX User Manual

Industrial grade 486dx/dx2/dx4 cpu card.
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AR-B1474
INDUSTRIAL GRADE
486DX/DX2/DX4 CPU CARD
User' s Guide
Edition: 3.1
Book Number: AR-B1474-99.B01

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   Summary of Contents for Sony 486DX

  • Page 1

    AR-B1474 INDUSTRIAL GRADE 486DX/DX2/DX4 CPU CARD User’ s Guide Edition: 3.1 Book Number: AR-B1474-99.B01...

  • Page 3: Table Of Contents

    Table of Contents PREFACE... 0-3 COPYRIGHT NOTICE AND DISCLAIMER ...0-3 WELCOME TO THE AR-B1474 SERIAL CPU BOARD...0-3 BEFORE YOU USE THIS GUIDE...0-3 RETURNING YOUR BOARD FOR SERVICE...0-3 TECHNICAL SUPPORT AND USER COMMENTS ...0-3 ORGANIZATION...0-4 STATIC ELECTRICITY PRECAUTIONS...0-4 OVERVIEW... 1-1 INTRODUCTION ...1-1 PACKING LIST ...1-2 FEATURES ...1-2 SYSTEM CONTROLLER ...

  • Page 4

    AR-B1474 User¡ ¦ s Guide ROM DISK INSTALLATION ...5-6 5.4.1 UV EPROM (27Cxxx)...5-6 5.4.2 Large Page 5V FLASH Disk...5-8 5.4.3 Small Page 5V FLASH ROM Disk ...5-9 5.4.4 RAM Disk...5-11 5.4.5 Combination of ROM and RAM Disk ...5-12 INSTALLATION D.O.C..5-12 5.5.1 Hardware Setting...5-12 5.5.2...

  • Page 5: Preface

    0.1 COPYRIGHT NOTICE AND DISCLAIMER September 1995 Acrosser Technology makes no representations or warranties with respect to the contents hereof and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. Furthermore, Acrosser Technology reserves the right to revise this publication and to make changes from time to time in the contents hereof without obligation of Acrosser Technology to notify any person of such revisions or changes.

  • Page 6: Organization

    AR-B1474 User¡ ¦ s Guide 0.6 ORGANIZATION This information for users covers the following topics (see the Table of Contents for a detailed listing): Chapter 1, “Overview”, provides an overview of the system features and packing list. Chapter 2, “System Controller” describes the major structure. Chapter 3, “Setting Up the System”, describes how to adjust the jumper, and the connectors setting.

  • Page 7: Overview

    1. OVERVIEW This chapter provides an overview of your system features and capabilities. The following topics are covered: Introduction Packing List Features 1.1 INTRODUCTION The AR-B1474 is a half size industrial grade CPU card that has been designed to withstand continuous operation in harsh environments.

  • Page 8: Packing List

    The system provides a number of special features that enhance its reliability, ensure its availability, and improve its expansion capabilities, as well as its hardware structure. All-in-one designed 486DX/DX2/DX4 CPU card Support 3.3V/5V CPU with voltage regulator Support ISA bus and PC/104 bus...

  • Page 9: System Controller

    2. SYSTEM CONTROLLER This chapter describes the major structure of the AR-B1474 serial CPU board. The following topics are covered: DMA Controller Keyboard Controller Interrupt Controller Serial Port Parallel Port 2.1 DMA CONTROLLER The equivalent of two 8237A DMA controllers are implemented in the AR-B1474 card. Each controller is a four- channel DMA device that will generate the memory addresses and control signals necessary to transfer information directly between a peripheral device and memory.

  • Page 10: Interrupt Controller

    AR-B1474 User¡ ¦ s Guide 2.3 INTERRUPT CONTROLLER The equivalent of two 8259 Programmable Interrupt Controllers (PIC) are included on the AR-B1474 card. They accept requests from peripherals, resolve priorities on pending interrupts in service, issue interrupt requests to the CPU, and provide vectors which are used as acceptance indices by the CPU to determine which interrupt service routine to execute.

  • Page 11: I/o Port Address Map

    2.3.1 I/O Port Address Map Hex Range 000-01F 020-021 022-023 040-04F 050-05F 060-06F 070-071 080-09F 0A0-0A1 0C0-0DF 0F8-0FF 170-178 1F0-1F8 208-20A 210-213 214-215 218-21A 278-27F 290-293 294-295 2E8-2EF 2F8-2FF 310-313 314-315 378-37F 380-38F 390-393 394-395 3A0-3AF 3B0-3BF 3C0-3CF 3D0-3DF 3E8-3EF 3F0-3F7 3F8-3FF Table 2-2 I/O Port Address Map...

  • Page 12: Real-time Clock And Non-volatile Ram

    AR-B1474 User¡ ¦ s Guide 2.3.2 Real-Time Clock and Non-Volatile RAM The AR-B1474 contains a real-time clock compartment that maintains the date and time in addition to storing configuration information about the computer system. It contains 14 bytes of clock and control registers and 114 bytes of general purpose RAM.

  • Page 13: Isa Bus Pin Assignment

    2.3.4 ISA Bus Pin Assignment I/O Pin Table 2-4 ISA Bus Pin Assignment I/O Pin Table 2-5 ISA Bus Pin Assignment Signal Name Input/Output I/O Pin Signal Name Input/Output -IOCHCK Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output IOCHRDY Input Output SA19...

  • Page 14: Isa Bus Signal Description

    AR-B1474 User¡ ¦ s Guide 2.3.5 ISA Bus Signal Description Name BUSCLK [Output] RSTDRV [Output] SA0 - SA19 [Input / Output] LA17 - LA23 [Input/Output] SD0 - SD15 [Input/Output] BALE [Output] -IOCHCK [Input] IOCHRDY [Input, Open IRQ 3-7, 9-12, 14, 15 -IOR [Input/Output] -IOW [Input/Output] The I/O write signal is an active low signal which instructs...

  • Page 15: Serial Port

    Name -MASTER [Input] -MEMCS16 [Input, collector] -IOCS16 [Input, collector] OSC [Output] [Input, collector] Table 2-6 ISA Bus Signal Description 2.4 SERIAL PORT The ACEs (Asynchronous Communication Elements ACE1 to ACE2) are used to convert parallel data to a serial format on the transmit side and convert serial data to parallel on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits.

  • Page 16

    AR-B1474 User¡ ¦ s Guide (3) Interrupt Enable Register (IER) Bit 0: Enable Received Data Available Interrupt (ERBFI) Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI) Bit 2: Enable Receiver Line Status Interrupt (ELSI) Bit 3: Enable MODEM Status Interrupt (EDSSI) Bit 4: Must be 0 Bit 5: Must be 0 Bit 6: Must be 0...

  • Page 17: Parallel Port

    (8) MODEM Status Register (MSR) Bit 0: Delta Clear to Send (DCTS) Bit 1: Delta Data Set Ready (DDSR) Bit 2: Training Edge Ring Indicator (TERI) Bit 3: Delta Receive Line Signal Detect (DSLSD) Bit 4: Clear to Send (CTS) Bit 5: Data Set Ready (DSR) Bit 6: Ring Indicator (RI) Bit 7: Received Line Signal Detect (RSLD)

  • Page 18

    AR-B1474 User¡ ¦ s Guide (3) Data Swapper The system microprocessor can read the contents of the printer’ s Data Latch through the Data Swapper by reading the Data Swapper address. (4) Printer Status Buffer The system microprocessor can read the printer status by reading the address of the Printer Status Buffer. The bit definitions are described as follows: NOTE: X presents not used.

  • Page 19: Setting Up The System

    3. SETTING UP THE SYSTEM This section describes pin assignments for system’ s external connectors and the jumpers setting. Overview System Setting 3.1 OVERVIEW The AR-B1474 is a half size industrial grade CPU card that has been designed to withstand continuous operation in harsh environments.

  • Page 20: System Setting

    AR-B1474 User¡ ¦ s Guide 3.2 SYSTEM SETTING Jumper pins allow you to set specific system parameters. Set them by changing the pin location of jumper blocks. (A jumper block is a small plastic-encased conductor that slips over the pins.) To change a jumper setting, remove the jumper from its current location with your fingers or small needle-nosed pliers.

  • Page 21: Hard Disk (ide) Connector (cn1)

    3.2.2 Hard Disk (IDE) Connector (CN1) A 40-pin header type connector (CN1) is provided to interface with up to two embedded hard disk drives (IDE AT bus). This interface, through a 40-pin cable, allows the user to connect up to two drives in a “daisy chain” fashion. To enable or disable the hard disk controller, please use BIOS Setup program to select.

  • Page 22: Fdd Port Connector (cn2)

    AR-B1474 User¡ ¦ s Guide 3.2.4 FDD Port Connector (CN2) The AR-B1474 provides a 34-pin header type connector for supporting up to two floppy disk drives. To enable or disable the floppy disk controller, please use BIOS Setup program to select. 1-33(odd) Table 3-2 FDD Pin Assignment 3.2.5 Parallel Port Connector (CN3)

  • Page 23: Pc/104 Connector

    3.2.6 PC/104 Connector (1) 64-Pin PC/104 Connector Bus A & B (CN6) Figure 3-9 CN6: 64-Pin PC/104 Connector Bus A & B (2) 40-Pin PC/104 Connector Bus C & D (CN4) Figure 3-10 CN4: 40-Pin PC/104 Connector Bus C & D 64-Pin PC/104 Connector -IOCHCK --- --- GND...

  • Page 24

    AR-B1474 User¡ ¦ s Guide (3) PC/104 ISA Bus Signal Description Name BUSCLK [Output] RSTDRV [Output] SA0 - SA19 [Input / Output] LA17 - LA23 [Input/Output] SD0 - SD15 [Input/Output] BALE [Output] -IOCHCK [Input] IOCHRDY [Input, Open collector] IRQ 3-7, 9-12, 14, 15 -IOR [Input/Output] -IOW [Input/Output]...

  • Page 25: Cpu Setting

    Table 3-4 PC/104 ISA Bus Pin Assignment 3.2.7 CPU Setting The AR-B1474 accepts many types of microprocessor, such as INTEL/AMD/CYRIX 486DX/DX2/DX4. All of these CPUs include an integer processing unit, floating-point processing unit, memory-management unit, and cache. They can give a two to ten-fold performance improvement in speed over the 386 processor, depending on the clock speeds used and specific application.

  • Page 26

    AR-B1474 User¡ ¦ s Guide (4) CPU Clock Select (JP6 & JP9) For different type of CPUs, the clock generator and clock divisor need to be set by JP6 and JP9. The clock base is selected by JP6, JP9 is used to select single or half clock system. We recommend that you refer the following table for setting the CPU clock.

  • Page 27: Memory Setting

    3.2.8 Memory Setting (1) Cache RAM Size Select (JP8) The AR-B1474 can be configured to provide a write-back or write-through cache scheme and support 128KB to 512KB cache systems. A write-back cache system may provide better performance than a write-through cache system.

  • Page 28: Led Header (j1, J2 & J4)

    AR-B1474 User¡ ¦ s Guide 3.2.9 LED Header (J1, J2 & J4) (1) External Power LED & Keyboard Lock Header (J4) (2) HDD LED Header (J1) (3) Watchdog LED Header (J2) 3.2.10 Keyboard Connector (1) 6-Pin Mini DIN Keyboard Connector (CN5) CN5 is a 6-pin Mini-DIN connector.

  • Page 29: External Speaker Header (j3)

    3.2.11 External Speaker Header (J3) Besides the on board buzzer, you can use an external speaker by connecting J3 header directly. 3.2.12 Reset Header (J7) J7 is used to connect to an external reset switch. Shorting these two pins will reset the system. 3.2.13 Battery Setting (1) Battery Charger Select (JP4) (2) External Battery Connector (J6)

  • Page 31: Installation

    4. INSTALLATION This chapter describes the procedure of the installation. The following topics are covered: Overview Utility Diskette Write Protect Function Watchdog Timer 4.1 OVERVIEW This chapter provides information for you to set up a working system based on the AR-B1474 CPU card. Please read the details of the CPU card’...

  • Page 32: Utility Diskette

    AR-B1474 User¡ ¦ s Guide 4.2 UTILITY DISKETTE To support the AR-B1474 solid state disk’ s operations, the following programs or files has been provided on the accompanying utility diskette: (1) PGM1474.EXE PGM1474.EXE PGM1474.EXE is used to program the 12V FLASH EPROM after the ROM pattern files are generated by RFG.EXE The PGM1474.EXE can also program the correctness of the ROM pattern files onto 5V FLASH EPROM (start from MEM1) or SRAM for testing the ROM pattern files.

  • Page 33

    (2) WD1474.EXE WD1474.EXE This program demonstrates how to enable and trigger the watchdog timer. It allows you to test the <TIMES-OUT & RESET> function when the watchdog timer is enabled. (3) WP1474.EXE WP1474.EXE This program demonstrates how to enable and disable software write protected function. It also shows the current protect mode of write or read only memory.

  • Page 34

    AR-B1474 User¡ ¦ s Guide stated in your PGF). The ROM pattern files will have the same file names, but will have different extension names. For example: TEST.R01, TEST.R02, TEST.R03 … etc. Display Error in PGF File This option displays errors that were detected in your PGF. Help to PGF File This option gives information on how to write a PGF file and how to generate ROM pattern files.

  • Page 35: Write Protect Function

    4.3 WRITE PROTECT FUNCTION The AR-B1474 provides hardware and software write protect functions for small page 5V FLASH disk and only software write protected function for SRAM disk. This is to prevent your data on 5V FLASH or SRAM disk from accidental deletion or overwrite.

  • Page 36: Watchdog Timer

    AR-B1474 User¡ ¦ s Guide 4.4 WATCHDOG TIMER This section describes how to use the Watchdog Timer, disabled, enabled, and trigger. The AR-B1474 is equipped with a programmable time-out period watchdog timer. This watchdog timer can be enabled by your program. Once you have enabled the watchdog timer, the program should trigger it every time before it times out.

  • Page 37: Watchdog Timer Enabled

    If you want to generate IRQ15 signal to warn your program when watchdog times out, the following table listed the relation of timer factors between time-out period. Table 4-2 Time-Out Setting NOTE: 1. If you program the watchdog to generate IRQ15 signal when it times out, you should initial IRQ15 interrupt vector and enable the second interrupt controller (8259 PIC) in order to enable CPU to process this interrupt.

  • Page 39: Solid State Disk

    5. SOLID STATE DISK The section describes the various type SSDs’ installation steps as follows. This chapter describes the procedure of the installation. The following topics are covered: Overview Switch Setting Jumper Setting ROM Disk Installation 5.1 OVERVIEW The AR-B1474 provides three 32-pin JEDEC DIP sockets which may be populated with up to 3MB of EPROM or 1.5MB of FLASH or 1.5MB of SRAM disk.

  • Page 40: Overview

    AR-B1474 User¡ ¦ s Guide 5.2.1 Overview There is 1 DIP Switch located on the AR-B1474. It performs the following functions: SW1-1 & SW1-2 Set the base I/O port address SW1-3 & SW1-4 Set the starting memory address SW1-5 & SW1-6 Set the drive number of solid state SW1-7 &...

  • Page 41: Ssd Drive Number (sw1-5 & Sw1-6)

    5.2.4 SSD Drive Number (SW1-5 & SW1-6) The AR-B1474 SSD can simulate one or two disk drives. You can assign the drive letter of the AR-B1474 by configuring SW1-5 & SW1-6. You can make the computer to boot from SSD by copying DOS into the SSD. If your SSD does not have DOS, the computer will boot from your hard disk or floppy disk.

  • Page 42: Rom Type Select (sw1-7 & Sw1-8)

    AR-B1474 User¡ ¦ s Guide (2) Disk Drive Name Arrangement If any logical hard disk drives exist in your system, there will also be a different disk number depending on which version DOS you are using. The solid state disk drive number with there respective DOS drive designation are listed in table as follows. The solid state disk drive number is changeable as the DOS version.

  • Page 43: Jumper Setting

    5.3 JUMPER SETTING Before installing the memory into memory sockets MEM1 through MEM3, you have to configure the memory type which will be used (ROM/RAM) on the AR-B1474. Each socket is equipped with a jumper to select the memory type. You can configure the AR-B1474 as a (FLASH) EPROM disk (ROM only), a SRAM disk (SRAM only) or a combination of (FLASH) EPROM and SRAM disk.

  • Page 44: Ssd Memory Type Setting (m1 ~ M3 & Jp5)

    AR-B1474 User¡ ¦ s Guide 5.3.2 SSD Memory Type Setting (M1 ~ M3 & JP5) M1, M2 & M3 M1, M2 & M3 M1, M2 & M3 M1, M2 & M3 5.4 ROM DISK INSTALLATION The section describes the various type SSDs’ installation steps as follows. The jumper and switch adjust as SSD’ s different type to set.

  • Page 45

    (2) Software Programming Use the UV EPROM, please refer to the follow steps: Step 1: Turn on the power and boot DOS from hard disk drive or floppy disk drive. Step 2: Making a Program Group File (*.PGF file) Step 3: Using the RFG.EXE to generate ROM pattern files, and counting the ROM numbers as the pattern files.

  • Page 46: Large Page 5v Flash Disk

    AR-B1474 User¡ ¦ s Guide 5.4.2 Large Page 5V FLASH Disk If you are using large page 5V FLASH as ROM disk, it is the same procedure as step 1 to step 4 of using the UV EPROM. (2) Switch and Jumper Setting Step 1: Use jumper block to set the memory type as ROM (FLASH).

  • Page 47: Small Page 5v Flash Rom Disk

    Step 4: Turn on your system, and Program FLASH EPROMs. NOTE: The FLASH EPROM program is built-in the AR-B1474 board. The FLASH EPROMs can be programmed on the AR-B1474. Before programming the FLASH EPROMs, please insert at least the same number of FLASH EPROMs, please insert at least the same number of FLASH EPROMs, please insert at least the same number of FLASH chips as the ROM pattern files generated.

  • Page 48

    AR-B1474 User¡ ¦ s Guide M1, M2 & M3 M1, M2 & M3 Figure 5-10 5V FLASH (29CXXX & 28EEXXX) Jumper Setting (2) Using Tool Program If small page 5V FLASH EPROMs are used, you can use the same method as step 1 to step 4 of using the UV EPROM: Step 1: Making a Program Group File (*.PGF file) Step 2: Generating ROM pattern files...

  • Page 49: Ram Disk

    CAUTION: It is not recommended that the user formatted the disk and copy files to the FLASH disk very often. Since the FLASH EPROM’ s write cycle life time is about 10,000 or 100,000 times, writing data to the FLASH too often will reduce the life time of the FLASH EPROM chips, especially the FLASH EPROM chip in the MEM1 socket.

  • Page 50: Combination Of Rom And Ram Disk

    AR-B1474 User¡ ¦ s Guide 5.4.5 Combination of ROM and RAM Disk The AR-B1474 can be configured as a combination of one ROM disk and one RAM disk. Each disk occupies a drive unit. Step 1: Use jumper block to select the proper ROM/RAM configuration you are going to use. Step 2: Insert the first programmed EPROM into the socket mem1, the second into the socket MEM2, etc.

  • Page 51: Software Setting

    (3) D.O.C. Setting (SW1-8) Note: There is 1 DIP switch located on the AR-B1474. It performs the followings: SW1-1 & SW1-2 Set the base I/O port address SW1-3 & SW1-4 Set the starting memory address SW1-5, SW1-6 & SW1-7 SW1-8 5.5.2 Software Setting We will attach the BU1474.EXE and 1474DOC.INI these two files, BU1474.EXE is the utility program, and the 1474DOC.INI is for D.O.C.

  • Page 53: Bios Console

    6. BIOS CONSOLE This chapter describes the AR-B1474 BIOS menu displays and explains how to perform common tasks needed to get up and running, and presents detailed explanations of the elements found in each of the BIOS menus. The following topics are covered: BIOS Setup Overview Standard CMOS Setup Advanced CMOS Setup...

  • Page 54: Standard Cmos Setup

    AR-B1474 User¡ ¦ s Guide 6.2 STANDARD CMOS SETUP The <Standard CMOS Setup> option allows you to record some basic system hardware configuration and set the system clock and error handling. If the CPU board is already installed in a working system, you will not need to select this option anymore.

  • Page 55: Advanced Cmos Setup

    6.3 ADVANCED CMOS SETUP The <Advanced CMOS SETUP> option consists of configuration entries that allow you to improve your system performance, or let you set up some system features according to your preference. System BootUp Sequence The option determines where the system looks first for an operating system. System BootUp Num-Lock This item is used to activate the Num Lock function upon system boot.

  • Page 56

    AR-B1474 User¡ ¦ s Guide Internal Cache Memory This option specifies the caching algorithm used for L1 internal cache memory. The settings are: Setting Disabled WriteBack WriteThru Table 6-1 Internal Cache Setting External Cache Memory This option specifies the caching algorithm used for L2 secondary (external) cache memory. The settings are: Setting Disabled WriteBack...

  • Page 57: Advanced Chipset Setup

    OnBoard FDC This option enables the floppy drive controller on the AR-B1474. OnBoard IDE This option Enabled/Disabled the use of the IDE controller on the AR-B1474. Parallel Port Address This option is used to select the port address and the IRQ of the on-board parallel port. The addresses are 378H, 278H, 3BCH, and Disable.

  • Page 58: Power Management

    AR-B1474 User¡ ¦ s Guide Parity Check This option enables or disables parity error checking for all system RAM. This option must be Disabled if the used DRAM SIMMs are 32-bit but not 36-bit devices. Slow Refresh This options sets the DRAM refresh cycle time. The settings are 15us, 30us, 60us, and 120us. Hidden Refresh Hidden refresh separates refreshing of AT-bus memory and local DRAM.

  • Page 59: Auto-detect Hard Disks

    6.6 AUTO-DETECT HARD DISKS This option detects the parameters of an IDE hard disk drive, and automatically enters them into the Standard CMOS Setup screen. 6.7 PASSWORD SETTING This BIOS Setup has an optional password feature. The system can be configured so that all users must enter a password every time the system boots or when BIOS Setup is executed.

  • Page 60: Bios Exit

    AR-B1474 User¡ ¦ s Guide 6.9 BIOS EXIT This section is used to exit the BIOS main menu in two types situation. After making your changes, you can either save them or exit the BIOS menu and without saving the new values. 6.9.1 Save Settings and Exit This item set in the <Standard CMOS Setup>, <Advanced CMOS Setup>, <Advanced Chipset Setup>...

  • Page 61: Specifications

    7. SPECIFICATIONS CPU: 25-100 MHz INTEL/AMD/CYRIX 80486DX/DX2/DX4 Bus Interface: ISA (PC-AT) Bus and PC/104 Bus Chipset: ALI M1429 and M1431 RAM Memory: 1MB to 32MB using 32-bit or 36-bit 72-pin SIMMs with access time of 70ns or less Shadow RAM: Up to 256KB in 32 KB blocks supports system and video BIOS Extended Memory Fully supports the LIM EMS 4.0 and 3.2 specifications...

  • Page 63: Placement & Dimensions

    8. PLACEMENT & DIMENSIONS 8.1 PLACEMENT JP14 SIMM1 JP15 LED1 JP10 JP12 BUS1 AR-B1474 User¡ ¦ s Guide LED2 JP11 JP13 BUS2...

  • Page 64: Dimensions

    AR-B1474 User¡ ¦ s Guide 8.2 DIMENSIONS 3290 3190 7290 2900 6300 5500 3150 1700 1900 Unit: mil (1 inch = 25.4 mm = 1000 mil) 3000 3200...

  • Page 65: Memory Banks & Programming Rs-485

    9. MEMORY BANKS & PROGRAMMING RS-485 9.1 USING MEMORY BANK This section provides the information about how to access the memory on the AR-B1474 without using the AR- B1474 SSD BIOS. The AR-B1474 hardware divides every 8K bytes of memory into a memory bank. To access the data in the memory, you have to assign the chip number and the bank number.

  • Page 66: Programming Rs-485

    AR-B1474 User¡ ¦ s Guide Example 1: Select the 10th bank of the MEM1 on the AR-B1474. The AR-B1474 is using 27C020 (256K*8), and the base port is &H210. 100 base_port=&H210 110 OUT base_port+0,&H59 Example 2: Select the 40th bank of MEM3 on the AR-B1474. The AR-B1474 is using 27C040 (512K*8), and the base port is &H390.

  • Page 67

    (3) Send out one block data (Transmit – the data more than two characters) Step 1: Enable TXC signal, and the bit 0 of the address of offset+4 just sets “1”. Step 2: Send out the data. (Write all data to the offset+0 of the current COM port address) Step 3: Wait for the buffer’...

  • Page 69: Ssd Types Supported & Index

    10. SSD TYPES SUPPORTED & INDEX 10.1 SSD TYPES SUPPORTED The following list contains SRAMs supported by the AR-B1474: HITACHI SONY HITACHI SONY The following list contains large page 5V FLASHs supported by the AR-B1474: The following list contains small page 5V FLASHs supported by the AR-B1474:...

  • Page 70

    AR-B1474 User¡ ¦ s Guide SGS-THOMSON TOSHIBA ATMEL FUJITSU HITACHI INTEL MITSUBISHI SGS-THOMSON TOSHIBA ATMEL The following list contains 12V FLASHs supported by the AR-B1474: INTEL SGS-THOMSON INTEL SGS-THOMSON MXIC INTEL SGS-THOMSON MXIC 10-2 M27C2001 (256Kx8, 2M bits) TMS27C020 (256Kx8, 2M bits) TCS712000 (256Kx8, 2M bits) Am27C040...

  • Page 71: Index

    10.2 INDEX Name SIMM1 LED1 LED2 JP11 JP13 JP15 M1,M2 &M3 Memory type setting Function Hard disk (IDE) connector FDD port connector Parallel port connector 40-pin PC/104 connector bus C & D 6-pin mini DIN keyboard connector 64-pin PC/104 connector bus A & B HDD LED header Watchdog LED header External speaker header...

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Ar-b1474, Dx4

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