Texas Instruments TRF7970A Instruction Manual page 39

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6.10.5.1 Serial Interface Mode With Slave Select (SS)
The serial interface is in reset while the Slave Select signal is high. Serial data in (MOSI) changes on the
rising edge, and is validated in the reader on the falling edge, as shown in
terminated when the Slave Select signal goes high.
All words must be 8 bits long with the MSB transmitted first.
MOSI Transitions on Data Clock
t STE,LEAD
MOSI Valid on Data Clock Falling Edge
Slave
Select
1/f UCxCLK
DATA
CLK
t LO/HI t LO/HI
MOSI b7
MISO DON'T CARE
The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data
changes on the rising edge, and is validated in the reader on the falling edge, as shown in
During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is
validated at the eighth falling edge of SCLK, valid data can be read on the MISO pin at the falling edge of
SCLK. It takes eight clock edges to read out the full byte (MSB first). See
specifications related to
The continuous read operation is shown in
WRITE
ADDRESS BYTE
DATA
CLK
MOSI
B7 B6 B5 B4
MISO
DON'T CARE
SLAVE
SELECT
Figure 6-20. Continuous Read Operation Using SPI With Slave Select
Copyright © 2011–2014, Texas Instruments Incorporated
WRITE
Rising Edge
t SU,SI t HD,SI
b6...b1 b0
Figure 6-19. SPI With Slave Select Timing Diagram
Figure 6-19.
Figure
READ DATA
BYTE 1
No Data Transitions (All High or Low)
B3 B2 B1 B0
B7 B6 B5 B4
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SLOS743K – AUGUST 2011 – REVISED APRIL 2014
READ
Data Transition is on Data Clock
Rising Edge
MISO Valid on Data Clock Falling Edge
NO DATA TRANSITIONS
(ALL HIGH/LOW)
t SU,SO
t HD,SO
b7
6-20.
B3 B2 B1 B0
TRF7970A
TRF7970A
Figure 6-19. Communication is
t STE,LAG
t VALID,SO
b6...b1 b0
Figure
Section 5.3 for electrical
READ DATA
BYTE n
No Data Transitions (All High or Low)
B7 B6 B5 B4 B3 B2 B1 B0
Detailed Description
t STE,DIS
6-19.
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