Texas Instruments TRF7970A Instruction Manual page 23

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If register setting changes are needed for fine tuning the system, they must be done after
setting the ISO Control register (0x01).
The framing section also supports the bit-collision detection as specified in ISO14443A. When a bit
collision is detected, an interrupt request is sent and a flag is set in the IRQ and Status register (0x0C).
The position of the bit collision is written in two registers: Collision Position register (0x0E) and partly in
Collision Position and Interrupt Mask register (0x0D) (bits B6 and B7).
The collision position is presented as sequential bit number, where the count starts immediately after the
start bit. This means a collision in the first bit of a UID would give the value 00 0001 0000 in these
registers when their contents are combined after being read. (the count starts with 0 and the first 16 bits
are the command code and the Number of Valid Bits (NVB) byte).
The receive section also contains two timers. The RX wait time timer is controlled by the value in the RX
Wait Time register (0x08). This timer defines the time interval after the end of the transmit operation in
which the receive decoders are not active (held in reset state). This prevents false detections resulting
from transients following the transmit operation. The value of the RX Wait Time register (0x08) defines the
time in increments of 9.44 µs. This register is preset at every write to ISO Control register (0x01)
according to the minimum tag response time defined by each standard.
The RX no response timer is controlled by the RX No Response Wait Time register (0x07). This timer
measures the time from the start of slot in the anticollision sequence until the start of tag response. If there
is no tag response in the defined time, an interrupt request is sent and a flag is set in the IRQ Status
register (0x0C). This enables the external controller to be relieved of the task of detecting empty slots. The
wait time is stored in the register in increments of 37.76 µs. This register is also preset, automatically for
every new protocol selection.
The digitized output of the analog receiver is at the input of the digital portion of the receiver. This input
signal is the subcarrier coded signal, which is a digital representation of modulation signal on the RF
envelope.
The digital part of the receiver consists of two sections which partly overlap. The first section contains the
bit decoders for the various protocols. The bit decoders convert the subcarrier coded signal to a bit stream
and also the data clock. Thus the subcarrier coded signal is transformed to serial data and the data clock
is extracted. The decoder logic is designed for maximum error tolerance. This enables the decoders to
successfully decode even partly corrupted (due to noise or interference) subcarrier signals.
The second section contains the framing logic for the protocols supported by the bit decoder section. In
the framing section, the serial bit stream data is formatted in bytes. In this process, special signals like the
SOF (start of frame), EOF (end of frame), start of communication, end of communication are automatically
removed. The parity bits and CRC bytes are checked and also removed. The end result is "clean or raw"
data which is sent to the
127-byte FIFO register where it can be read out by the external microcontroller system.
The start of the receive operation (successfully received SOF) sets the flags in the IRQ and Status
register. The end of the receive operation is signaled to the external system (MCU) by sending an interrupt
request (pin 13 IRQ). If the receive data packet is longer than 96 bytes, an interrupt is sent to the MCU
when the received data occupies 75% of the FIFO capacity to signal that the data should be removed
from the FIFO.
Any error in data format, parity or CRC is detected and the external system is made aware of the error by
an interrupt request pulse. The nature of the interrupt request pulse is available in the IRQ and Status
register (address 0x0C). The bit coding description of this register is shown in
information in IRQ and Status register differs if the chip is configured as RFID reader or as NFC device
(including tag emulation). The case of NFC operation is presented in
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SLOS743K – AUGUST 2011 – REVISED APRIL 2014
Section 6.14.3.3.1. The
Section 6.12.
Detailed Description
TRF7970A
23