Supermicro X11DDW-L User Manual page 87

Chapter 4: BIOS
SDDC Plus One (Available when this feature is supported by the CPU & the item:
Intel Run Sure is set to Disable)
SDDC (Single Device Data Correction) checks and corrects single-bit or multiple-bit (4-bit
max.) memory faults that affect an entire single x4 DRAM device. SDDC Plus One is the
enhanced feature to SDDC. SDDC+1 will spare the faulty DRAM device out after an SDDC
event has occurred. After the event, the SDDC+1 ECC mode is activated to protect against
any additional memory failure caused by a 'single-bit' error in the same memory rank. The
options are Disable and Enable*. (The option "Enable" can be set as default when it is
supported by the motherboard.)
ADDDC (Adaptive Double Device Data Correction) Sparing
Select Enable for Adaptive Double Device Data Correction (ADDDC) support, which will
not only provide memory error checking and correction but will also prevent the system
from issuing a performance penalty before a device fails. Please note that virtual lockstep
mode will only start to work for ADDDC after a faulty DRAM module is spared. The options
are Enable* and Disable. (The option "Enable" can be set as default when it is supported
by the motherboard.)
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected in a memory module and send the corrections to the requestor (the original
source). When this item is set to Enable, the IO hub will read and write back one cache line
every 16K cycles if there is no delay caused by internal processing. By using this method,
roughly 64 GB of memory behind the IO hub will be scrubbed every day. The options are
Enable and Disable.
Patrol Scrub Interval
Use this item to specify the number of hours (between 0 to 24) required for the system to
complete a full patrol scrubbing. Enter 0 for patrol scrubbing to be performed automatically.
The default setting is 24.
Note: This item is hidden when Patrol Scrub item is set to Disable.

IIO Confi guration
EV DFX (Device Function On-Hide) Features
When this feature is set to Enable, the EV_DFX Lock Bits that are located in a processor
will always remain clear during electric tuning. The options are Disable and Enable.
CPU1 Confi guration/CPU2 Confi guration
IOU0 (IIO PCIe Br1)
This feature confi gures the PCI-E Bifuraction setting for a PCI-E port specifi ed by the user.
The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.
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