Notes On Debug - LAPIS Semiconductor EASE1000 User Manual

5 Notes on Use of EASE1000

5.1 Notes on Debug

(1) About the execution cycle at the wait mode.
On wait mode, STEP execution may differ from the execution cycle of Go- execution.
The final check of an application program should use Go-execution.
(2) About the RAM Match Break
・The timing of RAM Match Break is after executing a maximum of 3 instruction from the instruction which
read/write access of RAM.
・The RAM Match Break of DSR (0F000H) cannot choose.
(3) About the peripheral operation during Break
The operation of the following periphera1 stops during Break.
An interrupt request will be in a suspension state and an interrupt will generate it after an emulation start.
The periphera1 which operation stops during a break
2
- I C master module
2
- I C bus unit (master / slave)
- Serial unit (SIO / UART)
- General timer
- Functional timer
- External interrupts ( A stop of a sampling clock)
- Low-speed time base counter
- DMA controller
- Analog module ( CMP / DAC / AD converter / VLS)
- Buzzer
- CRC
(4) About STOP / STOP-D / HALT / HALT-D
The state of STOP / STOP-D / HALT / HALT-D will become invalid the Force break is used in the state of
STOP / STOP-D / HALT / HALT-D.
The state of STOP / STOP-D / HALT / HALT-D is canceled by break when Break-point is set up immediately
after the instruction which sets up STOP / STOP-D / HALT / HALT-D.
(5) About Real-Time-Watch
The Real-Time-Watch of DSR (0F000H) cannot choose.
(6) About change of the register value of DTU8 debugger
・When high-speed clock operation is chosen for target LSI, the FHWUPT register cannot be changed in the SFR
window of DTU8 debugger..
・When following peripheral is changed by DTU8 debugger, it is set as LSI before an emulation start.
- CPU register: R0, R1, EA, PSW
- SFR: DSR, FCON
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EASE1000 User's Manual
Chapter 5 Notes on Use of EASE1000
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