Recommended Circuitry Using Test1_N Pin And Test0 Pin - LAPIS Semiconductor EASE1000 User Manual

On-chip emulator
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2.5.1.2.2 Recommended circuitry using TEST1_N pin and TEST0 pin

The example of a circuit connected with EASE1000 using TEST1_N pin and TEST0 pin is shown below.
- Do not connect any parts to TEST1_N pin and TEST0 pin.
- EASE1000 controls reset of a target LSI, do not reset from a RESET_N pin during debugging.
RST_OUT/SCK
Figure 2-6
FEXTEASE1000-02
EASE1000
Interface connector
1
VTref
5
7
SDATA
13
3.3VOUT
9
VDDL
2,4,6,8,10,12
Vss
3,11,14
NC
Recommended circuitry using TEST1_N pin and TEST0 pin
EASE1000 User's Manual
General Description
Chapter 2
Target LSI
V
DD
TEST1_N
TEST0
RESET_N
VDDL
Vss
8

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