Zynq UltraScale+ User Manual page 8

The RF-ADCs and RF-DACs are organized into tiles, each containing either two or four
RF-ADCs or four RF-DACs (see
the necessary clock handling logic and distribution routing for the analog and digital logic.
X-Ref Target - Figure 1-2
s03_axis
Data Path 3
s02_axis
Data Path 2
IP State
Machine
s01_axis
Data Path 1
s00_axis
Data Path 0
6.4 GSPS RF-DAC Tile
For device specifications and additional information, see:
• Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889)
• Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
[Ref 2]
• Zynq UltraScale+ Device Technical Reference Manual (UG1085)
RFSoC Data Converter Evaluation Tool User Guide
UG1287 (v2018.2) October 1, 2018
Figure 1-2). Each tile also includes a block with a PLL and all
m13_axis
DAC3
m12_axis
DAC2
IP State
Machine
m11_axis
DAC1
m10_axis
DAC0
DAC_X0Y0
Figure 1-2: Converter Tile Structure
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Data Path 3 ADC3
Data Path 2 ADC2
IP State
Machine
Data Path 1 ADC1
Data Path 0 ADC0
ADC_X0Y1
2 GSPS RF-ADC Tile
[Ref 1]
Chapter 1: Introduction
m03_axis
Data Path 1
ADC1
m02_axis
(23)
(23)
m01_axis
Data Path 0
ADC0
m00_axis (01)
(01)
ADC_X0Y0
4 GSPS RF-ADC Tile
X21300-090918
[Ref 3].
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