Zynq UltraScale+ User Manual page 29

this signal is overridden with a global start/stop signal which is generated using Channel
Select of the Master DAC block, i.e., tile 0 block 0. This signal selection is controlled using
multi-tile mode select.
X-Ref Target - Figure 4-4
Example:
Fs = 3.2 GHz
Decimation = x1
SYREF = 8 MHz
PL SYSREF = 8 MHz
PL REF CLK = 200 MHz
PL CLK = 400 MHz
333 MHz
PL DDR +
DMA
MIG
GP
PS
IO
PL SYSREF (PCB)
PL REF CLK (PCB)
User_sysref_adc
MMCM
(Fabric Clock)
RFSoC Data Converter Evaluation Tool User Guide
UG1287 (v2018.2) October 1, 2018
AXIS FIFO
64 KS
AXIS FIFO
64 KS
To Tile0
channels
Stream
Mux
To Tile2
channels
AXIS FIFO
64 KS
PL CLK
AXIS FIFO
64 KS
Figure 4-4: RF-ADC Multi-Tile Sync Clocking Structure
www.xilinx.com
Multi-Tile Control
PL CLK
Tile0 _ADC_Clock out
Tile0_clk
I & Q
Merge
I & Q
Merge
To Tile1
channels
PL
Sync logic
CLK
To Tile3
channels
Multi-Tile Control
PL CLK
Tile3_clk
Tile3 _ADC_Clock out
I & Q
Merge
I & Q
Merge
Chapter 4: Clocking
PLL
ADC 0
ADC 0 Analog Clock (PCB)
Tile 0
ADC 1
ADC 2
ADC 1 Analog Clock (PCB)
Tile 1
ADC 3
SYSREF (PCB)
User_sysref_dac (Fabric Clock)
ADC 4
ADC 2 Analog Clock (PCB)
Tile 2
ADC 5
PLL
ADC 6
ADC 3 Analog Clock (PCB)
Tile 3
ADC 7
Send Feedback
X21247-092118
29