Zynq UltraScale+ User Manual page 25

Table 3-2: Control Signals (Cont'd)
DAC
DAC0 Loopback select
DAC1 Memory Loopback Reset
DAC1 Loopback select
DAC1 Channel Control
DAC2 Loopback select
DAC2 Memory Loopback Reset
DAC3 Loopback select
DAC2 Channel Control
DAC4 Loopback select
DAC3 Memory Loopback Reset
DAC5 Loopback select
DAC3 Channel Control
DAC6 Loopback select
DAC4 Memory Loopback Reset
DAC7 Loopback select
DAC4 Channel Control
Reserved
DAC5 Memory Loopback Reset
Reserved
DAC5 Channel Control
Reserved
DAC6 Memory Loopback Reset
Reserved
DAC6 Channel Control
Reserved
DAC7 Memory Loopback Reset
Reserved
DAC7 Channel Control
Reserved
RFSoC Data Converter Evaluation Tool User Guide
UG1287 (v2018.2) October 1, 2018
ADC
3 Reserved
4 ADC0203 FIFO Reset
5 ADC0203_IQ_Merge_sel
6 ADC0203 Channel Control
7 Reserved
8 ADC1011 FIFO Reset
9 ADC1011_IQ_Merge_sel
10 ADC1011 Channel Control
11 Reserved
12 ADC1213 FIFO Reset
13 ADC1213_IQ_Merge_sel
14 ADC1213 Channel Control
15 Reserved
16 ADC2021 FIFO Reset
17 ADC2021_IQ_Merge_sel
18 ADC2021 Channel Control
19 Reserved
20 ADC2223 FIFO Reset
21 ADC2223_IQ_Merge_sel
22 ADC2223 Channel Control
23 Reserved
24 ADC3031 FIFO Reset
25 ADC3031_IQ_Merge_sel
26 ADC3031 Channel Control
27 Reserved
28 ADC3132 FIFO Reset
29 ADC3132_IQ_Merge_sel
30 ADC3132 Channel Control
31 Reserved
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Chapter 3: Hardware Design
Common
35 Reserved
36 DAC Multi Tile Select
37 Reserved
38 Reserved
39 Reserved
40 ADC Channel Mux
select
41 Reserved
42 ADC Multi Tile Select
43 ADC Fabric Filter
Select
44 DAC Fabric Filter
Select
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Send Feedback
67
68
69
70
79:71
82:80
83
84
90
91
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